1/*
2 * Copyright (C) 2016 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/*
18  Art assembly interpreter notes:
19
20  First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't
21  handle invoke, allows higher-level code to create frame & shadow frame.
22
23  Once that's working, support direct entry code & eliminate shadow frame (and
24  excess locals allocation.
25
26  Some (hopefully) temporary ugliness.  We'll treat rFP as pointing to the
27  base of the vreg array within the shadow frame.  Access the other fields,
28  dex_pc_, method_ and number_of_vregs_ via negative offsets.  For now, we'll continue
29  the shadow frame mechanism of double-storing object references - via rFP &
30  number_of_vregs_.
31
32 */
33
34/*
35x86 ABI general notes:
36
37Caller save set:
38   eax, edx, ecx, st(0)-st(7)
39Callee save set:
40   ebx, esi, edi, ebp
41Return regs:
42   32-bit in eax
43   64-bit in edx:eax (low-order 32 in eax)
44   fp on top of fp stack st(0)
45
46Parameters passed on stack, pushed right-to-left.  On entry to target, first
47parm is at 4(%esp).  Traditional entry code is:
48
49functEntry:
50    push    %ebp             # save old frame pointer
51    mov     %ebp,%esp        # establish new frame pointer
52    sub     FrameSize,%esp   # Allocate storage for spill, locals & outs
53
54Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp)
55
56Stack must be 16-byte aligned to support SSE in native code.
57
58If we're not doing variable stack allocation (alloca), the frame pointer can be
59eliminated and all arg references adjusted to be esp relative.
60*/
61
62/*
63Mterp and x86 notes:
64
65Some key interpreter variables will be assigned to registers.
66
67  nick     reg   purpose
68  rPC      esi   interpreted program counter, used for fetching instructions
69  rFP      edi   interpreted frame pointer, used for accessing locals and args
70  rINSTw   bx    first 16-bit code of current instruction
71  rINSTbl  bl    opcode portion of instruction word
72  rINSTbh  bh    high byte of inst word, usually contains src/tgt reg names
73  rIBASE   edx   base of instruction handler table
74  rREFS    ebp   base of object references in shadow frame.
75
76Notes:
77   o High order 16 bits of ebx must be zero on entry to handler
78   o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit
79   o eax and ecx are scratch, rINSTw/ebx sometimes scratch
80
81Macros are provided for common operations.  Each macro MUST emit only
82one instruction to make instruction-counting easier.  They MUST NOT alter
83unspecified registers or condition codes.
84*/
85
86/*
87 * This is a #include, not a %include, because we want the C pre-processor
88 * to expand the macros into assembler assignment statements.
89 */
90#include "asm_support.h"
91
92/*
93 * Handle mac compiler specific
94 */
95#if defined(__APPLE__)
96    #define MACRO_LITERAL(value) $$(value)
97    #define FUNCTION_TYPE(name)
98    #define SIZE(start,end)
99    // Mac OS' symbols have an _ prefix.
100    #define SYMBOL(name) _ ## name
101#else
102    #define MACRO_LITERAL(value) $$value
103    #define FUNCTION_TYPE(name) .type name, @function
104    #define SIZE(start,end) .size start, .-end
105    #define SYMBOL(name) name
106#endif
107
108.macro PUSH _reg
109    pushl \_reg
110    .cfi_adjust_cfa_offset 4
111    .cfi_rel_offset \_reg, 0
112.endm
113
114.macro POP _reg
115    popl \_reg
116    .cfi_adjust_cfa_offset -4
117    .cfi_restore \_reg
118.endm
119
120/*
121 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs.  So,
122 * to access other shadow frame fields, we need to use a backwards offset.  Define those here.
123 */
124#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET)
125#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET)
126#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET)
127#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET)
128#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
129#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
130#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
131#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
132#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET)
133#define OFF_FP_SHADOWFRAME OFF_FP(0)
134
135/* Frame size must be 16-byte aligned.
136 * Remember about 4 bytes for return address + 4 * 4 for spills
137 */
138#define FRAME_SIZE     28
139
140/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */
141#define IN_ARG3        (FRAME_SIZE + 16 + 16)
142#define IN_ARG2        (FRAME_SIZE + 16 + 12)
143#define IN_ARG1        (FRAME_SIZE + 16 +  8)
144#define IN_ARG0        (FRAME_SIZE + 16 +  4)
145/* Spill offsets relative to %esp */
146#define LOCAL0         (FRAME_SIZE -  4)
147#define LOCAL1         (FRAME_SIZE -  8)
148#define LOCAL2         (FRAME_SIZE - 12)
149/* Out Arg offsets, relative to %esp */
150#define OUT_ARG3       ( 12)
151#define OUT_ARG2       (  8)
152#define OUT_ARG1       (  4)
153#define OUT_ARG0       (  0)  /* <- ExecuteMterpImpl esp + 0 */
154
155/* During bringup, we'll use the shadow frame model instead of rFP */
156/* single-purpose registers, given names for clarity */
157#define rSELF    IN_ARG0(%esp)
158#define rPC      %esi
159#define rFP      %edi
160#define rINST    %ebx
161#define rINSTw   %bx
162#define rINSTbh  %bh
163#define rINSTbl  %bl
164#define rIBASE   %edx
165#define rREFS    %ebp
166#define rPROFILE OFF_FP_COUNTDOWN_OFFSET(rFP)
167
168#define MTERP_LOGGING 0
169
170/*
171 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects.  Must
172 * be done *before* something throws.
173 *
174 * It's okay to do this more than once.
175 *
176 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped
177 * dex byte codes.  However, the rest of the runtime expects dex pc to be an instruction
178 * offset into the code_items_[] array.  For effiency, we will "export" the
179 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC
180 * to convert to a dex pc when needed.
181 */
182.macro EXPORT_PC
183    movl    rPC, OFF_FP_DEX_PC_PTR(rFP)
184.endm
185
186/*
187 * Refresh handler table.
188 */
189.macro REFRESH_IBASE
190    movl    rSELF, rIBASE
191    movl    THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE
192.endm
193
194/*
195 * Refresh handler table.
196 * IBase handles uses the caller save register so we must restore it after each call.
197 * Also it is used as a result of some 64-bit operations (like imul) and we should
198 * restore it in such cases also.
199 *
200 * TODO: Consider spilling the IBase instead of restoring it from Thread structure.
201 */
202.macro RESTORE_IBASE
203    movl    rSELF, rIBASE
204    movl    THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE
205.endm
206
207/*
208 * If rSELF is already loaded then we can use it from known reg.
209 */
210.macro RESTORE_IBASE_FROM_SELF _reg
211    movl    THREAD_CURRENT_IBASE_OFFSET(\_reg), rIBASE
212.endm
213
214/*
215 * Refresh rINST.
216 * At enter to handler rINST does not contain the opcode number.
217 * However some utilities require the full value, so this macro
218 * restores the opcode number.
219 */
220.macro REFRESH_INST _opnum
221    movb    rINSTbl, rINSTbh
222    movb    MACRO_LITERAL(\_opnum), rINSTbl
223.endm
224
225/*
226 * Fetch the next instruction from rPC into rINSTw.  Does not advance rPC.
227 */
228.macro FETCH_INST
229    movzwl  (rPC), rINST
230.endm
231
232/*
233 * Remove opcode from rINST, compute the address of handler and jump to it.
234 */
235.macro GOTO_NEXT
236    movzx   rINSTbl,%eax
237    movzbl  rINSTbh,rINST
238    shll    MACRO_LITERAL(${handler_size_bits}), %eax
239    addl    rIBASE, %eax
240    jmp     *%eax
241.endm
242
243/*
244 * Advance rPC by instruction count.
245 */
246.macro ADVANCE_PC _count
247    leal    2*\_count(rPC), rPC
248.endm
249
250/*
251 * Advance rPC by instruction count, fetch instruction and jump to handler.
252 */
253.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count
254    ADVANCE_PC \_count
255    FETCH_INST
256    GOTO_NEXT
257.endm
258
259/*
260 * Get/set the 32-bit value from a Dalvik register.
261 */
262#define VREG_ADDRESS(_vreg) (rFP,_vreg,4)
263#define VREG_HIGH_ADDRESS(_vreg) 4(rFP,_vreg,4)
264#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4)
265#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4)
266
267.macro GET_VREG _reg _vreg
268    movl    (rFP,\_vreg,4), \_reg
269.endm
270
271/* Read wide value to xmm. */
272.macro GET_WIDE_FP_VREG _reg _vreg
273    movq    (rFP,\_vreg,4), \_reg
274.endm
275
276.macro SET_VREG _reg _vreg
277    movl    \_reg, (rFP,\_vreg,4)
278    movl    MACRO_LITERAL(0), (rREFS,\_vreg,4)
279.endm
280
281/* Write wide value from xmm. xmm is clobbered. */
282.macro SET_WIDE_FP_VREG _reg _vreg
283    movq    \_reg, (rFP,\_vreg,4)
284    pxor    \_reg, \_reg
285    movq    \_reg, (rREFS,\_vreg,4)
286.endm
287
288.macro SET_VREG_OBJECT _reg _vreg
289    movl    \_reg, (rFP,\_vreg,4)
290    movl    \_reg, (rREFS,\_vreg,4)
291.endm
292
293.macro GET_VREG_HIGH _reg _vreg
294    movl    4(rFP,\_vreg,4), \_reg
295.endm
296
297.macro SET_VREG_HIGH _reg _vreg
298    movl    \_reg, 4(rFP,\_vreg,4)
299    movl    MACRO_LITERAL(0), 4(rREFS,\_vreg,4)
300.endm
301
302.macro CLEAR_REF _vreg
303    movl    MACRO_LITERAL(0),  (rREFS,\_vreg,4)
304.endm
305
306.macro CLEAR_WIDE_REF _vreg
307    movl    MACRO_LITERAL(0),  (rREFS,\_vreg,4)
308    movl    MACRO_LITERAL(0), 4(rREFS,\_vreg,4)
309.endm
310