1//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subtarget options of a Target machine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15#define LLVM_TARGET_TARGETSUBTARGETINFO_H
16
17#include "llvm/CodeGen/PBQPRAConstraint.h"
18#include "llvm/CodeGen/SchedulerRegistry.h"
19#include "llvm/MC/MCSubtargetInfo.h"
20#include "llvm/Support/CodeGen.h"
21
22namespace llvm {
23
24class DataLayout;
25class MachineFunction;
26class MachineInstr;
27class SDep;
28class SUnit;
29class TargetFrameLowering;
30class TargetInstrInfo;
31class TargetLowering;
32class TargetRegisterClass;
33class TargetRegisterInfo;
34class TargetSchedModel;
35class TargetSelectionDAGInfo;
36struct MachineSchedPolicy;
37template <typename T> class SmallVectorImpl;
38
39//===----------------------------------------------------------------------===//
40///
41/// TargetSubtargetInfo - Generic base class for all target subtargets.  All
42/// Target-specific options that control code generation and printing should
43/// be exposed through a TargetSubtargetInfo-derived class.
44///
45class TargetSubtargetInfo : public MCSubtargetInfo {
46  TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
47  void operator=(const TargetSubtargetInfo &) = delete;
48  TargetSubtargetInfo() = delete;
49
50protected: // Can only create subclasses...
51  TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
52                      ArrayRef<SubtargetFeatureKV> PF,
53                      ArrayRef<SubtargetFeatureKV> PD,
54                      const SubtargetInfoKV *ProcSched,
55                      const MCWriteProcResEntry *WPR,
56                      const MCWriteLatencyEntry *WL,
57                      const MCReadAdvanceEntry *RA, const InstrStage *IS,
58                      const unsigned *OC, const unsigned *FP);
59
60public:
61  // AntiDepBreakMode - Type of anti-dependence breaking that should
62  // be performed before post-RA scheduling.
63  typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
64  typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector;
65
66  virtual ~TargetSubtargetInfo();
67
68  // Interfaces to the major aspects of target machine information:
69  //
70  // -- Instruction opcode and operand information
71  // -- Pipelines and scheduling information
72  // -- Stack frame information
73  // -- Selection DAG lowering information
74  //
75  // N.B. These objects may change during compilation. It's not safe to cache
76  // them between functions.
77  virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
78  virtual const TargetFrameLowering *getFrameLowering() const {
79    return nullptr;
80  }
81  virtual const TargetLowering *getTargetLowering() const { return nullptr; }
82  virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
83    return nullptr;
84  }
85  /// Target can subclass this hook to select a different DAG scheduler.
86  virtual RegisterScheduler::FunctionPassCtor
87      getDAGScheduler(CodeGenOpt::Level) const {
88    return nullptr;
89  }
90
91  /// getRegisterInfo - If register information is available, return it.  If
92  /// not, return null.  This is kept separate from RegInfo until RegInfo has
93  /// details of graph coloring register allocation removed from it.
94  ///
95  virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
96
97  /// getInstrItineraryData - Returns instruction itinerary data for the target
98  /// or specific subtarget.
99  ///
100  virtual const InstrItineraryData *getInstrItineraryData() const {
101    return nullptr;
102  }
103
104  /// Resolve a SchedClass at runtime, where SchedClass identifies an
105  /// MCSchedClassDesc with the isVariant property. This may return the ID of
106  /// another variant SchedClass, but repeated invocation must quickly terminate
107  /// in a nonvariant SchedClass.
108  virtual unsigned resolveSchedClass(unsigned SchedClass,
109                                     const MachineInstr *MI,
110                                     const TargetSchedModel *SchedModel) const {
111    return 0;
112  }
113
114  /// \brief True if the subtarget should run MachineScheduler after aggressive
115  /// coalescing.
116  ///
117  /// This currently replaces the SelectionDAG scheduler with the "source" order
118  /// scheduler (though see below for an option to turn this off and use the
119  /// TargetLowering preference). It does not yet disable the postRA scheduler.
120  virtual bool enableMachineScheduler() const;
121
122  /// \brief True if the machine scheduler should disable the TLI preference
123  /// for preRA scheduling with the source level scheduler.
124  virtual bool enableMachineSchedDefaultSched() const { return true; }
125
126  /// \brief True if the subtarget should enable joining global copies.
127  ///
128  /// By default this is enabled if the machine scheduler is enabled, but
129  /// can be overridden.
130  virtual bool enableJoinGlobalCopies() const;
131
132  /// True if the subtarget should run a scheduler after register allocation.
133  ///
134  /// By default this queries the PostRAScheduling bit in the scheduling model
135  /// which is the preferred way to influence this.
136  virtual bool enablePostRAScheduler() const;
137
138  /// \brief True if the subtarget should run the atomic expansion pass.
139  virtual bool enableAtomicExpand() const;
140
141  /// \brief Override generic scheduling policy within a region.
142  ///
143  /// This is a convenient way for targets that don't provide any custom
144  /// scheduling heuristics (no custom MachineSchedStrategy) to make
145  /// changes to the generic scheduling policy.
146  virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
147                                   MachineInstr *begin, MachineInstr *end,
148                                   unsigned NumRegionInstrs) const {}
149
150  // \brief Perform target specific adjustments to the latency of a schedule
151  // dependency.
152  virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
153
154  // For use with PostRAScheduling: get the anti-dependence breaking that should
155  // be performed before post-RA scheduling.
156  virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
157
158  // For use with PostRAScheduling: in CriticalPathRCs, return any register
159  // classes that should only be considered for anti-dependence breaking if they
160  // are on the critical path.
161  virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
162    return CriticalPathRCs.clear();
163  }
164
165  // For use with PostRAScheduling: get the minimum optimization level needed
166  // to enable post-RA scheduling.
167  virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
168    return CodeGenOpt::Default;
169  }
170
171  /// \brief True if the subtarget should run the local reassignment
172  /// heuristic of the register allocator.
173  /// This heuristic may be compile time intensive, \p OptLevel provides
174  /// a finer grain to tune the register allocator.
175  virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
176
177  /// \brief Enable use of alias analysis during code generation (during MI
178  /// scheduling, DAGCombine, etc.).
179  virtual bool useAA() const;
180
181  /// \brief Enable the use of the early if conversion pass.
182  virtual bool enableEarlyIfConversion() const { return false; }
183
184  /// \brief Return PBQPConstraint(s) for the target.
185  ///
186  /// Override to provide custom PBQP constraints.
187  virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
188    return nullptr;
189  }
190
191  /// Enable tracking of subregister liveness in register allocator.
192  virtual bool enableSubRegLiveness() const { return false; }
193};
194
195} // End llvm namespace
196
197#endif
198