1//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the RegisterClassInfo class which provides dynamic
11// information about target register classes. Callee-saved vs. caller-saved and
12// reserved registers depend on calling conventions and other dynamic
13// information, so some things cannot be determined statically.
14//
15//===----------------------------------------------------------------------===//
16
17#include "llvm/CodeGen/RegisterClassInfo.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "regalloc"
27
28static cl::opt<unsigned>
29StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
30         cl::desc("Limit all regclasses to N registers"));
31
32RegisterClassInfo::RegisterClassInfo()
33  : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
34
35void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
36  bool Update = false;
37  MF = &mf;
38
39  // Allocate new array the first time we see a new target.
40  if (MF->getSubtarget().getRegisterInfo() != TRI) {
41    TRI = MF->getSubtarget().getRegisterInfo();
42    RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
43    unsigned NumPSets = TRI->getNumRegPressureSets();
44    PSetLimits.reset(new unsigned[NumPSets]);
45    std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
46    Update = true;
47  }
48
49  // Does this MF have different CSRs?
50  assert(TRI && "no register info set");
51  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
52  if (Update || CSR != CalleeSaved) {
53    // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
54    // overlapping CSR.
55    CSRNum.clear();
56    CSRNum.resize(TRI->getNumRegs(), 0);
57    for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
58      for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
59        CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
60    Update = true;
61  }
62  CalleeSaved = CSR;
63
64  // Different reserved registers?
65  const BitVector &RR = MF->getRegInfo().getReservedRegs();
66  if (Reserved.size() != RR.size() || RR != Reserved) {
67    Update = true;
68    Reserved = RR;
69  }
70
71  // Invalidate cached information from previous function.
72  if (Update)
73    ++Tag;
74}
75
76/// compute - Compute the preferred allocation order for RC with reserved
77/// registers filtered out. Volatile registers come first followed by CSR
78/// aliases ordered according to the CSR order specified by the target.
79void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
80  assert(RC && "no register class given");
81  RCInfo &RCI = RegClass[RC->getID()];
82
83  // Raw register count, including all reserved regs.
84  unsigned NumRegs = RC->getNumRegs();
85
86  if (!RCI.Order)
87    RCI.Order.reset(new MCPhysReg[NumRegs]);
88
89  unsigned N = 0;
90  SmallVector<MCPhysReg, 16> CSRAlias;
91  unsigned MinCost = 0xff;
92  unsigned LastCost = ~0u;
93  unsigned LastCostChange = 0;
94
95  // FIXME: Once targets reserve registers instead of removing them from the
96  // allocation order, we can simply use begin/end here.
97  ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
98  for (unsigned i = 0; i != RawOrder.size(); ++i) {
99    unsigned PhysReg = RawOrder[i];
100    // Remove reserved registers from the allocation order.
101    if (Reserved.test(PhysReg))
102      continue;
103    unsigned Cost = TRI->getCostPerUse(PhysReg);
104    MinCost = std::min(MinCost, Cost);
105
106    if (CSRNum[PhysReg])
107      // PhysReg aliases a CSR, save it for later.
108      CSRAlias.push_back(PhysReg);
109    else {
110      if (Cost != LastCost)
111        LastCostChange = N;
112      RCI.Order[N++] = PhysReg;
113      LastCost = Cost;
114    }
115  }
116  RCI.NumRegs = N + CSRAlias.size();
117  assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
118
119  // CSR aliases go after the volatile registers, preserve the target's order.
120  for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
121    unsigned PhysReg = CSRAlias[i];
122    unsigned Cost = TRI->getCostPerUse(PhysReg);
123    if (Cost != LastCost)
124      LastCostChange = N;
125    RCI.Order[N++] = PhysReg;
126    LastCost = Cost;
127  }
128
129  // Register allocator stress test.  Clip register class to N registers.
130  if (StressRA && RCI.NumRegs > StressRA)
131    RCI.NumRegs = StressRA;
132
133  // Check if RC is a proper sub-class.
134  if (const TargetRegisterClass *Super =
135          TRI->getLargestLegalSuperClass(RC, *MF))
136    if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
137      RCI.ProperSubClass = true;
138
139  RCI.MinCost = uint8_t(MinCost);
140  RCI.LastCostChange = LastCostChange;
141
142  DEBUG({
143    dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
144    for (unsigned I = 0; I != RCI.NumRegs; ++I)
145      dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
146    dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
147  });
148
149  // RCI is now up-to-date.
150  RCI.Tag = Tag;
151}
152
153/// This is not accurate because two overlapping register sets may have some
154/// nonoverlapping reserved registers. However, computing the allocation order
155/// for all register classes would be too expensive.
156unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
157  const TargetRegisterClass *RC = nullptr;
158  unsigned NumRCUnits = 0;
159  for (TargetRegisterInfo::regclass_iterator
160         RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) {
161    const int *PSetID = TRI->getRegClassPressureSets(*RI);
162    for (; *PSetID != -1; ++PSetID) {
163      if ((unsigned)*PSetID == Idx)
164        break;
165    }
166    if (*PSetID == -1)
167      continue;
168
169    // Found a register class that counts against this pressure set.
170    // For efficiency, only compute the set order for the largest set.
171    unsigned NUnits = TRI->getRegClassWeight(*RI).WeightLimit;
172    if (!RC || NUnits > NumRCUnits) {
173      RC = *RI;
174      NumRCUnits = NUnits;
175    }
176  }
177  compute(RC);
178  unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
179  return TRI->getRegPressureSetLimit(*MF, Idx) -
180         TRI->getRegClassWeight(RC).RegWeight * NReserved;
181}
182