1//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This defines functionality used to emit comments about X86 instructions to
11// an output stream for -fverbose-asm.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86InstComments.h"
16#include "MCTargetDesc/X86MCTargetDesc.h"
17#include "Utils/X86ShuffleDecode.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/CodeGen/MachineValueType.h"
20#include "llvm/Support/raw_ostream.h"
21
22using namespace llvm;
23
24static unsigned getVectorRegSize(unsigned RegNo) {
25  if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
26    return 512;
27  if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
28    return 256;
29  if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
30    return 128;
31  if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
32    return 64;
33
34  llvm_unreachable("Unknown vector reg!");
35  return 0;
36}
37
38static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
39                                 unsigned OperandIndex) {
40  unsigned OpReg = MI->getOperand(OperandIndex).getReg();
41  return MVT::getVectorVT(ScalarVT,
42                          getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
43}
44
45/// \brief Extracts the src/dst types for a given zero extension instruction.
46/// \note While the number of elements in DstVT type correct, the
47/// number in the SrcVT type is expanded to fill the src xmm register and the
48/// upper elements may not be included in the dst xmm/ymm register.
49static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
50  switch (MI->getOpcode()) {
51  default:
52    llvm_unreachable("Unknown zero extension instruction");
53  // i8 zero extension
54  case X86::PMOVZXBWrm:
55  case X86::PMOVZXBWrr:
56  case X86::VPMOVZXBWrm:
57  case X86::VPMOVZXBWrr:
58    SrcVT = MVT::v16i8;
59    DstVT = MVT::v8i16;
60    break;
61  case X86::VPMOVZXBWYrm:
62  case X86::VPMOVZXBWYrr:
63    SrcVT = MVT::v16i8;
64    DstVT = MVT::v16i16;
65    break;
66  case X86::PMOVZXBDrm:
67  case X86::PMOVZXBDrr:
68  case X86::VPMOVZXBDrm:
69  case X86::VPMOVZXBDrr:
70    SrcVT = MVT::v16i8;
71    DstVT = MVT::v4i32;
72    break;
73  case X86::VPMOVZXBDYrm:
74  case X86::VPMOVZXBDYrr:
75    SrcVT = MVT::v16i8;
76    DstVT = MVT::v8i32;
77    break;
78  case X86::PMOVZXBQrm:
79  case X86::PMOVZXBQrr:
80  case X86::VPMOVZXBQrm:
81  case X86::VPMOVZXBQrr:
82    SrcVT = MVT::v16i8;
83    DstVT = MVT::v2i64;
84    break;
85  case X86::VPMOVZXBQYrm:
86  case X86::VPMOVZXBQYrr:
87    SrcVT = MVT::v16i8;
88    DstVT = MVT::v4i64;
89    break;
90  // i16 zero extension
91  case X86::PMOVZXWDrm:
92  case X86::PMOVZXWDrr:
93  case X86::VPMOVZXWDrm:
94  case X86::VPMOVZXWDrr:
95    SrcVT = MVT::v8i16;
96    DstVT = MVT::v4i32;
97    break;
98  case X86::VPMOVZXWDYrm:
99  case X86::VPMOVZXWDYrr:
100    SrcVT = MVT::v8i16;
101    DstVT = MVT::v8i32;
102    break;
103  case X86::PMOVZXWQrm:
104  case X86::PMOVZXWQrr:
105  case X86::VPMOVZXWQrm:
106  case X86::VPMOVZXWQrr:
107    SrcVT = MVT::v8i16;
108    DstVT = MVT::v2i64;
109    break;
110  case X86::VPMOVZXWQYrm:
111  case X86::VPMOVZXWQYrr:
112    SrcVT = MVT::v8i16;
113    DstVT = MVT::v4i64;
114    break;
115  // i32 zero extension
116  case X86::PMOVZXDQrm:
117  case X86::PMOVZXDQrr:
118  case X86::VPMOVZXDQrm:
119  case X86::VPMOVZXDQrr:
120    SrcVT = MVT::v4i32;
121    DstVT = MVT::v2i64;
122    break;
123  case X86::VPMOVZXDQYrm:
124  case X86::VPMOVZXDQYrr:
125    SrcVT = MVT::v4i32;
126    DstVT = MVT::v4i64;
127    break;
128  }
129}
130
131#define CASE_MASK_INS_COMMON(Inst, Suffix, src)  \
132  case X86::V##Inst##Suffix##src:                \
133  case X86::V##Inst##Suffix##src##k:             \
134  case X86::V##Inst##Suffix##src##kz:
135
136#define CASE_SSE_INS_COMMON(Inst, src)           \
137  case X86::Inst##src:
138
139#define CASE_AVX_INS_COMMON(Inst, Suffix, src)  \
140  case X86::V##Inst##Suffix##src:
141
142#define CASE_MOVDUP(Inst, src)                  \
143  CASE_MASK_INS_COMMON(Inst, Z, r##src)         \
144  CASE_MASK_INS_COMMON(Inst, Z256, r##src)      \
145  CASE_MASK_INS_COMMON(Inst, Z128, r##src)      \
146  CASE_AVX_INS_COMMON(Inst, , r##src)           \
147  CASE_AVX_INS_COMMON(Inst, Y, r##src)          \
148  CASE_SSE_INS_COMMON(Inst, r##src)             \
149
150#define CASE_UNPCK(Inst, src)                   \
151  CASE_MASK_INS_COMMON(Inst, Z, r##src)         \
152  CASE_MASK_INS_COMMON(Inst, Z256, r##src)      \
153  CASE_MASK_INS_COMMON(Inst, Z128, r##src)      \
154  CASE_AVX_INS_COMMON(Inst, , r##src)           \
155  CASE_AVX_INS_COMMON(Inst, Y, r##src)          \
156  CASE_SSE_INS_COMMON(Inst, r##src)             \
157
158#define CASE_SHUF(Inst, src)                    \
159  CASE_MASK_INS_COMMON(Inst, Z, r##src##i)      \
160  CASE_MASK_INS_COMMON(Inst, Z256, r##src##i)   \
161  CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)   \
162  CASE_AVX_INS_COMMON(Inst, , r##src##i)        \
163  CASE_AVX_INS_COMMON(Inst, Y, r##src##i)       \
164  CASE_SSE_INS_COMMON(Inst, r##src##i)          \
165
166#define CASE_VPERM(Inst, src)                   \
167  CASE_MASK_INS_COMMON(Inst, Z, src##i)         \
168  CASE_MASK_INS_COMMON(Inst, Z256, src##i)      \
169  CASE_MASK_INS_COMMON(Inst, Z128, src##i)      \
170  CASE_AVX_INS_COMMON(Inst, , src##i)           \
171  CASE_AVX_INS_COMMON(Inst, Y, src##i)          \
172
173#define CASE_VSHUF(Inst, src)                          \
174  CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i)      \
175  CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i)      \
176  CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i)   \
177  CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)   \
178
179/// \brief Extracts the types and if it has memory operand for a given
180/// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
181static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
182  HasMemOp = false;
183  switch (MI->getOpcode()) {
184  default:
185    llvm_unreachable("Unknown VSHUF64x2 family instructions.");
186    break;
187  CASE_VSHUF(64X2, m)
188    HasMemOp = true;        // FALL THROUGH.
189  CASE_VSHUF(64X2, r)
190    VT = getRegOperandVectorVT(MI, MVT::i64, 0);
191    break;
192  CASE_VSHUF(32X4, m)
193    HasMemOp = true;        // FALL THROUGH.
194  CASE_VSHUF(32X4, r)
195    VT = getRegOperandVectorVT(MI, MVT::i32, 0);
196    break;
197  }
198}
199
200//===----------------------------------------------------------------------===//
201// Top Level Entrypoint
202//===----------------------------------------------------------------------===//
203
204/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
205/// newline terminated strings to the specified string if desired.  This
206/// information is shown in disassembly dumps when verbose assembly is enabled.
207bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
208                                  const char *(*getRegName)(unsigned)) {
209  // If this is a shuffle operation, the switch should fill in this state.
210  SmallVector<int, 8> ShuffleMask;
211  const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
212
213  switch (MI->getOpcode()) {
214  default:
215    // Not an instruction for which we can decode comments.
216    return false;
217
218  case X86::BLENDPDrri:
219  case X86::VBLENDPDrri:
220  case X86::VBLENDPDYrri:
221    Src2Name = getRegName(MI->getOperand(2).getReg());
222    // FALL THROUGH.
223  case X86::BLENDPDrmi:
224  case X86::VBLENDPDrmi:
225  case X86::VBLENDPDYrmi:
226    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
227      DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
228                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
229                      ShuffleMask);
230    Src1Name = getRegName(MI->getOperand(1).getReg());
231    DestName = getRegName(MI->getOperand(0).getReg());
232    break;
233
234  case X86::BLENDPSrri:
235  case X86::VBLENDPSrri:
236  case X86::VBLENDPSYrri:
237    Src2Name = getRegName(MI->getOperand(2).getReg());
238    // FALL THROUGH.
239  case X86::BLENDPSrmi:
240  case X86::VBLENDPSrmi:
241  case X86::VBLENDPSYrmi:
242    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
243      DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
244                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
245                      ShuffleMask);
246    Src1Name = getRegName(MI->getOperand(1).getReg());
247    DestName = getRegName(MI->getOperand(0).getReg());
248    break;
249
250  case X86::PBLENDWrri:
251  case X86::VPBLENDWrri:
252  case X86::VPBLENDWYrri:
253    Src2Name = getRegName(MI->getOperand(2).getReg());
254    // FALL THROUGH.
255  case X86::PBLENDWrmi:
256  case X86::VPBLENDWrmi:
257  case X86::VPBLENDWYrmi:
258    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
259      DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
260                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
261                      ShuffleMask);
262    Src1Name = getRegName(MI->getOperand(1).getReg());
263    DestName = getRegName(MI->getOperand(0).getReg());
264    break;
265
266  case X86::VPBLENDDrri:
267  case X86::VPBLENDDYrri:
268    Src2Name = getRegName(MI->getOperand(2).getReg());
269    // FALL THROUGH.
270  case X86::VPBLENDDrmi:
271  case X86::VPBLENDDYrmi:
272    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
273      DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
274                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
275                      ShuffleMask);
276    Src1Name = getRegName(MI->getOperand(1).getReg());
277    DestName = getRegName(MI->getOperand(0).getReg());
278    break;
279
280  case X86::INSERTPSrr:
281  case X86::VINSERTPSrr:
282    Src2Name = getRegName(MI->getOperand(2).getReg());
283    // FALL THROUGH.
284  case X86::INSERTPSrm:
285  case X86::VINSERTPSrm:
286    DestName = getRegName(MI->getOperand(0).getReg());
287    Src1Name = getRegName(MI->getOperand(1).getReg());
288    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
289      DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
290                         ShuffleMask);
291    break;
292
293  case X86::MOVLHPSrr:
294  case X86::VMOVLHPSrr:
295  case X86::VMOVLHPSZrr:
296    Src2Name = getRegName(MI->getOperand(2).getReg());
297    Src1Name = getRegName(MI->getOperand(1).getReg());
298    DestName = getRegName(MI->getOperand(0).getReg());
299    DecodeMOVLHPSMask(2, ShuffleMask);
300    break;
301
302  case X86::MOVHLPSrr:
303  case X86::VMOVHLPSrr:
304  case X86::VMOVHLPSZrr:
305    Src2Name = getRegName(MI->getOperand(2).getReg());
306    Src1Name = getRegName(MI->getOperand(1).getReg());
307    DestName = getRegName(MI->getOperand(0).getReg());
308    DecodeMOVHLPSMask(2, ShuffleMask);
309    break;
310
311  CASE_MOVDUP(MOVSLDUP, r)
312    Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
313    // FALL THROUGH.
314  CASE_MOVDUP(MOVSLDUP, m)
315    DestName = getRegName(MI->getOperand(0).getReg());
316    DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
317    break;
318
319  CASE_MOVDUP(MOVSHDUP, r)
320    Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
321    // FALL THROUGH.
322  CASE_MOVDUP(MOVSHDUP, m)
323    DestName = getRegName(MI->getOperand(0).getReg());
324    DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
325    break;
326
327  CASE_MOVDUP(MOVDDUP, r)
328    Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
329    // FALL THROUGH.
330  CASE_MOVDUP(MOVDDUP, m)
331    DestName = getRegName(MI->getOperand(0).getReg());
332    DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
333    break;
334
335  case X86::PSLLDQri:
336  case X86::VPSLLDQri:
337  case X86::VPSLLDQYri:
338    Src1Name = getRegName(MI->getOperand(1).getReg());
339    DestName = getRegName(MI->getOperand(0).getReg());
340    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
341      DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
342                       MI->getOperand(MI->getNumOperands() - 1).getImm(),
343                       ShuffleMask);
344    break;
345
346  case X86::PSRLDQri:
347  case X86::VPSRLDQri:
348  case X86::VPSRLDQYri:
349    Src1Name = getRegName(MI->getOperand(1).getReg());
350    DestName = getRegName(MI->getOperand(0).getReg());
351    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
352      DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
353                       MI->getOperand(MI->getNumOperands() - 1).getImm(),
354                       ShuffleMask);
355    break;
356
357  case X86::PALIGNR128rr:
358  case X86::VPALIGNR128rr:
359  case X86::VPALIGNR256rr:
360    Src1Name = getRegName(MI->getOperand(2).getReg());
361    // FALL THROUGH.
362  case X86::PALIGNR128rm:
363  case X86::VPALIGNR128rm:
364  case X86::VPALIGNR256rm:
365    Src2Name = getRegName(MI->getOperand(1).getReg());
366    DestName = getRegName(MI->getOperand(0).getReg());
367    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
368      DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
369                        MI->getOperand(MI->getNumOperands() - 1).getImm(),
370                        ShuffleMask);
371    break;
372
373  case X86::PSHUFDri:
374  case X86::VPSHUFDri:
375  case X86::VPSHUFDYri:
376    Src1Name = getRegName(MI->getOperand(1).getReg());
377    // FALL THROUGH.
378  case X86::PSHUFDmi:
379  case X86::VPSHUFDmi:
380  case X86::VPSHUFDYmi:
381    DestName = getRegName(MI->getOperand(0).getReg());
382    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
383      DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
384                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
385                      ShuffleMask);
386    break;
387
388  case X86::PSHUFHWri:
389  case X86::VPSHUFHWri:
390  case X86::VPSHUFHWYri:
391    Src1Name = getRegName(MI->getOperand(1).getReg());
392    // FALL THROUGH.
393  case X86::PSHUFHWmi:
394  case X86::VPSHUFHWmi:
395  case X86::VPSHUFHWYmi:
396    DestName = getRegName(MI->getOperand(0).getReg());
397    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
398      DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
399                        MI->getOperand(MI->getNumOperands() - 1).getImm(),
400                        ShuffleMask);
401    break;
402
403  case X86::PSHUFLWri:
404  case X86::VPSHUFLWri:
405  case X86::VPSHUFLWYri:
406    Src1Name = getRegName(MI->getOperand(1).getReg());
407    // FALL THROUGH.
408  case X86::PSHUFLWmi:
409  case X86::VPSHUFLWmi:
410  case X86::VPSHUFLWYmi:
411    DestName = getRegName(MI->getOperand(0).getReg());
412    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
413      DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
414                        MI->getOperand(MI->getNumOperands() - 1).getImm(),
415                        ShuffleMask);
416    break;
417
418  case X86::MMX_PSHUFWri:
419    Src1Name = getRegName(MI->getOperand(1).getReg());
420    // FALL THROUGH.
421  case X86::MMX_PSHUFWmi:
422    DestName = getRegName(MI->getOperand(0).getReg());
423    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
424      DecodePSHUFMask(MVT::v4i16,
425                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
426                      ShuffleMask);
427    break;
428
429  case X86::PSWAPDrr:
430    Src1Name = getRegName(MI->getOperand(1).getReg());
431    // FALL THROUGH.
432  case X86::PSWAPDrm:
433    DestName = getRegName(MI->getOperand(0).getReg());
434    DecodePSWAPMask(MVT::v2i32, ShuffleMask);
435    break;
436
437  CASE_UNPCK(PUNPCKHBW, r)
438  case X86::MMX_PUNPCKHBWirr:
439    Src2Name = getRegName(MI->getOperand(2).getReg());
440    // FALL THROUGH.
441  CASE_UNPCK(PUNPCKHBW, m)
442  case X86::MMX_PUNPCKHBWirm:
443    Src1Name = getRegName(MI->getOperand(1).getReg());
444    DestName = getRegName(MI->getOperand(0).getReg());
445    DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
446    break;
447
448  CASE_UNPCK(PUNPCKHWD, r)
449  case X86::MMX_PUNPCKHWDirr:
450    Src2Name = getRegName(MI->getOperand(2).getReg());
451    // FALL THROUGH.
452  CASE_UNPCK(PUNPCKHWD, m)
453  case X86::MMX_PUNPCKHWDirm:
454    Src1Name = getRegName(MI->getOperand(1).getReg());
455    DestName = getRegName(MI->getOperand(0).getReg());
456    DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
457    break;
458
459  CASE_UNPCK(PUNPCKHDQ, r)
460  case X86::MMX_PUNPCKHDQirr:
461    Src2Name = getRegName(MI->getOperand(2).getReg());
462    // FALL THROUGH.
463  CASE_UNPCK(PUNPCKHDQ, m)
464  case X86::MMX_PUNPCKHDQirm:
465    Src1Name = getRegName(MI->getOperand(1).getReg());
466    DestName = getRegName(MI->getOperand(0).getReg());
467    DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
468    break;
469
470  CASE_UNPCK(PUNPCKHQDQ, r)
471    Src2Name = getRegName(MI->getOperand(2).getReg());
472    // FALL THROUGH.
473  CASE_UNPCK(PUNPCKHQDQ, m)
474    Src1Name = getRegName(MI->getOperand(1).getReg());
475    DestName = getRegName(MI->getOperand(0).getReg());
476    DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
477    break;
478
479  CASE_UNPCK(PUNPCKLBW, r)
480  case X86::MMX_PUNPCKLBWirr:
481    Src2Name = getRegName(MI->getOperand(2).getReg());
482    // FALL THROUGH.
483  CASE_UNPCK(PUNPCKLBW, m)
484  case X86::MMX_PUNPCKLBWirm:
485    Src1Name = getRegName(MI->getOperand(1).getReg());
486    DestName = getRegName(MI->getOperand(0).getReg());
487    DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
488    break;
489
490  CASE_UNPCK(PUNPCKLWD, r)
491  case X86::MMX_PUNPCKLWDirr:
492    Src2Name = getRegName(MI->getOperand(2).getReg());
493    // FALL THROUGH.
494  CASE_UNPCK(PUNPCKLWD, m)
495  case X86::MMX_PUNPCKLWDirm:
496    Src1Name = getRegName(MI->getOperand(1).getReg());
497    DestName = getRegName(MI->getOperand(0).getReg());
498    DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
499    break;
500
501  CASE_UNPCK(PUNPCKLDQ, r)
502  case X86::MMX_PUNPCKLDQirr:
503    Src2Name = getRegName(MI->getOperand(2).getReg());
504    // FALL THROUGH.
505  CASE_UNPCK(PUNPCKLDQ, m)
506  case X86::MMX_PUNPCKLDQirm:
507    Src1Name = getRegName(MI->getOperand(1).getReg());
508    DestName = getRegName(MI->getOperand(0).getReg());
509    DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
510    break;
511
512  CASE_UNPCK(PUNPCKLQDQ, r)
513    Src2Name = getRegName(MI->getOperand(2).getReg());
514    // FALL THROUGH.
515  CASE_UNPCK(PUNPCKLQDQ, m)
516    Src1Name = getRegName(MI->getOperand(1).getReg());
517    DestName = getRegName(MI->getOperand(0).getReg());
518    DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
519    break;
520
521  CASE_SHUF(SHUFPD, r)
522    Src2Name = getRegName(MI->getOperand(2).getReg());
523    // FALL THROUGH.
524  CASE_SHUF(SHUFPD, m)
525    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
526      DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
527                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
528                      ShuffleMask);
529    Src1Name = getRegName(MI->getOperand(1).getReg());
530    DestName = getRegName(MI->getOperand(0).getReg());
531    break;
532
533  CASE_SHUF(SHUFPS, r)
534    Src2Name = getRegName(MI->getOperand(2).getReg());
535    // FALL THROUGH.
536  CASE_SHUF(SHUFPS, m)
537    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
538      DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
539                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
540                      ShuffleMask);
541    Src1Name = getRegName(MI->getOperand(1).getReg());
542    DestName = getRegName(MI->getOperand(0).getReg());
543    break;
544
545  CASE_VSHUF(64X2, r)
546  CASE_VSHUF(64X2, m)
547  CASE_VSHUF(32X4, r)
548  CASE_VSHUF(32X4, m) {
549    MVT VT;
550    bool HasMemOp;
551    unsigned NumOp = MI->getNumOperands();
552    getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
553    decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
554                              ShuffleMask);
555    DestName = getRegName(MI->getOperand(0).getReg());
556    if (HasMemOp) {
557      assert((NumOp >= 8) && "Expected at least 8 operands!");
558      Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
559    } else {
560      assert((NumOp >= 4) && "Expected at least 4 operands!");
561      Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
562      Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
563    }
564    break;
565  }
566
567  CASE_UNPCK(UNPCKLPD, r)
568    Src2Name = getRegName(MI->getOperand(2).getReg());
569    // FALL THROUGH.
570  CASE_UNPCK(UNPCKLPD, m)
571    DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
572    Src1Name = getRegName(MI->getOperand(1).getReg());
573    DestName = getRegName(MI->getOperand(0).getReg());
574    break;
575
576  CASE_UNPCK(UNPCKLPS, r)
577    Src2Name = getRegName(MI->getOperand(2).getReg());
578    // FALL THROUGH.
579  CASE_UNPCK(UNPCKLPS, m)
580    DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
581    Src1Name = getRegName(MI->getOperand(1).getReg());
582    DestName = getRegName(MI->getOperand(0).getReg());
583    break;
584
585  CASE_UNPCK(UNPCKHPD, r)
586    Src2Name = getRegName(MI->getOperand(2).getReg());
587    // FALL THROUGH.
588  CASE_UNPCK(UNPCKHPD, m)
589    DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
590    Src1Name = getRegName(MI->getOperand(1).getReg());
591    DestName = getRegName(MI->getOperand(0).getReg());
592    break;
593
594  CASE_UNPCK(UNPCKHPS, r)
595    Src2Name = getRegName(MI->getOperand(2).getReg());
596    // FALL THROUGH.
597  CASE_UNPCK(UNPCKHPS, m)
598    DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
599    Src1Name = getRegName(MI->getOperand(1).getReg());
600    DestName = getRegName(MI->getOperand(0).getReg());
601    break;
602
603  CASE_VPERM(PERMILPS, r)
604    Src1Name = getRegName(MI->getOperand(1).getReg());
605    // FALL THROUGH.
606  CASE_VPERM(PERMILPS, m)
607    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
608      DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
609                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
610                      ShuffleMask);
611    DestName = getRegName(MI->getOperand(0).getReg());
612    break;
613
614  CASE_VPERM(PERMILPD, r)
615    Src1Name = getRegName(MI->getOperand(1).getReg());
616    // FALL THROUGH.
617  CASE_VPERM(PERMILPD, m)
618    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
619      DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
620                      MI->getOperand(MI->getNumOperands() - 1).getImm(),
621                      ShuffleMask);
622    DestName = getRegName(MI->getOperand(0).getReg());
623    break;
624
625  case X86::VPERM2F128rr:
626  case X86::VPERM2I128rr:
627    Src2Name = getRegName(MI->getOperand(2).getReg());
628    // FALL THROUGH.
629  case X86::VPERM2F128rm:
630  case X86::VPERM2I128rm:
631    // For instruction comments purpose, assume the 256-bit vector is v4i64.
632    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
633      DecodeVPERM2X128Mask(MVT::v4i64,
634                           MI->getOperand(MI->getNumOperands() - 1).getImm(),
635                           ShuffleMask);
636    Src1Name = getRegName(MI->getOperand(1).getReg());
637    DestName = getRegName(MI->getOperand(0).getReg());
638    break;
639
640  case X86::VPERMQYri:
641  case X86::VPERMPDYri:
642    Src1Name = getRegName(MI->getOperand(1).getReg());
643    // FALL THROUGH.
644  case X86::VPERMQYmi:
645  case X86::VPERMPDYmi:
646    if (MI->getOperand(MI->getNumOperands() - 1).isImm())
647      DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
648                      ShuffleMask);
649    DestName = getRegName(MI->getOperand(0).getReg());
650    break;
651
652  case X86::MOVSDrr:
653  case X86::VMOVSDrr:
654    Src2Name = getRegName(MI->getOperand(2).getReg());
655    Src1Name = getRegName(MI->getOperand(1).getReg());
656    // FALL THROUGH.
657  case X86::MOVSDrm:
658  case X86::VMOVSDrm:
659    DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
660    DestName = getRegName(MI->getOperand(0).getReg());
661    break;
662
663  case X86::MOVSSrr:
664  case X86::VMOVSSrr:
665    Src2Name = getRegName(MI->getOperand(2).getReg());
666    Src1Name = getRegName(MI->getOperand(1).getReg());
667    // FALL THROUGH.
668  case X86::MOVSSrm:
669  case X86::VMOVSSrm:
670    DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
671    DestName = getRegName(MI->getOperand(0).getReg());
672    break;
673
674  case X86::MOVPQI2QIrr:
675  case X86::MOVZPQILo2PQIrr:
676  case X86::VMOVPQI2QIrr:
677  case X86::VMOVZPQILo2PQIrr:
678  case X86::VMOVZPQILo2PQIZrr:
679    Src1Name = getRegName(MI->getOperand(1).getReg());
680  // FALL THROUGH.
681  case X86::MOVQI2PQIrm:
682  case X86::MOVZQI2PQIrm:
683  case X86::MOVZPQILo2PQIrm:
684  case X86::VMOVQI2PQIrm:
685  case X86::VMOVZQI2PQIrm:
686  case X86::VMOVZPQILo2PQIrm:
687  case X86::VMOVZPQILo2PQIZrm:
688    DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
689    DestName = getRegName(MI->getOperand(0).getReg());
690    break;
691
692  case X86::MOVDI2PDIrm:
693  case X86::VMOVDI2PDIrm:
694    DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
695    DestName = getRegName(MI->getOperand(0).getReg());
696    break;
697
698  case X86::EXTRQI:
699    if (MI->getOperand(2).isImm() &&
700        MI->getOperand(3).isImm())
701      DecodeEXTRQIMask(MI->getOperand(2).getImm(),
702                       MI->getOperand(3).getImm(),
703                       ShuffleMask);
704
705    DestName = getRegName(MI->getOperand(0).getReg());
706    Src1Name = getRegName(MI->getOperand(1).getReg());
707    break;
708
709  case X86::INSERTQI:
710    if (MI->getOperand(3).isImm() &&
711        MI->getOperand(4).isImm())
712      DecodeINSERTQIMask(MI->getOperand(3).getImm(),
713                         MI->getOperand(4).getImm(),
714                         ShuffleMask);
715
716    DestName = getRegName(MI->getOperand(0).getReg());
717    Src1Name = getRegName(MI->getOperand(1).getReg());
718    Src2Name = getRegName(MI->getOperand(2).getReg());
719    break;
720
721  case X86::PMOVZXBWrr:
722  case X86::PMOVZXBDrr:
723  case X86::PMOVZXBQrr:
724  case X86::PMOVZXWDrr:
725  case X86::PMOVZXWQrr:
726  case X86::PMOVZXDQrr:
727  case X86::VPMOVZXBWrr:
728  case X86::VPMOVZXBDrr:
729  case X86::VPMOVZXBQrr:
730  case X86::VPMOVZXWDrr:
731  case X86::VPMOVZXWQrr:
732  case X86::VPMOVZXDQrr:
733  case X86::VPMOVZXBWYrr:
734  case X86::VPMOVZXBDYrr:
735  case X86::VPMOVZXBQYrr:
736  case X86::VPMOVZXWDYrr:
737  case X86::VPMOVZXWQYrr:
738  case X86::VPMOVZXDQYrr:
739    Src1Name = getRegName(MI->getOperand(1).getReg());
740  // FALL THROUGH.
741  case X86::PMOVZXBWrm:
742  case X86::PMOVZXBDrm:
743  case X86::PMOVZXBQrm:
744  case X86::PMOVZXWDrm:
745  case X86::PMOVZXWQrm:
746  case X86::PMOVZXDQrm:
747  case X86::VPMOVZXBWrm:
748  case X86::VPMOVZXBDrm:
749  case X86::VPMOVZXBQrm:
750  case X86::VPMOVZXWDrm:
751  case X86::VPMOVZXWQrm:
752  case X86::VPMOVZXDQrm:
753  case X86::VPMOVZXBWYrm:
754  case X86::VPMOVZXBDYrm:
755  case X86::VPMOVZXBQYrm:
756  case X86::VPMOVZXWDYrm:
757  case X86::VPMOVZXWQYrm:
758  case X86::VPMOVZXDQYrm: {
759    MVT SrcVT, DstVT;
760    getZeroExtensionTypes(MI, SrcVT, DstVT);
761    DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask);
762    DestName = getRegName(MI->getOperand(0).getReg());
763  } break;
764  }
765
766  // The only comments we decode are shuffles, so give up if we were unable to
767  // decode a shuffle mask.
768  if (ShuffleMask.empty())
769    return false;
770
771  if (!DestName) DestName = Src1Name;
772  OS << (DestName ? DestName : "mem") << " = ";
773
774  // If the two sources are the same, canonicalize the input elements to be
775  // from the first src so that we get larger element spans.
776  if (Src1Name == Src2Name) {
777    for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
778      if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
779          ShuffleMask[i] >= (int)e)   // From second mask.
780        ShuffleMask[i] -= e;
781    }
782  }
783
784  // The shuffle mask specifies which elements of the src1/src2 fill in the
785  // destination, with a few sentinel values.  Loop through and print them
786  // out.
787  for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
788    if (i != 0)
789      OS << ',';
790    if (ShuffleMask[i] == SM_SentinelZero) {
791      OS << "zero";
792      continue;
793    }
794
795    // Otherwise, it must come from src1 or src2.  Print the span of elements
796    // that comes from this src.
797    bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
798    const char *SrcName = isSrc1 ? Src1Name : Src2Name;
799    OS << (SrcName ? SrcName : "mem") << '[';
800    bool IsFirst = true;
801    while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
802           (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
803      if (!IsFirst)
804        OS << ',';
805      else
806        IsFirst = false;
807      if (ShuffleMask[i] == SM_SentinelUndef)
808        OS << "u";
809      else
810        OS << ShuffleMask[i] % ShuffleMask.size();
811      ++i;
812    }
813    OS << ']';
814    --i; // For loop increments element #.
815  }
816  //MI->print(OS, 0);
817  OS << "\n";
818
819  // We successfully added a comment to this instruction.
820  return true;
821}
822