X86RegisterInfo.cpp revision 18bd7bb4d453e014c39729c4bf2b43f1846b8a9a 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the MRegisterInfo class.  This
11// file is responsible for the frame pointer elimination optimization on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86RegisterInfo.h"
17#include "X86InstrBuilder.h"
18#include "llvm/Constants.h"
19#include "llvm/Type.h"
20#include "llvm/CodeGen/ValueTypes.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/Target/TargetMachine.h"
25#include "llvm/Target/TargetFrameInfo.h"
26#include "Support/CommandLine.h"
27#include "Support/STLExtras.h"
28using namespace llvm;
29
30namespace {
31  cl::opt<bool>
32  NoFPElim("disable-fp-elim",
33	   cl::desc("Disable frame pointer elimination optimization"));
34  cl::opt<bool>
35  NoFusing("disable-spill-fusing",
36           cl::desc("Disable fusing of spill code into instructions"));
37  cl::opt<bool>
38  PrintFailedFusing("print-failed-fuse-candidates",
39                    cl::desc("Print instructions that the allocator wants to"
40                             " fuse, but the X86 backend currently can't"),
41                    cl::Hidden);
42}
43
44X86RegisterInfo::X86RegisterInfo()
45  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
46
47static unsigned getIdx(const TargetRegisterClass *RC) {
48  switch (RC->getSize()) {
49  default: assert(0 && "Invalid data size!");
50  case 1:  return 0;
51  case 2:  return 1;
52  case 4:  return 2;
53  case 10: return 3;
54  }
55}
56
57int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
58                                         MachineBasicBlock::iterator MI,
59                                         unsigned SrcReg, int FrameIdx,
60                                         const TargetRegisterClass *RC) const {
61  static const unsigned Opcode[] =
62    { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTPr80 };
63  MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
64				       FrameIdx).addReg(SrcReg);
65  MBB.insert(MI, I);
66  return 1;
67}
68
69int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
70                                          MachineBasicBlock::iterator MI,
71                                          unsigned DestReg, int FrameIdx,
72                                          const TargetRegisterClass *RC) const{
73  static const unsigned Opcode[] =
74    { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDr80 };
75  unsigned OC = Opcode[getIdx(RC)];
76  MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
77  return 1;
78}
79
80int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
81                                  MachineBasicBlock::iterator MI,
82                                  unsigned DestReg, unsigned SrcReg,
83                                  const TargetRegisterClass *RC) const {
84  static const unsigned Opcode[] =
85    { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
86  MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
87  return 1;
88}
89
90static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
91                                MachineInstr *MI) {
92  return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
93                 .addReg(MI->getOperand(1).getReg());
94}
95
96static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
97                                MachineInstr *MI) {
98  return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
99                 .addZImm(MI->getOperand(1).getImmedValue());
100}
101
102static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
103                                MachineInstr *MI) {
104  return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
105                           FrameIndex);
106}
107
108static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
109                                 MachineInstr *MI) {
110  return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
111                        FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
112}
113
114
115bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
116                                        unsigned i, int FrameIndex) const {
117  if (NoFusing) return false;
118
119  /// FIXME: This should obviously be autogenerated by tablegen when patterns
120  /// are available!
121  MachineBasicBlock& MBB = *MI->getParent();
122  MachineInstr* NI = 0;
123  if (i == 0) {
124    switch(MI->getOpcode()) {
125    case X86::MOVrr8:  NI = MakeMRInst(X86::MOVmr8 , FrameIndex, MI); break;
126    case X86::MOVrr16: NI = MakeMRInst(X86::MOVmr16, FrameIndex, MI); break;
127    case X86::MOVrr32: NI = MakeMRInst(X86::MOVmr32, FrameIndex, MI); break;
128    case X86::MOVri8:  NI = MakeMIInst(X86::MOVmi8 , FrameIndex, MI); break;
129    case X86::MOVri16: NI = MakeMIInst(X86::MOVmi16, FrameIndex, MI); break;
130    case X86::MOVri32: NI = MakeMIInst(X86::MOVmi32, FrameIndex, MI); break;
131    case X86::ADDrr8:  NI = MakeMRInst(X86::ADDmr8 , FrameIndex, MI); break;
132    case X86::ADDrr16: NI = MakeMRInst(X86::ADDmr16, FrameIndex, MI); break;
133    case X86::ADDrr32: NI = MakeMRInst(X86::ADDmr32, FrameIndex, MI); break;
134    case X86::ADCrr32: NI = MakeMRInst(X86::ADCmr32, FrameIndex, MI); break;
135    case X86::ADDri8:  NI = MakeMIInst(X86::ADDmi8 , FrameIndex, MI); break;
136    case X86::ADDri16: NI = MakeMIInst(X86::ADDmi16, FrameIndex, MI); break;
137    case X86::ADDri32: NI = MakeMIInst(X86::ADDmi32, FrameIndex, MI); break;
138    case X86::SUBrr8:  NI = MakeMRInst(X86::SUBmr8 , FrameIndex, MI); break;
139    case X86::SUBrr16: NI = MakeMRInst(X86::SUBmr16, FrameIndex, MI); break;
140    case X86::SUBrr32: NI = MakeMRInst(X86::SUBmr32, FrameIndex, MI); break;
141    case X86::SBBrr32: NI = MakeMRInst(X86::SBBmr32, FrameIndex, MI); break;
142    case X86::SUBri8:  NI = MakeMIInst(X86::SUBmi8 , FrameIndex, MI); break;
143    case X86::SUBri16: NI = MakeMIInst(X86::SUBmi16, FrameIndex, MI); break;
144    case X86::SUBri32: NI = MakeMIInst(X86::SUBmi32, FrameIndex, MI); break;
145    case X86::ANDrr8:  NI = MakeMRInst(X86::ANDmr8 , FrameIndex, MI); break;
146    case X86::ANDrr16: NI = MakeMRInst(X86::ANDmr16, FrameIndex, MI); break;
147    case X86::ANDrr32: NI = MakeMRInst(X86::ANDmr32, FrameIndex, MI); break;
148    case X86::ANDri8:  NI = MakeMIInst(X86::ANDmi8 , FrameIndex, MI); break;
149    case X86::ANDri16: NI = MakeMIInst(X86::ANDmi16, FrameIndex, MI); break;
150    case X86::ANDri32: NI = MakeMIInst(X86::ANDmi32, FrameIndex, MI); break;
151    default: break; // Cannot fold
152    }
153  } else if (i == 1) {
154    switch(MI->getOpcode()) {
155    case X86::MOVrr8:  NI = MakeRMInst(X86::MOVrm8 , FrameIndex, MI); break;
156    case X86::MOVrr16: NI = MakeRMInst(X86::MOVrm16, FrameIndex, MI); break;
157    case X86::MOVrr32: NI = MakeRMInst(X86::MOVrm32, FrameIndex, MI); break;
158    case X86::ADDrr8:  NI = MakeRMInst(X86::ADDrm8 , FrameIndex, MI); break;
159    case X86::ADDrr16: NI = MakeRMInst(X86::ADDrm16, FrameIndex, MI); break;
160    case X86::ADDrr32: NI = MakeRMInst(X86::ADDrm32, FrameIndex, MI); break;
161    case X86::ADCrr32: NI = MakeRMInst(X86::ADCrm32, FrameIndex, MI); break;
162    case X86::SUBrr8:  NI = MakeRMInst(X86::SUBrm8 , FrameIndex, MI); break;
163    case X86::SUBrr16: NI = MakeRMInst(X86::SUBrm16, FrameIndex, MI); break;
164    case X86::SUBrr32: NI = MakeRMInst(X86::SUBrm32, FrameIndex, MI); break;
165    case X86::SBBrr32: NI = MakeRMInst(X86::SBBrm32, FrameIndex, MI); break;
166    case X86::ANDrr8:  NI = MakeRMInst(X86::ANDrm8 , FrameIndex, MI); break;
167    case X86::ANDrr16: NI = MakeRMInst(X86::ANDrm16, FrameIndex, MI); break;
168    case X86::ANDrr32: NI = MakeRMInst(X86::ANDrm32, FrameIndex, MI); break;
169    case X86::IMULrr16:NI = MakeRMInst(X86::IMULrm16, FrameIndex, MI); break;
170    case X86::IMULrr32:NI = MakeRMInst(X86::IMULrm32, FrameIndex, MI); break;
171    case X86::IMULrri16: NI = MakeRMIInst(X86::IMULrmi16, FrameIndex, MI);break;
172    case X86::IMULrri32: NI = MakeRMIInst(X86::IMULrmi32, FrameIndex, MI);break;
173    default: break;
174    }
175  }
176  if (NI) {
177    MI = MBB.insert(MBB.erase(MI), NI);
178    return true;
179  } else {
180    if (PrintFailedFusing)
181      std::cerr << "We failed to fuse: " << *MI;
182    return false;
183  }
184}
185
186//===----------------------------------------------------------------------===//
187// Stack Frame Processing methods
188//===----------------------------------------------------------------------===//
189
190// hasFP - Return true if the specified function should have a dedicated frame
191// pointer register.  This is true if the function has variable sized allocas or
192// if frame pointer elimination is disabled.
193//
194static bool hasFP(MachineFunction &MF) {
195  return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
196}
197
198void X86RegisterInfo::
199eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
200                              MachineBasicBlock::iterator I) const {
201  if (hasFP(MF)) {
202    // If we have a frame pointer, turn the adjcallstackup instruction into a
203    // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
204    // <amt>'
205    MachineInstr *Old = I;
206    unsigned Amount = Old->getOperand(0).getImmedValue();
207    if (Amount != 0) {
208      // We need to keep the stack aligned properly.  To do this, we round the
209      // amount of space needed for the outgoing arguments up to the next
210      // alignment boundary.
211      unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
212      Amount = (Amount+Align-1)/Align*Align;
213
214      MachineInstr *New;
215      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
216	New=BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
217      } else {
218	assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
219	New=BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
220      }
221
222      // Replace the pseudo instruction with a new instruction...
223      MBB.insert(I, New);
224    }
225  }
226
227  MBB.erase(I);
228}
229
230void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
231                                         MachineBasicBlock::iterator II) const {
232  unsigned i = 0;
233  MachineInstr &MI = *II;
234  while (!MI.getOperand(i).isFrameIndex()) {
235    ++i;
236    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
237  }
238
239  int FrameIndex = MI.getOperand(i).getFrameIndex();
240
241  // This must be part of a four operand memory reference.  Replace the
242  // FrameIndex with base register with EBP.  Add add an offset to the offset.
243  MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
244
245  // Now add the frame object offset to the offset from EBP.
246  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
247               MI.getOperand(i+3).getImmedValue()+4;
248
249  if (!hasFP(MF))
250    Offset += MF.getFrameInfo()->getStackSize();
251  else
252    Offset += 4;  // Skip the saved EBP
253
254  MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
255}
256
257void
258X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
259  if (hasFP(MF)) {
260    // Create a frame entry for the EBP register that must be saved.
261    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
262    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
263           "Slot for EBP register must be last in order to be found!");
264  }
265}
266
267void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
268  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
269  MachineBasicBlock::iterator MBBI = MBB.begin();
270  MachineFrameInfo *MFI = MF.getFrameInfo();
271  MachineInstr *MI;
272
273  // Get the number of bytes to allocate from the FrameInfo
274  unsigned NumBytes = MFI->getStackSize();
275  if (hasFP(MF)) {
276    // Get the offset of the stack slot for the EBP register... which is
277    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
278    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
279
280    if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
281      MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
282      MBB.insert(MBBI, MI);
283    }
284
285    // Save EBP into the appropriate stack slot...
286    MI = addRegOffset(BuildMI(X86::MOVmr32, 5),    // mov [ESP-<offset>], EBP
287		      X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
288    MBB.insert(MBBI, MI);
289
290    // Update EBP with the new base value...
291    if (NumBytes == 4)    // mov EBP, ESP
292      MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
293    else                  // lea EBP, [ESP+StackSize]
294      MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP,NumBytes-4);
295
296    MBB.insert(MBBI, MI);
297
298  } else {
299    if (MFI->hasCalls()) {
300      // When we have no frame pointer, we reserve argument space for call sites
301      // in the function immediately on entry to the current function.  This
302      // eliminates the need for add/sub ESP brackets around call sites.
303      //
304      NumBytes += MFI->getMaxCallFrameSize();
305
306      // Round the size to a multiple of the alignment (don't forget the 4 byte
307      // offset though).
308      unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
309      NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
310    }
311
312    // Update frame info to pretend that this is part of the stack...
313    MFI->setStackSize(NumBytes);
314
315    if (NumBytes) {
316      // adjust stack pointer: ESP -= numbytes
317      MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
318      MBB.insert(MBBI, MI);
319    }
320  }
321}
322
323void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
324                                   MachineBasicBlock &MBB) const {
325  const MachineFrameInfo *MFI = MF.getFrameInfo();
326  MachineBasicBlock::iterator MBBI = prior(MBB.end());
327  MachineInstr *MI;
328  assert(MBBI->getOpcode() == X86::RET &&
329         "Can only insert epilog into returning blocks");
330
331  if (hasFP(MF)) {
332    // Get the offset of the stack slot for the EBP register... which is
333    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
334    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
335
336    // mov ESP, EBP
337    MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
338    MBB.insert(MBBI, MI);
339
340    // pop EBP
341    MI = BuildMI(X86::POPr32, 0, X86::EBP);
342    MBB.insert(MBBI, MI);
343  } else {
344    // Get the number of bytes allocated from the FrameInfo...
345    unsigned NumBytes = MFI->getStackSize();
346
347    if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
348      MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
349      MBB.insert(MBBI, MI);
350    }
351  }
352}
353
354#include "X86GenRegisterInfo.inc"
355
356const TargetRegisterClass*
357X86RegisterInfo::getRegClassForType(const Type* Ty) const {
358  switch (Ty->getPrimitiveID()) {
359  case Type::LongTyID:
360  case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
361  default:              assert(0 && "Invalid type to getClass!");
362  case Type::BoolTyID:
363  case Type::SByteTyID:
364  case Type::UByteTyID:   return &R8Instance;
365  case Type::ShortTyID:
366  case Type::UShortTyID:  return &R16Instance;
367  case Type::IntTyID:
368  case Type::UIntTyID:
369  case Type::PointerTyID: return &R32Instance;
370
371  case Type::FloatTyID:
372  case Type::DoubleTyID: return &RFPInstance;
373  }
374}
375