X86RegisterInfo.cpp revision 2a9d1ca9c244aeac98044a5fc9a081ff3df7b2ff 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86.h"
17#include "X86RegisterInfo.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Target/TargetFrameLowering.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/STLExtras.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/CommandLine.h"
42using namespace llvm;
43
44cl::opt<bool>
45ForceStackAlign("force-align-stack",
46                 cl::desc("Force align the stack to the minimum alignment"
47                           " needed for the function."),
48                 cl::init(false), cl::Hidden);
49
50X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51                                 const TargetInstrInfo &tii)
52  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
53                         X86::ADJCALLSTACKDOWN64 :
54                         X86::ADJCALLSTACKDOWN32,
55                       tm.getSubtarget<X86Subtarget>().is64Bit() ?
56                         X86::ADJCALLSTACKUP64 :
57                         X86::ADJCALLSTACKUP32),
58    TM(tm), TII(tii) {
59  // Cache some information.
60  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
61  Is64Bit = Subtarget->is64Bit();
62  IsWin64 = Subtarget->isTargetWin64();
63  StackAlign = TM.getFrameLowering()->getStackAlignment();
64
65  if (Is64Bit) {
66    SlotSize = 8;
67    StackPtr = X86::RSP;
68    FramePtr = X86::RBP;
69  } else {
70    SlotSize = 4;
71    StackPtr = X86::ESP;
72    FramePtr = X86::EBP;
73  }
74}
75
76static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
77  if (!Subtarget->is64Bit()) {
78    if (Subtarget->isTargetDarwin()) {
79      if (isEH)
80        return DWARFFlavour::X86_32_DarwinEH;
81      else
82        return DWARFFlavour::X86_32_Generic;
83    } else if (Subtarget->isTargetCygMing()) {
84      // Unsupported by now, just quick fallback
85      return DWARFFlavour::X86_32_Generic;
86    } else {
87      return DWARFFlavour::X86_32_Generic;
88    }
89  }
90  return DWARFFlavour::X86_64;
91}
92
93/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
94/// specific numbering, used in debug info and exception tables.
95int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
96  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
97  unsigned Flavour = getFlavour(Subtarget, isEH);
98
99  return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
100}
101
102/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
103int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
104  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
105  unsigned Flavour = getFlavour(Subtarget, isEH);
106
107  return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
108}
109
110int
111X86RegisterInfo::getSEHRegNum(unsigned i) const {
112  int reg = getX86RegNum(i);
113  switch (i) {
114  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
115  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
116  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
117  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
120  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
121  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
122  case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
123  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
124  case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
125  case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
126    reg += 8;
127  }
128  return reg;
129}
130
131/// getX86RegNum - This function maps LLVM register identifiers to their X86
132/// specific numbering, which is used in various places encoding instructions.
133unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
134  switch(RegNo) {
135  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
136  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
137  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
138  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
139  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
140    return N86::ESP;
141  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
142    return N86::EBP;
143  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
144    return N86::ESI;
145  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
146    return N86::EDI;
147
148  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
149    return N86::EAX;
150  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
151    return N86::ECX;
152  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
153    return N86::EDX;
154  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
155    return N86::EBX;
156  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
157    return N86::ESP;
158  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
159    return N86::EBP;
160  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
161    return N86::ESI;
162  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
163    return N86::EDI;
164
165  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
166  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
167    return RegNo-X86::ST0;
168
169  case X86::XMM0: case X86::XMM8:
170  case X86::YMM0: case X86::YMM8: case X86::MM0:
171    return 0;
172  case X86::XMM1: case X86::XMM9:
173  case X86::YMM1: case X86::YMM9: case X86::MM1:
174    return 1;
175  case X86::XMM2: case X86::XMM10:
176  case X86::YMM2: case X86::YMM10: case X86::MM2:
177    return 2;
178  case X86::XMM3: case X86::XMM11:
179  case X86::YMM3: case X86::YMM11: case X86::MM3:
180    return 3;
181  case X86::XMM4: case X86::XMM12:
182  case X86::YMM4: case X86::YMM12: case X86::MM4:
183    return 4;
184  case X86::XMM5: case X86::XMM13:
185  case X86::YMM5: case X86::YMM13: case X86::MM5:
186    return 5;
187  case X86::XMM6: case X86::XMM14:
188  case X86::YMM6: case X86::YMM14: case X86::MM6:
189    return 6;
190  case X86::XMM7: case X86::XMM15:
191  case X86::YMM7: case X86::YMM15: case X86::MM7:
192    return 7;
193
194  case X86::ES: return 0;
195  case X86::CS: return 1;
196  case X86::SS: return 2;
197  case X86::DS: return 3;
198  case X86::FS: return 4;
199  case X86::GS: return 5;
200
201  case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
202  case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
203  case X86::CR2: case X86::CR10: case X86::DR2: return 2;
204  case X86::CR3: case X86::CR11: case X86::DR3: return 3;
205  case X86::CR4: case X86::CR12: case X86::DR4: return 4;
206  case X86::CR5: case X86::CR13: case X86::DR5: return 5;
207  case X86::CR6: case X86::CR14: case X86::DR6: return 6;
208  case X86::CR7: case X86::CR15: case X86::DR7: return 7;
209
210  // Pseudo index registers are equivalent to a "none"
211  // scaled index (See Intel Manual 2A, table 2-3)
212  case X86::EIZ:
213  case X86::RIZ:
214    return 4;
215
216  default:
217    assert(isVirtualRegister(RegNo) && "Unknown physical register!");
218    llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
219    return 0;
220  }
221}
222
223const TargetRegisterClass *
224X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
225                                          const TargetRegisterClass *B,
226                                          unsigned SubIdx) const {
227  switch (SubIdx) {
228  default: return 0;
229  case X86::sub_8bit:
230    if (B == &X86::GR8RegClass) {
231      if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
232        return A;
233    } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
234      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
235          A == &X86::GR64_NOREXRegClass ||
236          A == &X86::GR64_NOSPRegClass ||
237          A == &X86::GR64_NOREX_NOSPRegClass)
238        return &X86::GR64_ABCDRegClass;
239      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
240               A == &X86::GR32_NOREXRegClass ||
241               A == &X86::GR32_NOSPRegClass)
242        return &X86::GR32_ABCDRegClass;
243      else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
244               A == &X86::GR16_NOREXRegClass)
245        return &X86::GR16_ABCDRegClass;
246    } else if (B == &X86::GR8_NOREXRegClass) {
247      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
248          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
249        return &X86::GR64_NOREXRegClass;
250      else if (A == &X86::GR64_ABCDRegClass)
251        return &X86::GR64_ABCDRegClass;
252      else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
253               A == &X86::GR32_NOSPRegClass)
254        return &X86::GR32_NOREXRegClass;
255      else if (A == &X86::GR32_ABCDRegClass)
256        return &X86::GR32_ABCDRegClass;
257      else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
258        return &X86::GR16_NOREXRegClass;
259      else if (A == &X86::GR16_ABCDRegClass)
260        return &X86::GR16_ABCDRegClass;
261    }
262    break;
263  case X86::sub_8bit_hi:
264    if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
265      switch (A->getSize()) {
266        case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
267        case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
268        case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
269        default: return 0;
270      }
271    break;
272  case X86::sub_16bit:
273    if (B == &X86::GR16RegClass) {
274      if (A->getSize() == 4 || A->getSize() == 8)
275        return A;
276    } else if (B == &X86::GR16_ABCDRegClass) {
277      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
278          A == &X86::GR64_NOREXRegClass ||
279          A == &X86::GR64_NOSPRegClass ||
280          A == &X86::GR64_NOREX_NOSPRegClass)
281        return &X86::GR64_ABCDRegClass;
282      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
283               A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
284        return &X86::GR32_ABCDRegClass;
285    } else if (B == &X86::GR16_NOREXRegClass) {
286      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
287          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
288        return &X86::GR64_NOREXRegClass;
289      else if (A == &X86::GR64_ABCDRegClass)
290        return &X86::GR64_ABCDRegClass;
291      else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
292               A == &X86::GR32_NOSPRegClass)
293        return &X86::GR32_NOREXRegClass;
294      else if (A == &X86::GR32_ABCDRegClass)
295        return &X86::GR64_ABCDRegClass;
296    }
297    break;
298  case X86::sub_32bit:
299    if (B == &X86::GR32RegClass) {
300      if (A->getSize() == 8)
301        return A;
302    } else if (B == &X86::GR32_NOSPRegClass) {
303      if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
304        return &X86::GR64_NOSPRegClass;
305      if (A->getSize() == 8)
306        return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
307    } else if (B == &X86::GR32_ABCDRegClass) {
308      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
309          A == &X86::GR64_NOREXRegClass ||
310          A == &X86::GR64_NOSPRegClass ||
311          A == &X86::GR64_NOREX_NOSPRegClass)
312        return &X86::GR64_ABCDRegClass;
313    } else if (B == &X86::GR32_NOREXRegClass) {
314      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
315        return &X86::GR64_NOREXRegClass;
316      else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
317        return &X86::GR64_NOREX_NOSPRegClass;
318      else if (A == &X86::GR64_ABCDRegClass)
319        return &X86::GR64_ABCDRegClass;
320    } else if (B == &X86::GR32_NOREX_NOSPRegClass) {
321      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
322          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
323        return &X86::GR64_NOREX_NOSPRegClass;
324      else if (A == &X86::GR64_ABCDRegClass)
325        return &X86::GR64_ABCDRegClass;
326    }
327    break;
328  case X86::sub_ss:
329    if (B == &X86::FR32RegClass)
330      return A;
331    break;
332  case X86::sub_sd:
333    if (B == &X86::FR64RegClass)
334      return A;
335    break;
336  case X86::sub_xmm:
337    if (B == &X86::VR128RegClass)
338      return A;
339    break;
340  }
341  return 0;
342}
343
344const TargetRegisterClass*
345X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
346  const TargetRegisterClass *Super = RC;
347  TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
348  do {
349    switch (Super->getID()) {
350    case X86::GR8RegClassID:
351    case X86::GR16RegClassID:
352    case X86::GR32RegClassID:
353    case X86::GR64RegClassID:
354    case X86::FR32RegClassID:
355    case X86::FR64RegClassID:
356    case X86::RFP32RegClassID:
357    case X86::RFP64RegClassID:
358    case X86::RFP80RegClassID:
359    case X86::VR128RegClassID:
360    case X86::VR256RegClassID:
361      // Don't return a super-class that would shrink the spill size.
362      // That can happen with the vector and float classes.
363      if (Super->getSize() == RC->getSize())
364        return Super;
365    }
366    Super = *I++;
367  } while (Super);
368  return RC;
369}
370
371const TargetRegisterClass *
372X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
373  switch (Kind) {
374  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
375  case 0: // Normal GPRs.
376    if (TM.getSubtarget<X86Subtarget>().is64Bit())
377      return &X86::GR64RegClass;
378    return &X86::GR32RegClass;
379  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
380    if (TM.getSubtarget<X86Subtarget>().is64Bit())
381      return &X86::GR64_NOSPRegClass;
382    return &X86::GR32_NOSPRegClass;
383  case 2: // Available for tailcall (not callee-saved GPRs).
384    if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
385      return &X86::GR64_TCW64RegClass;
386    if (TM.getSubtarget<X86Subtarget>().is64Bit())
387      return &X86::GR64_TCRegClass;
388    return &X86::GR32_TCRegClass;
389  }
390}
391
392const TargetRegisterClass *
393X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
394  if (RC == &X86::CCRRegClass) {
395    if (Is64Bit)
396      return &X86::GR64RegClass;
397    else
398      return &X86::GR32RegClass;
399  }
400  return RC;
401}
402
403unsigned
404X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
405                                     MachineFunction &MF) const {
406  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
407
408  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
409  switch (RC->getID()) {
410  default:
411    return 0;
412  case X86::GR32RegClassID:
413    return 4 - FPDiff;
414  case X86::GR64RegClassID:
415    return 12 - FPDiff;
416  case X86::VR128RegClassID:
417    return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
418  case X86::VR64RegClassID:
419    return 4;
420  }
421}
422
423const unsigned *
424X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
425  bool callsEHReturn = false;
426  bool ghcCall = false;
427
428  if (MF) {
429    callsEHReturn = MF->getMMI().callsEHReturn();
430    const Function *F = MF->getFunction();
431    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
432  }
433
434  static const unsigned GhcCalleeSavedRegs[] = {
435    0
436  };
437
438  static const unsigned CalleeSavedRegs32Bit[] = {
439    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
440  };
441
442  static const unsigned CalleeSavedRegs32EHRet[] = {
443    X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
444  };
445
446  static const unsigned CalleeSavedRegs64Bit[] = {
447    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
448  };
449
450  static const unsigned CalleeSavedRegs64EHRet[] = {
451    X86::RAX, X86::RDX, X86::RBX, X86::R12,
452    X86::R13, X86::R14, X86::R15, X86::RBP, 0
453  };
454
455  static const unsigned CalleeSavedRegsWin64[] = {
456    X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
457    X86::R12,   X86::R13,   X86::R14,   X86::R15,
458    X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
459    X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
460    X86::XMM14, X86::XMM15, 0
461  };
462
463  if (ghcCall) {
464    return GhcCalleeSavedRegs;
465  } else if (Is64Bit) {
466    if (IsWin64)
467      return CalleeSavedRegsWin64;
468    else
469      return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
470  } else {
471    return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
472  }
473}
474
475BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
476  BitVector Reserved(getNumRegs());
477  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
478
479  // Set the stack-pointer register and its aliases as reserved.
480  Reserved.set(X86::RSP);
481  Reserved.set(X86::ESP);
482  Reserved.set(X86::SP);
483  Reserved.set(X86::SPL);
484
485  // Set the instruction pointer register and its aliases as reserved.
486  Reserved.set(X86::RIP);
487  Reserved.set(X86::EIP);
488  Reserved.set(X86::IP);
489
490  // Set the frame-pointer register and its aliases as reserved if needed.
491  if (TFI->hasFP(MF)) {
492    Reserved.set(X86::RBP);
493    Reserved.set(X86::EBP);
494    Reserved.set(X86::BP);
495    Reserved.set(X86::BPL);
496  }
497
498  // Mark the x87 stack registers as reserved, since they don't behave normally
499  // with respect to liveness. We don't fully model the effects of x87 stack
500  // pushes and pops after stackification.
501  Reserved.set(X86::ST0);
502  Reserved.set(X86::ST1);
503  Reserved.set(X86::ST2);
504  Reserved.set(X86::ST3);
505  Reserved.set(X86::ST4);
506  Reserved.set(X86::ST5);
507  Reserved.set(X86::ST6);
508  Reserved.set(X86::ST7);
509
510  // Mark the segment registers as reserved.
511  Reserved.set(X86::CS);
512  Reserved.set(X86::SS);
513  Reserved.set(X86::DS);
514  Reserved.set(X86::ES);
515  Reserved.set(X86::FS);
516  Reserved.set(X86::GS);
517
518  // Reserve the registers that only exist in 64-bit mode.
519  if (!Is64Bit) {
520    for (unsigned n = 0; n != 8; ++n) {
521      const unsigned GPR64[] = {
522        X86::R8,  X86::R9,  X86::R10, X86::R11,
523        X86::R12, X86::R13, X86::R14, X86::R15
524      };
525      for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI;
526           ++AI)
527        Reserved.set(Reg);
528
529      // XMM8, XMM9, ...
530      assert(X86::XMM15 == X86::XMM8+7);
531      for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
532           ++AI)
533        Reserved.set(Reg);
534    }
535  }
536
537  return Reserved;
538}
539
540//===----------------------------------------------------------------------===//
541// Stack Frame Processing methods
542//===----------------------------------------------------------------------===//
543
544bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
545  const MachineFrameInfo *MFI = MF.getFrameInfo();
546  return (RealignStack &&
547          !MFI->hasVarSizedObjects());
548}
549
550bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
551  const MachineFrameInfo *MFI = MF.getFrameInfo();
552  const Function *F = MF.getFunction();
553  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
554                               F->hasFnAttr(Attribute::StackAlignment));
555
556  // FIXME: Currently we don't support stack realignment for functions with
557  //        variable-sized allocas.
558  // FIXME: It's more complicated than this...
559  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
560    report_fatal_error(
561      "Stack realignment in presence of dynamic allocas is not supported");
562
563  // If we've requested that we force align the stack do so now.
564  if (ForceStackAlign)
565    return canRealignStack(MF);
566
567  return requiresRealignment && canRealignStack(MF);
568}
569
570bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
571                                           unsigned Reg, int &FrameIdx) const {
572  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
573
574  if (Reg == FramePtr && TFI->hasFP(MF)) {
575    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
576    return true;
577  }
578  return false;
579}
580
581static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
582  if (is64Bit) {
583    if (isInt<8>(Imm))
584      return X86::SUB64ri8;
585    return X86::SUB64ri32;
586  } else {
587    if (isInt<8>(Imm))
588      return X86::SUB32ri8;
589    return X86::SUB32ri;
590  }
591}
592
593static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
594  if (is64Bit) {
595    if (isInt<8>(Imm))
596      return X86::ADD64ri8;
597    return X86::ADD64ri32;
598  } else {
599    if (isInt<8>(Imm))
600      return X86::ADD32ri8;
601    return X86::ADD32ri;
602  }
603}
604
605void X86RegisterInfo::
606eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
607                              MachineBasicBlock::iterator I) const {
608  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
609  bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
610  int Opcode = I->getOpcode();
611  bool isDestroy = Opcode == getCallFrameDestroyOpcode();
612  DebugLoc DL = I->getDebugLoc();
613  uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
614  uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
615  I = MBB.erase(I);
616
617  if (!reseveCallFrame) {
618    // If the stack pointer can be changed after prologue, turn the
619    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
620    // adjcallstackdown instruction into 'add ESP, <amt>'
621    // TODO: consider using push / pop instead of sub + store / add
622    if (Amount == 0)
623      return;
624
625    // We need to keep the stack aligned properly.  To do this, we round the
626    // amount of space needed for the outgoing arguments up to the next
627    // alignment boundary.
628    Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
629
630    MachineInstr *New = 0;
631    if (Opcode == getCallFrameSetupOpcode()) {
632      New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
633                    StackPtr)
634        .addReg(StackPtr)
635        .addImm(Amount);
636    } else {
637      assert(Opcode == getCallFrameDestroyOpcode());
638
639      // Factor out the amount the callee already popped.
640      Amount -= CalleeAmt;
641
642      if (Amount) {
643        unsigned Opc = getADDriOpcode(Is64Bit, Amount);
644        New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
645          .addReg(StackPtr).addImm(Amount);
646      }
647    }
648
649    if (New) {
650      // The EFLAGS implicit def is dead.
651      New->getOperand(3).setIsDead();
652
653      // Replace the pseudo instruction with a new instruction.
654      MBB.insert(I, New);
655    }
656
657    return;
658  }
659
660  if (Opcode == getCallFrameDestroyOpcode() && CalleeAmt) {
661    // If we are performing frame pointer elimination and if the callee pops
662    // something off the stack pointer, add it back.  We do this until we have
663    // more advanced stack pointer tracking ability.
664    unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
665    MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
666      .addReg(StackPtr).addImm(CalleeAmt);
667
668    // The EFLAGS implicit def is dead.
669    New->getOperand(3).setIsDead();
670    MBB.insert(I, New);
671  }
672}
673
674void
675X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
676                                     int SPAdj, RegScavenger *RS) const{
677  assert(SPAdj == 0 && "Unexpected");
678
679  unsigned i = 0;
680  MachineInstr &MI = *II;
681  MachineFunction &MF = *MI.getParent()->getParent();
682  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
683
684  while (!MI.getOperand(i).isFI()) {
685    ++i;
686    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
687  }
688
689  int FrameIndex = MI.getOperand(i).getIndex();
690  unsigned BasePtr;
691
692  unsigned Opc = MI.getOpcode();
693  bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
694  if (needsStackRealignment(MF))
695    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
696  else if (AfterFPPop)
697    BasePtr = StackPtr;
698  else
699    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
700
701  // This must be part of a four operand memory reference.  Replace the
702  // FrameIndex with base register with EBP.  Add an offset to the offset.
703  MI.getOperand(i).ChangeToRegister(BasePtr, false);
704
705  // Now add the frame object offset to the offset from EBP.
706  int FIOffset;
707  if (AfterFPPop) {
708    // Tail call jmp happens after FP is popped.
709    const MachineFrameInfo *MFI = MF.getFrameInfo();
710    FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
711  } else
712    FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
713
714  if (MI.getOperand(i+3).isImm()) {
715    // Offset is a 32-bit integer.
716    int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
717    MI.getOperand(i + 3).ChangeToImmediate(Offset);
718  } else {
719    // Offset is symbolic. This is extremely rare.
720    uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
721    MI.getOperand(i+3).setOffset(Offset);
722  }
723}
724
725unsigned X86RegisterInfo::getRARegister() const {
726  return Is64Bit ? X86::RIP     // Should have dwarf #16.
727                 : X86::EIP;    // Should have dwarf #8.
728}
729
730unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
731  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
732  return TFI->hasFP(MF) ? FramePtr : StackPtr;
733}
734
735unsigned X86RegisterInfo::getEHExceptionRegister() const {
736  llvm_unreachable("What is the exception register");
737  return 0;
738}
739
740unsigned X86RegisterInfo::getEHHandlerRegister() const {
741  llvm_unreachable("What is the exception handler register");
742  return 0;
743}
744
745namespace llvm {
746unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
747  switch (VT.getSimpleVT().SimpleTy) {
748  default: return Reg;
749  case MVT::i8:
750    if (High) {
751      switch (Reg) {
752      default: return 0;
753      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
754        return X86::AH;
755      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
756        return X86::DH;
757      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
758        return X86::CH;
759      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
760        return X86::BH;
761      }
762    } else {
763      switch (Reg) {
764      default: return 0;
765      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
766        return X86::AL;
767      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
768        return X86::DL;
769      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
770        return X86::CL;
771      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
772        return X86::BL;
773      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
774        return X86::SIL;
775      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
776        return X86::DIL;
777      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
778        return X86::BPL;
779      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
780        return X86::SPL;
781      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
782        return X86::R8B;
783      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
784        return X86::R9B;
785      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
786        return X86::R10B;
787      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
788        return X86::R11B;
789      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
790        return X86::R12B;
791      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
792        return X86::R13B;
793      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
794        return X86::R14B;
795      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
796        return X86::R15B;
797      }
798    }
799  case MVT::i16:
800    switch (Reg) {
801    default: return Reg;
802    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
803      return X86::AX;
804    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
805      return X86::DX;
806    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
807      return X86::CX;
808    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
809      return X86::BX;
810    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
811      return X86::SI;
812    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
813      return X86::DI;
814    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
815      return X86::BP;
816    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
817      return X86::SP;
818    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
819      return X86::R8W;
820    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
821      return X86::R9W;
822    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
823      return X86::R10W;
824    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
825      return X86::R11W;
826    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
827      return X86::R12W;
828    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
829      return X86::R13W;
830    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
831      return X86::R14W;
832    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
833      return X86::R15W;
834    }
835  case MVT::i32:
836    switch (Reg) {
837    default: return Reg;
838    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
839      return X86::EAX;
840    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
841      return X86::EDX;
842    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
843      return X86::ECX;
844    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
845      return X86::EBX;
846    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
847      return X86::ESI;
848    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
849      return X86::EDI;
850    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
851      return X86::EBP;
852    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
853      return X86::ESP;
854    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
855      return X86::R8D;
856    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
857      return X86::R9D;
858    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
859      return X86::R10D;
860    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
861      return X86::R11D;
862    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
863      return X86::R12D;
864    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
865      return X86::R13D;
866    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
867      return X86::R14D;
868    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
869      return X86::R15D;
870    }
871  case MVT::i64:
872    switch (Reg) {
873    default: return Reg;
874    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
875      return X86::RAX;
876    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
877      return X86::RDX;
878    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
879      return X86::RCX;
880    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
881      return X86::RBX;
882    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
883      return X86::RSI;
884    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
885      return X86::RDI;
886    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
887      return X86::RBP;
888    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
889      return X86::RSP;
890    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
891      return X86::R8;
892    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
893      return X86::R9;
894    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
895      return X86::R10;
896    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
897      return X86::R11;
898    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
899      return X86::R12;
900    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
901      return X86::R13;
902    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
903      return X86::R14;
904    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
905      return X86::R15;
906    }
907  }
908
909  return Reg;
910}
911}
912
913#include "X86GenRegisterInfo.inc"
914
915namespace {
916  struct MSAH : public MachineFunctionPass {
917    static char ID;
918    MSAH() : MachineFunctionPass(ID) {}
919
920    virtual bool runOnMachineFunction(MachineFunction &MF) {
921      const X86TargetMachine *TM =
922        static_cast<const X86TargetMachine *>(&MF.getTarget());
923      const X86RegisterInfo *X86RI = TM->getRegisterInfo();
924      MachineRegisterInfo &RI = MF.getRegInfo();
925      X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
926      unsigned StackAlignment = X86RI->getStackAlignment();
927
928      // Be over-conservative: scan over all vreg defs and find whether vector
929      // registers are used. If yes, there is a possibility that vector register
930      // will be spilled and thus require dynamic stack realignment.
931      for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
932        unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
933        if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
934          FuncInfo->setReserveFP(true);
935          return true;
936        }
937      }
938      // Nothing to do
939      return false;
940    }
941
942    virtual const char *getPassName() const {
943      return "X86 Maximal Stack Alignment Check";
944    }
945
946    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
947      AU.setPreservesCFG();
948      MachineFunctionPass::getAnalysisUsage(AU);
949    }
950  };
951
952  char MSAH::ID = 0;
953}
954
955FunctionPass*
956llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
957