X86RegisterInfo.cpp revision 2dad0250f683ac5b28a8984ce5be00d299f3c35e 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86.h"
17#include "X86RegisterInfo.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/Target/TargetAsmInfo.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/STLExtras.h"
40#include "llvm/Support/Compiler.h"
41using namespace llvm;
42
43X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44                                 const TargetInstrInfo &tii)
45  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
46    TM(tm), TII(tii) {
47  // Cache some information.
48  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
49  Is64Bit = Subtarget->is64Bit();
50  IsWin64 = Subtarget->isTargetWin64();
51  StackAlign = TM.getFrameInfo()->getStackAlignment();
52  if (Is64Bit) {
53    SlotSize = 8;
54    StackPtr = X86::RSP;
55    FramePtr = X86::RBP;
56  } else {
57    SlotSize = 4;
58    StackPtr = X86::ESP;
59    FramePtr = X86::EBP;
60  }
61}
62
63// getDwarfRegNum - This function maps LLVM register identifiers to the
64// Dwarf specific numbering, used in debug info and exception tables.
65
66int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
67  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68  unsigned Flavour = DWARFFlavour::X86_64;
69  if (!Subtarget->is64Bit()) {
70    if (Subtarget->isTargetDarwin()) {
71      if (isEH)
72        Flavour = DWARFFlavour::X86_32_DarwinEH;
73      else
74        Flavour = DWARFFlavour::X86_32_Generic;
75    } else if (Subtarget->isTargetCygMing()) {
76      // Unsupported by now, just quick fallback
77      Flavour = DWARFFlavour::X86_32_Generic;
78    } else {
79      Flavour = DWARFFlavour::X86_32_Generic;
80    }
81  }
82
83  return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84}
85
86// getX86RegNum - This function maps LLVM register identifiers to their X86
87// specific numbering, which is used in various places encoding instructions.
88//
89unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
90  switch(RegNo) {
91  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
92  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
93  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
94  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
95  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
96    return N86::ESP;
97  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
98    return N86::EBP;
99  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
100    return N86::ESI;
101  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102    return N86::EDI;
103
104  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
105    return N86::EAX;
106  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
107    return N86::ECX;
108  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
109    return N86::EDX;
110  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
111    return N86::EBX;
112  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
113    return N86::ESP;
114  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
115    return N86::EBP;
116  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
117    return N86::ESI;
118  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119    return N86::EDI;
120
121  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
122  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
123    return RegNo-X86::ST0;
124
125  case X86::XMM0: case X86::XMM8: case X86::MM0:
126    return 0;
127  case X86::XMM1: case X86::XMM9: case X86::MM1:
128    return 1;
129  case X86::XMM2: case X86::XMM10: case X86::MM2:
130    return 2;
131  case X86::XMM3: case X86::XMM11: case X86::MM3:
132    return 3;
133  case X86::XMM4: case X86::XMM12: case X86::MM4:
134    return 4;
135  case X86::XMM5: case X86::XMM13: case X86::MM5:
136    return 5;
137  case X86::XMM6: case X86::XMM14: case X86::MM6:
138    return 6;
139  case X86::XMM7: case X86::XMM15: case X86::MM7:
140    return 7;
141
142  default:
143    assert(isVirtualRegister(RegNo) && "Unknown physical register!");
144    assert(0 && "Register allocator hasn't allocated reg correctly yet!");
145    return 0;
146  }
147}
148
149const TargetRegisterClass *
150X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
151  if (RC == &X86::CCRRegClass) {
152    if (Is64Bit)
153      return &X86::GR64RegClass;
154    else
155      return &X86::GR32RegClass;
156  }
157  return NULL;
158}
159
160const unsigned *
161X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
162  static const unsigned CalleeSavedRegs32Bit[] = {
163    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
164  };
165
166  static const unsigned CalleeSavedRegs32EHRet[] = {
167    X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
168  };
169
170  static const unsigned CalleeSavedRegs64Bit[] = {
171    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
172  };
173
174  static const unsigned CalleeSavedRegsWin64[] = {
175    X86::RBX, X86::RBP, X86::RDI, X86::RSI,
176    X86::R12, X86::R13, X86::R14, X86::R15, 0
177  };
178
179  if (Is64Bit) {
180    if (IsWin64)
181      return CalleeSavedRegsWin64;
182    else
183      return CalleeSavedRegs64Bit;
184  } else {
185    if (MF) {
186        MachineFrameInfo *MFI = MF->getFrameInfo();
187        MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
188        if (MMI && MMI->callsEHReturn())
189          return CalleeSavedRegs32EHRet;
190    }
191    return CalleeSavedRegs32Bit;
192  }
193}
194
195const TargetRegisterClass* const*
196X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
197  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
198    &X86::GR32RegClass, &X86::GR32RegClass,
199    &X86::GR32RegClass, &X86::GR32RegClass,  0
200  };
201  static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
202    &X86::GR32RegClass, &X86::GR32RegClass,
203    &X86::GR32RegClass, &X86::GR32RegClass,
204    &X86::GR32RegClass, &X86::GR32RegClass,  0
205  };
206  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
207    &X86::GR64RegClass, &X86::GR64RegClass,
208    &X86::GR64RegClass, &X86::GR64RegClass,
209    &X86::GR64RegClass, &X86::GR64RegClass, 0
210  };
211  static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
212    &X86::GR64RegClass, &X86::GR64RegClass,
213    &X86::GR64RegClass, &X86::GR64RegClass,
214    &X86::GR64RegClass, &X86::GR64RegClass,
215    &X86::GR64RegClass, &X86::GR64RegClass, 0
216  };
217
218  if (Is64Bit) {
219    if (IsWin64)
220      return CalleeSavedRegClassesWin64;
221    else
222      return CalleeSavedRegClasses64Bit;
223  } else {
224    if (MF) {
225        MachineFrameInfo *MFI = MF->getFrameInfo();
226        MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
227        if (MMI && MMI->callsEHReturn())
228          return CalleeSavedRegClasses32EHRet;
229    }
230    return CalleeSavedRegClasses32Bit;
231  }
232
233}
234
235BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
236  BitVector Reserved(getNumRegs());
237  Reserved.set(X86::RSP);
238  Reserved.set(X86::ESP);
239  Reserved.set(X86::SP);
240  Reserved.set(X86::SPL);
241  if (hasFP(MF)) {
242    Reserved.set(X86::RBP);
243    Reserved.set(X86::EBP);
244    Reserved.set(X86::BP);
245    Reserved.set(X86::BPL);
246  }
247  return Reserved;
248}
249
250//===----------------------------------------------------------------------===//
251// Stack Frame Processing methods
252//===----------------------------------------------------------------------===//
253
254static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
255  unsigned MaxAlign = 0;
256  for (int i = FFI->getObjectIndexBegin(),
257         e = FFI->getObjectIndexEnd(); i != e; ++i) {
258    if (FFI->isDeadObjectIndex(i))
259      continue;
260    unsigned Align = FFI->getObjectAlignment(i);
261    MaxAlign = std::max(MaxAlign, Align);
262  }
263
264  return MaxAlign;
265}
266
267// hasFP - Return true if the specified function should have a dedicated frame
268// pointer register.  This is true if the function has variable sized allocas or
269// if frame pointer elimination is disabled.
270//
271bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
272  MachineFrameInfo *MFI = MF.getFrameInfo();
273  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
274
275  return (NoFramePointerElim ||
276          needsStackRealignment(MF) ||
277          MFI->hasVarSizedObjects() ||
278          MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
279          (MMI && MMI->callsUnwindInit()));
280}
281
282bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
283  MachineFrameInfo *MFI = MF.getFrameInfo();;
284
285  // FIXME: Currently we don't support stack realignment for functions with
286  // variable-sized allocas
287  return (RealignStack &&
288          (MFI->getMaxAlignment() > StackAlign &&
289           !MFI->hasVarSizedObjects()));
290}
291
292bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
293  return !MF.getFrameInfo()->hasVarSizedObjects();
294}
295
296int
297X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
298  int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
299  uint64_t StackSize = MF.getFrameInfo()->getStackSize();
300
301  if (needsStackRealignment(MF)) {
302    if (FI < 0)
303      // Skip the saved EBP
304      Offset += SlotSize;
305    else {
306      unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
307      assert( (-(Offset + StackSize)) % Align == 0);
308      return Offset + StackSize;
309    }
310
311    // FIXME: Support tail calls
312  } else {
313    if (!hasFP(MF))
314      return Offset + StackSize;
315
316    // Skip the saved EBP
317    Offset += SlotSize;
318
319    // Skip the RETADDR move area
320    X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
321    int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
322    if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
323  }
324
325  return Offset;
326}
327
328void X86RegisterInfo::
329eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
330                              MachineBasicBlock::iterator I) const {
331  if (!hasReservedCallFrame(MF)) {
332    // If the stack pointer can be changed after prologue, turn the
333    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
334    // adjcallstackdown instruction into 'add ESP, <amt>'
335    // TODO: consider using push / pop instead of sub + store / add
336    MachineInstr *Old = I;
337    uint64_t Amount = Old->getOperand(0).getImm();
338    if (Amount != 0) {
339      // We need to keep the stack aligned properly.  To do this, we round the
340      // amount of space needed for the outgoing arguments up to the next
341      // alignment boundary.
342      Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
343
344      MachineInstr *New = 0;
345      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
346        New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
347          .addReg(StackPtr).addImm(Amount);
348      } else {
349        assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
350        // factor out the amount the callee already popped.
351        uint64_t CalleeAmt = Old->getOperand(1).getImm();
352        Amount -= CalleeAmt;
353        if (Amount) {
354          unsigned Opc = (Amount < 128) ?
355            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
356            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
357          New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
358        }
359      }
360
361      // Replace the pseudo instruction with a new instruction...
362      if (New) MBB.insert(I, New);
363    }
364  } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
365    // If we are performing frame pointer elimination and if the callee pops
366    // something off the stack pointer, add it back.  We do this until we have
367    // more advanced stack pointer tracking ability.
368    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
369      unsigned Opc = (CalleeAmt < 128) ?
370        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
371        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
372      MachineInstr *New =
373        BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
374      MBB.insert(I, New);
375    }
376  }
377
378  MBB.erase(I);
379}
380
381void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
382                                          int SPAdj, RegScavenger *RS) const{
383  assert(SPAdj == 0 && "Unexpected");
384
385  unsigned i = 0;
386  MachineInstr &MI = *II;
387  MachineFunction &MF = *MI.getParent()->getParent();
388  while (!MI.getOperand(i).isFrameIndex()) {
389    ++i;
390    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
391  }
392
393  int FrameIndex = MI.getOperand(i).getIndex();
394
395  unsigned BasePtr;
396  if (needsStackRealignment(MF))
397    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
398  else
399    BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
400
401  // This must be part of a four operand memory reference.  Replace the
402  // FrameIndex with base register with EBP.  Add an offset to the offset.
403  MI.getOperand(i).ChangeToRegister(BasePtr, false);
404
405  // Now add the frame object offset to the offset from EBP.
406  int64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
407                   MI.getOperand(i+3).getImm();
408
409  MI.getOperand(i+3).ChangeToImmediate(Offset);
410}
411
412void
413X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
414                                                      RegScavenger *RS) const {
415  MachineFrameInfo *FFI = MF.getFrameInfo();
416
417  // Calculate and set max stack object alignment early, so we can decide
418  // whether we will need stack realignment (and thus FP).
419  unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
420                               calculateMaxStackAlignment(FFI));
421
422  FFI->setMaxAlignment(MaxAlign);
423}
424
425void
426X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
427  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
428  int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
429  if (TailCallReturnAddrDelta < 0) {
430    // create RETURNADDR area
431    //   arg
432    //   arg
433    //   RETADDR
434    //   { ...
435    //     RETADDR area
436    //     ...
437    //   }
438    //   [EBP]
439    MF.getFrameInfo()->
440      CreateFixedObject(-TailCallReturnAddrDelta,
441                        (-1*SlotSize)+TailCallReturnAddrDelta);
442  }
443  if (hasFP(MF)) {
444    assert((TailCallReturnAddrDelta <= 0) &&
445           "The Delta should always be zero or negative");
446    // Create a frame entry for the EBP register that must be saved.
447    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
448                                                        (int)SlotSize * -2+
449                                                       TailCallReturnAddrDelta);
450    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
451           "Slot for EBP register must be last in order to be found!");
452  }
453}
454
455/// emitSPUpdate - Emit a series of instructions to increment / decrement the
456/// stack pointer by a constant value.
457static
458void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
459                  unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
460                  const TargetInstrInfo &TII) {
461  bool isSub = NumBytes < 0;
462  uint64_t Offset = isSub ? -NumBytes : NumBytes;
463  unsigned Opc = isSub
464    ? ((Offset < 128) ?
465       (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
466       (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
467    : ((Offset < 128) ?
468       (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
469       (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
470  uint64_t Chunk = (1LL << 31) - 1;
471
472  while (Offset) {
473    uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
474    BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
475    Offset -= ThisVal;
476  }
477}
478
479// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
480static
481void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
482                      unsigned StackPtr, uint64_t *NumBytes = NULL) {
483  if (MBBI == MBB.begin()) return;
484
485  MachineBasicBlock::iterator PI = prior(MBBI);
486  unsigned Opc = PI->getOpcode();
487  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
488       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
489      PI->getOperand(0).getReg() == StackPtr) {
490    if (NumBytes)
491      *NumBytes += PI->getOperand(2).getImm();
492    MBB.erase(PI);
493  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
494              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
495             PI->getOperand(0).getReg() == StackPtr) {
496    if (NumBytes)
497      *NumBytes -= PI->getOperand(2).getImm();
498    MBB.erase(PI);
499  }
500}
501
502// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
503static
504void mergeSPUpdatesDown(MachineBasicBlock &MBB,
505                        MachineBasicBlock::iterator &MBBI,
506                        unsigned StackPtr, uint64_t *NumBytes = NULL) {
507  return;
508
509  if (MBBI == MBB.end()) return;
510
511  MachineBasicBlock::iterator NI = next(MBBI);
512  if (NI == MBB.end()) return;
513
514  unsigned Opc = NI->getOpcode();
515  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
516       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
517      NI->getOperand(0).getReg() == StackPtr) {
518    if (NumBytes)
519      *NumBytes -= NI->getOperand(2).getImm();
520    MBB.erase(NI);
521    MBBI = NI;
522  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
523              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
524             NI->getOperand(0).getReg() == StackPtr) {
525    if (NumBytes)
526      *NumBytes += NI->getOperand(2).getImm();
527    MBB.erase(NI);
528    MBBI = NI;
529  }
530}
531
532/// mergeSPUpdates - Checks the instruction before/after the passed
533/// instruction. If it is an ADD/SUB instruction it is deleted
534/// argument and the stack adjustment is returned as a positive value for ADD
535/// and a negative for SUB.
536static int mergeSPUpdates(MachineBasicBlock &MBB,
537                           MachineBasicBlock::iterator &MBBI,
538                           unsigned StackPtr,
539                           bool doMergeWithPrevious) {
540
541  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
542      (!doMergeWithPrevious && MBBI == MBB.end()))
543    return 0;
544
545  int Offset = 0;
546
547  MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
548  MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
549  unsigned Opc = PI->getOpcode();
550  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
551       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
552      PI->getOperand(0).getReg() == StackPtr){
553    Offset += PI->getOperand(2).getImm();
554    MBB.erase(PI);
555    if (!doMergeWithPrevious) MBBI = NI;
556  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
557              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
558             PI->getOperand(0).getReg() == StackPtr) {
559    Offset -= PI->getOperand(2).getImm();
560    MBB.erase(PI);
561    if (!doMergeWithPrevious) MBBI = NI;
562  }
563
564  return Offset;
565}
566
567void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
568                                     unsigned FrameLabelId,
569                                     unsigned ReadyLabelId) const {
570  MachineFrameInfo *MFI = MF.getFrameInfo();
571  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
572  if (!MMI)
573    return;
574
575  uint64_t StackSize = MFI->getStackSize();
576  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
577  const TargetData *TD = MF.getTarget().getTargetData();
578
579  // Calculate amount of bytes used for return address storing
580  int stackGrowth =
581    (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
582     TargetFrameInfo::StackGrowsUp ?
583     TD->getPointerSize() : -TD->getPointerSize());
584
585  if (StackSize) {
586    // Show update of SP.
587    if (hasFP(MF)) {
588      // Adjust SP
589      MachineLocation SPDst(MachineLocation::VirtualFP);
590      MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
591      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
592    } else {
593      MachineLocation SPDst(MachineLocation::VirtualFP);
594      MachineLocation SPSrc(MachineLocation::VirtualFP,
595                            -StackSize+stackGrowth);
596      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
597    }
598  } else {
599    //FIXME: Verify & implement for FP
600    MachineLocation SPDst(StackPtr);
601    MachineLocation SPSrc(StackPtr, stackGrowth);
602    Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
603  }
604
605  // Add callee saved registers to move list.
606  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
607
608  // FIXME: This is dirty hack. The code itself is pretty mess right now.
609  // It should be rewritten from scratch and generalized sometimes.
610
611  // Determine maximum offset (minumum due to stack growth)
612  int64_t MaxOffset = 0;
613  for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
614    MaxOffset = std::min(MaxOffset,
615                         MFI->getObjectOffset(CSI[I].getFrameIdx()));
616
617  // Calculate offsets
618  int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
619  for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
620    int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
621    unsigned Reg = CSI[I].getReg();
622    Offset = (MaxOffset-Offset+saveAreaOffset);
623    MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
624    MachineLocation CSSrc(Reg);
625    Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
626  }
627
628  if (hasFP(MF)) {
629    // Save FP
630    MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
631    MachineLocation FPSrc(FramePtr);
632    Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
633  }
634
635  MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
636  MachineLocation FPSrc(MachineLocation::VirtualFP);
637  Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
638}
639
640
641void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
642  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
643  MachineFrameInfo *MFI = MF.getFrameInfo();
644  const Function* Fn = MF.getFunction();
645  const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
646  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
647  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
648  MachineBasicBlock::iterator MBBI = MBB.begin();
649  bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
650                          !Fn->doesNotThrow() ||
651                          UnwindTablesMandatory;
652  // Prepare for frame info.
653  unsigned FrameLabelId = 0;
654
655  // Get the number of bytes to allocate from the FrameInfo.
656  uint64_t StackSize = MFI->getStackSize();
657  // Get desired stack alignment
658  uint64_t MaxAlign  = MFI->getMaxAlignment();
659
660  // Add RETADDR move area to callee saved frame size.
661  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
662  if (TailCallReturnAddrDelta < 0)
663    X86FI->setCalleeSavedFrameSize(
664          X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
665
666  // Insert stack pointer adjustment for later moving of return addr.  Only
667  // applies to tail call optimized functions where the callee argument stack
668  // size is bigger than the callers.
669  if (TailCallReturnAddrDelta < 0) {
670    BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
671            StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
672  }
673
674  uint64_t NumBytes = 0;
675  if (hasFP(MF)) {
676    // Calculate required stack adjustment
677    uint64_t FrameSize = StackSize - SlotSize;
678    if (needsStackRealignment(MF))
679      FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
680
681    NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
682
683    // Get the offset of the stack slot for the EBP register... which is
684    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
685    // Update the frame offset adjustment.
686    MFI->setOffsetAdjustment(-NumBytes);
687
688    // Save EBP into the appropriate stack slot...
689    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
690      .addReg(FramePtr);
691
692    if (needsFrameMoves) {
693      // Mark effective beginning of when frame pointer becomes valid.
694      FrameLabelId = MMI->NextLabelID();
695      BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
696    }
697
698    // Update EBP with the new base value...
699    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
700      .addReg(StackPtr);
701
702    // Realign stack
703    if (needsStackRealignment(MF))
704      BuildMI(MBB, MBBI,
705              TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
706              StackPtr).addReg(StackPtr).addImm(-MaxAlign);
707  } else
708    NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
709
710  unsigned ReadyLabelId = 0;
711  if (needsFrameMoves) {
712    // Mark effective beginning of when frame pointer is ready.
713    ReadyLabelId = MMI->NextLabelID();
714    BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
715  }
716
717  // Skip the callee-saved push instructions.
718  while (MBBI != MBB.end() &&
719         (MBBI->getOpcode() == X86::PUSH32r ||
720          MBBI->getOpcode() == X86::PUSH64r))
721    ++MBBI;
722
723  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
724    if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
725      // Check, whether EAX is livein for this function
726      bool isEAXAlive = false;
727      for (MachineRegisterInfo::livein_iterator
728           II = MF.getRegInfo().livein_begin(),
729           EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
730        unsigned Reg = II->first;
731        isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
732                      Reg == X86::AH || Reg == X86::AL);
733      }
734
735      // Function prologue calls _alloca to probe the stack when allocating
736      // more than 4k bytes in one go. Touching the stack at 4K increments is
737      // necessary to ensure that the guard pages used by the OS virtual memory
738      // manager are allocated in correct sequence.
739      if (!isEAXAlive) {
740        BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
741        BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
742          .addExternalSymbol("_alloca");
743      } else {
744        // Save EAX
745        BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
746        // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
747        // allocated bytes for EAX.
748        BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
749        BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
750          .addExternalSymbol("_alloca");
751        // Restore EAX
752        MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
753                                        StackPtr, NumBytes-4);
754        MBB.insert(MBBI, MI);
755      }
756    } else {
757      // If there is an SUB32ri of ESP immediately before this instruction,
758      // merge the two. This can be the case when tail call elimination is
759      // enabled and the callee has more arguments then the caller.
760      NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
761      // If there is an ADD32ri or SUB32ri of ESP immediately after this
762      // instruction, merge the two instructions.
763      mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
764
765      if (NumBytes)
766        emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
767    }
768  }
769
770  if (needsFrameMoves)
771    emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
772}
773
774void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
775                                   MachineBasicBlock &MBB) const {
776  const MachineFrameInfo *MFI = MF.getFrameInfo();
777  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
778  MachineBasicBlock::iterator MBBI = prior(MBB.end());
779  unsigned RetOpcode = MBBI->getOpcode();
780
781  switch (RetOpcode) {
782  case X86::RET:
783  case X86::RETI:
784  case X86::TCRETURNdi:
785  case X86::TCRETURNri:
786  case X86::TCRETURNri64:
787  case X86::TCRETURNdi64:
788  case X86::EH_RETURN:
789  case X86::TAILJMPd:
790  case X86::TAILJMPr:
791  case X86::TAILJMPm: break;  // These are ok
792  default:
793    assert(0 && "Can only insert epilog into returning blocks");
794  }
795
796  // Get the number of bytes to allocate from the FrameInfo
797  uint64_t StackSize = MFI->getStackSize();
798  uint64_t MaxAlign  = MFI->getMaxAlignment();
799  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
800  uint64_t NumBytes = 0;
801
802  if (hasFP(MF)) {
803    // Calculate required stack adjustment
804    uint64_t FrameSize = StackSize - SlotSize;
805    if (needsStackRealignment(MF))
806      FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
807
808    NumBytes = FrameSize - CSSize;
809
810    // pop EBP.
811    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
812  } else
813    NumBytes = StackSize - CSSize;
814
815  // Skip the callee-saved pop instructions.
816  MachineBasicBlock::iterator LastCSPop = MBBI;
817  while (MBBI != MBB.begin()) {
818    MachineBasicBlock::iterator PI = prior(MBBI);
819    unsigned Opc = PI->getOpcode();
820    if (Opc != X86::POP32r && Opc != X86::POP64r &&
821        !PI->getDesc().isTerminator())
822      break;
823    --MBBI;
824  }
825
826  // If there is an ADD32ri or SUB32ri of ESP immediately before this
827  // instruction, merge the two instructions.
828  if (NumBytes || MFI->hasVarSizedObjects())
829    mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
830
831  // If dynamic alloca is used, then reset esp to point to the last callee-saved
832  // slot before popping them off! Same applies for the case, when stack was
833  // realigned
834  if (needsStackRealignment(MF)) {
835    // We cannot use LEA here, because stack pointer was realigned. We need to
836    // deallocate local frame back
837    if (CSSize) {
838      emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
839      MBBI = prior(LastCSPop);
840    }
841
842    BuildMI(MBB, MBBI,
843            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
844            StackPtr).addReg(FramePtr);
845  } else if (MFI->hasVarSizedObjects()) {
846    if (CSSize) {
847      unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
848      MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
849                                      FramePtr, -CSSize);
850      MBB.insert(MBBI, MI);
851    } else
852      BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
853        addReg(FramePtr);
854
855  } else {
856    // adjust stack pointer back: ESP += numbytes
857    if (NumBytes)
858      emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
859  }
860
861  // We're returning from function via eh_return.
862  if (RetOpcode == X86::EH_RETURN) {
863    MBBI = prior(MBB.end());
864    MachineOperand &DestAddr  = MBBI->getOperand(0);
865    assert(DestAddr.isRegister() && "Offset should be in register!");
866    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
867      addReg(DestAddr.getReg());
868  // Tail call return: adjust the stack pointer and jump to callee
869  } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
870             RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
871    MBBI = prior(MBB.end());
872    MachineOperand &JumpTarget = MBBI->getOperand(0);
873    MachineOperand &StackAdjust = MBBI->getOperand(1);
874    assert( StackAdjust.isImmediate() && "Expecting immediate value.");
875
876    // Adjust stack pointer.
877    int StackAdj = StackAdjust.getImm();
878    int MaxTCDelta = X86FI->getTCReturnAddrDelta();
879    int Offset = 0;
880    assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
881    // Incoporate the retaddr area.
882    Offset = StackAdj-MaxTCDelta;
883    assert(Offset >= 0 && "Offset should never be negative");
884    if (Offset) {
885      // Check for possible merge with preceeding ADD instruction.
886      Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
887      emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
888    }
889    // Jump to label or value in register.
890    if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
891      BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
892        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
893    else if (RetOpcode== X86::TCRETURNri64) {
894      BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
895    } else
896       BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
897    // Delete the pseudo instruction TCRETURN.
898    MBB.erase(MBBI);
899  } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
900             (X86FI->getTCReturnAddrDelta() < 0)) {
901    // Add the return addr area delta back since we are not tail calling.
902    int delta = -1*X86FI->getTCReturnAddrDelta();
903    MBBI = prior(MBB.end());
904    // Check for possible merge with preceeding ADD instruction.
905    delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
906    emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
907  }
908}
909
910unsigned X86RegisterInfo::getRARegister() const {
911  if (Is64Bit)
912    return X86::RIP;  // Should have dwarf #16
913  else
914    return X86::EIP;  // Should have dwarf #8
915}
916
917unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
918  return hasFP(MF) ? FramePtr : StackPtr;
919}
920
921void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
922                                                                         const {
923  // Calculate amount of bytes used for return address storing
924  int stackGrowth = (Is64Bit ? -8 : -4);
925
926  // Initial state of the frame pointer is esp+4.
927  MachineLocation Dst(MachineLocation::VirtualFP);
928  MachineLocation Src(StackPtr, stackGrowth);
929  Moves.push_back(MachineMove(0, Dst, Src));
930
931  // Add return address to move list
932  MachineLocation CSDst(StackPtr, stackGrowth);
933  MachineLocation CSSrc(getRARegister());
934  Moves.push_back(MachineMove(0, CSDst, CSSrc));
935}
936
937unsigned X86RegisterInfo::getEHExceptionRegister() const {
938  assert(0 && "What is the exception register");
939  return 0;
940}
941
942unsigned X86RegisterInfo::getEHHandlerRegister() const {
943  assert(0 && "What is the exception handler register");
944  return 0;
945}
946
947namespace llvm {
948unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
949  switch (VT.getSimpleVT()) {
950  default: return Reg;
951  case MVT::i8:
952    if (High) {
953      switch (Reg) {
954      default: return 0;
955      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
956        return X86::AH;
957      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
958        return X86::DH;
959      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
960        return X86::CH;
961      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
962        return X86::BH;
963      }
964    } else {
965      switch (Reg) {
966      default: return 0;
967      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
968        return X86::AL;
969      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
970        return X86::DL;
971      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
972        return X86::CL;
973      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
974        return X86::BL;
975      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
976        return X86::SIL;
977      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
978        return X86::DIL;
979      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
980        return X86::BPL;
981      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
982        return X86::SPL;
983      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
984        return X86::R8B;
985      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
986        return X86::R9B;
987      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
988        return X86::R10B;
989      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
990        return X86::R11B;
991      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
992        return X86::R12B;
993      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
994        return X86::R13B;
995      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
996        return X86::R14B;
997      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
998        return X86::R15B;
999      }
1000    }
1001  case MVT::i16:
1002    switch (Reg) {
1003    default: return Reg;
1004    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1005      return X86::AX;
1006    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1007      return X86::DX;
1008    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1009      return X86::CX;
1010    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1011      return X86::BX;
1012    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1013      return X86::SI;
1014    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1015      return X86::DI;
1016    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1017      return X86::BP;
1018    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1019      return X86::SP;
1020    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1021      return X86::R8W;
1022    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1023      return X86::R9W;
1024    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1025      return X86::R10W;
1026    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1027      return X86::R11W;
1028    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1029      return X86::R12W;
1030    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1031      return X86::R13W;
1032    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1033      return X86::R14W;
1034    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1035      return X86::R15W;
1036    }
1037  case MVT::i32:
1038    switch (Reg) {
1039    default: return Reg;
1040    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1041      return X86::EAX;
1042    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1043      return X86::EDX;
1044    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1045      return X86::ECX;
1046    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1047      return X86::EBX;
1048    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1049      return X86::ESI;
1050    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1051      return X86::EDI;
1052    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1053      return X86::EBP;
1054    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1055      return X86::ESP;
1056    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1057      return X86::R8D;
1058    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1059      return X86::R9D;
1060    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1061      return X86::R10D;
1062    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1063      return X86::R11D;
1064    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1065      return X86::R12D;
1066    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1067      return X86::R13D;
1068    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1069      return X86::R14D;
1070    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1071      return X86::R15D;
1072    }
1073  case MVT::i64:
1074    switch (Reg) {
1075    default: return Reg;
1076    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1077      return X86::RAX;
1078    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1079      return X86::RDX;
1080    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1081      return X86::RCX;
1082    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1083      return X86::RBX;
1084    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1085      return X86::RSI;
1086    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1087      return X86::RDI;
1088    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1089      return X86::RBP;
1090    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1091      return X86::RSP;
1092    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1093      return X86::R8;
1094    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1095      return X86::R9;
1096    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1097      return X86::R10;
1098    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1099      return X86::R11;
1100    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1101      return X86::R12;
1102    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1103      return X86::R13;
1104    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1105      return X86::R14;
1106    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1107      return X86::R15;
1108    }
1109  }
1110
1111  return Reg;
1112}
1113}
1114
1115#include "X86GenRegisterInfo.inc"
1116
1117namespace {
1118  struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1119    static char ID;
1120    MSAC() : MachineFunctionPass((intptr_t)&ID) {}
1121
1122    virtual bool runOnMachineFunction(MachineFunction &MF) {
1123      MachineFrameInfo *FFI = MF.getFrameInfo();
1124      MachineRegisterInfo &RI = MF.getRegInfo();
1125
1126      // Calculate max stack alignment of all already allocated stack objects.
1127      unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1128
1129      // Be over-conservative: scan over all vreg defs and find, whether vector
1130      // registers are used. If yes - there is probability, that vector register
1131      // will be spilled and thus stack needs to be aligned properly.
1132      for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1133           RegNum < RI.getLastVirtReg(); ++RegNum)
1134        MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1135
1136      FFI->setMaxAlignment(MaxAlign);
1137
1138      return false;
1139    }
1140
1141    virtual const char *getPassName() const {
1142      return "X86 Maximal Stack Alignment Calculator";
1143    }
1144  };
1145
1146  char MSAC::ID = 0;
1147}
1148
1149FunctionPass*
1150llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }
1151