X86RegisterInfo.cpp revision 396618b43a85e12d290a90b181c6af5d7c0c5f11 
1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86RegisterInfo.h"
17#include "X86.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineModuleInfo.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/MC/MCAsmInfo.h"
33#include "llvm/Target/TargetFrameLowering.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/STLExtras.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/CommandLine.h"
41
42#define GET_REGINFO_TARGET_DESC
43#include "X86GenRegisterInfo.inc"
44
45using namespace llvm;
46
47cl::opt<bool>
48ForceStackAlign("force-align-stack",
49                 cl::desc("Force align the stack to the minimum alignment"
50                           " needed for the function."),
51                 cl::init(false), cl::Hidden);
52
53X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
54                                 const TargetInstrInfo &tii)
55  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
56                         ? X86::RIP : X86::EIP,
57                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
58                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
59                       TM(tm), TII(tii) {
60  X86_MC::InitLLVM2SEHRegisterMapping(this);
61
62  // Cache some information.
63  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64  Is64Bit = Subtarget->is64Bit();
65  IsWin64 = Subtarget->isTargetWin64();
66
67  if (Is64Bit) {
68    SlotSize = 8;
69    StackPtr = X86::RSP;
70    FramePtr = X86::RBP;
71  } else {
72    SlotSize = 4;
73    StackPtr = X86::ESP;
74    FramePtr = X86::EBP;
75  }
76}
77
78/// getCompactUnwindRegNum - This function maps the register to the number for
79/// compact unwind encoding. Return -1 if the register isn't valid.
80int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
81  switch (getLLVMRegNum(RegNum, isEH)) {
82  case X86::EBX: case X86::RBX: return 1;
83  case X86::ECX: case X86::R12: return 2;
84  case X86::EDX: case X86::R13: return 3;
85  case X86::EDI: case X86::R14: return 4;
86  case X86::ESI: case X86::R15: return 5;
87  case X86::EBP: case X86::RBP: return 6;
88  }
89
90  return -1;
91}
92
93bool
94X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
95  // Only enable when post-RA scheduling is enabled and this is needed.
96  return TM.getSubtargetImpl()->postRAScheduler();
97}
98
99int
100X86RegisterInfo::getSEHRegNum(unsigned i) const {
101  int reg = X86_MC::getX86RegNum(i);
102  switch (i) {
103  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
104  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
105  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
106  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
107  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
108  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
109  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
110  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
111  case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
112  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
113  case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
114  case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
115    reg += 8;
116  }
117  return reg;
118}
119
120const TargetRegisterClass *
121X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
122                                       unsigned Idx) const {
123  // The sub_8bit sub-register index is more constrained in 32-bit mode.
124  // It behaves just like the sub_8bit_hi index.
125  if (!Is64Bit && Idx == X86::sub_8bit)
126    Idx = X86::sub_8bit_hi;
127
128  // Forward to TableGen's default version.
129  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
130}
131
132const TargetRegisterClass *
133X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
134                                          const TargetRegisterClass *B,
135                                          unsigned SubIdx) const {
136  // The sub_8bit sub-register index is more constrained in 32-bit mode.
137  if (!Is64Bit && SubIdx == X86::sub_8bit) {
138    A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
139    if (!A)
140      return 0;
141  }
142  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
143}
144
145const TargetRegisterClass*
146X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
147  // Don't allow super-classes of GR8_NOREX.  This class is only used after
148  // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
149  // to the full GR8 register class in 64-bit mode, so we cannot allow the
150  // reigster class inflation.
151  //
152  // The GR8_NOREX class is always used in a way that won't be constrained to a
153  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
154  // full GR8 class.
155  if (RC == &X86::GR8_NOREXRegClass)
156    return RC;
157
158  const TargetRegisterClass *Super = RC;
159  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
160  do {
161    switch (Super->getID()) {
162    case X86::GR8RegClassID:
163    case X86::GR16RegClassID:
164    case X86::GR32RegClassID:
165    case X86::GR64RegClassID:
166    case X86::FR32RegClassID:
167    case X86::FR64RegClassID:
168    case X86::RFP32RegClassID:
169    case X86::RFP64RegClassID:
170    case X86::RFP80RegClassID:
171    case X86::VR128RegClassID:
172    case X86::VR256RegClassID:
173      // Don't return a super-class that would shrink the spill size.
174      // That can happen with the vector and float classes.
175      if (Super->getSize() == RC->getSize())
176        return Super;
177    }
178    Super = *I++;
179  } while (Super);
180  return RC;
181}
182
183const TargetRegisterClass *
184X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
185                                                                         const {
186  switch (Kind) {
187  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
188  case 0: // Normal GPRs.
189    if (TM.getSubtarget<X86Subtarget>().is64Bit())
190      return &X86::GR64RegClass;
191    return &X86::GR32RegClass;
192  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
193    if (TM.getSubtarget<X86Subtarget>().is64Bit())
194      return &X86::GR64_NOSPRegClass;
195    return &X86::GR32_NOSPRegClass;
196  case 2: // Available for tailcall (not callee-saved GPRs).
197    if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
198      return &X86::GR64_TCW64RegClass;
199    if (TM.getSubtarget<X86Subtarget>().is64Bit())
200      return &X86::GR64_TCRegClass;
201    return &X86::GR32_TCRegClass;
202  }
203}
204
205const TargetRegisterClass *
206X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
207  if (RC == &X86::CCRRegClass) {
208    if (Is64Bit)
209      return &X86::GR64RegClass;
210    else
211      return &X86::GR32RegClass;
212  }
213  return RC;
214}
215
216unsigned
217X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
218                                     MachineFunction &MF) const {
219  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
220
221  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
222  switch (RC->getID()) {
223  default:
224    return 0;
225  case X86::GR32RegClassID:
226    return 4 - FPDiff;
227  case X86::GR64RegClassID:
228    return 12 - FPDiff;
229  case X86::VR128RegClassID:
230    return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
231  case X86::VR64RegClassID:
232    return 4;
233  }
234}
235
236const uint16_t *
237X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
238  bool callsEHReturn = false;
239  bool ghcCall = false;
240
241  if (MF) {
242    callsEHReturn = MF->getMMI().callsEHReturn();
243    const Function *F = MF->getFunction();
244    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
245  }
246
247  if (ghcCall)
248    return CSR_NoRegs_SaveList;
249  if (Is64Bit) {
250    if (IsWin64)
251      return CSR_Win64_SaveList;
252    if (callsEHReturn)
253      return CSR_64EHRet_SaveList;
254    return CSR_64_SaveList;
255  }
256  if (callsEHReturn)
257    return CSR_32EHRet_SaveList;
258  return CSR_32_SaveList;
259}
260
261const uint32_t*
262X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
263  if (CC == CallingConv::GHC)
264    return CSR_NoRegs_RegMask;
265  if (!Is64Bit)
266    return CSR_32_RegMask;
267  if (IsWin64)
268    return CSR_Win64_RegMask;
269  return CSR_64_RegMask;
270}
271
272BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
273  BitVector Reserved(getNumRegs());
274  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
275
276  // Set the stack-pointer register and its aliases as reserved.
277  Reserved.set(X86::RSP);
278  for (MCSubRegIterator I(X86::RSP, this); I.isValid(); ++I)
279    Reserved.set(*I);
280
281  // Set the instruction pointer register and its aliases as reserved.
282  Reserved.set(X86::RIP);
283  for (MCSubRegIterator I(X86::RIP, this); I.isValid(); ++I)
284    Reserved.set(*I);
285
286  // Set the frame-pointer register and its aliases as reserved if needed.
287  if (TFI->hasFP(MF)) {
288    Reserved.set(X86::RBP);
289    for (MCSubRegIterator I(X86::RBP, this); I.isValid(); ++I)
290      Reserved.set(*I);
291  }
292
293  // Mark the segment registers as reserved.
294  Reserved.set(X86::CS);
295  Reserved.set(X86::SS);
296  Reserved.set(X86::DS);
297  Reserved.set(X86::ES);
298  Reserved.set(X86::FS);
299  Reserved.set(X86::GS);
300
301  // Mark the floating point stack registers as reserved.
302  Reserved.set(X86::ST0);
303  Reserved.set(X86::ST1);
304  Reserved.set(X86::ST2);
305  Reserved.set(X86::ST3);
306  Reserved.set(X86::ST4);
307  Reserved.set(X86::ST5);
308  Reserved.set(X86::ST6);
309  Reserved.set(X86::ST7);
310
311  // Reserve the registers that only exist in 64-bit mode.
312  if (!Is64Bit) {
313    // These 8-bit registers are part of the x86-64 extension even though their
314    // super-registers are old 32-bits.
315    Reserved.set(X86::SIL);
316    Reserved.set(X86::DIL);
317    Reserved.set(X86::BPL);
318    Reserved.set(X86::SPL);
319
320    for (unsigned n = 0; n != 8; ++n) {
321      // R8, R9, ...
322      static const uint16_t GPR64[] = {
323        X86::R8,  X86::R9,  X86::R10, X86::R11,
324        X86::R12, X86::R13, X86::R14, X86::R15
325      };
326      for (MCRegAliasIterator AI(GPR64[n], this, true); AI.isValid(); ++AI)
327        Reserved.set(*AI);
328
329      // XMM8, XMM9, ...
330      assert(X86::XMM15 == X86::XMM8+7);
331      for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
332        Reserved.set(*AI);
333    }
334  }
335
336  return Reserved;
337}
338
339//===----------------------------------------------------------------------===//
340// Stack Frame Processing methods
341//===----------------------------------------------------------------------===//
342
343bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
344  const MachineFrameInfo *MFI = MF.getFrameInfo();
345  return (MF.getTarget().Options.RealignStack &&
346          !MFI->hasVarSizedObjects());
347}
348
349bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
350  const MachineFrameInfo *MFI = MF.getFrameInfo();
351  const Function *F = MF.getFunction();
352  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
353  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
354                               F->hasFnAttr(Attribute::StackAlignment));
355
356  // FIXME: Currently we don't support stack realignment for functions with
357  //        variable-sized allocas.
358  // FIXME: It's more complicated than this...
359  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
360    report_fatal_error(
361      "Stack realignment in presence of dynamic allocas is not supported");
362
363  // If we've requested that we force align the stack do so now.
364  if (ForceStackAlign)
365    return canRealignStack(MF);
366
367  return requiresRealignment && canRealignStack(MF);
368}
369
370bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
371                                           unsigned Reg, int &FrameIdx) const {
372  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
373
374  if (Reg == FramePtr && TFI->hasFP(MF)) {
375    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
376    return true;
377  }
378  return false;
379}
380
381static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
382  if (is64Bit) {
383    if (isInt<8>(Imm))
384      return X86::SUB64ri8;
385    return X86::SUB64ri32;
386  } else {
387    if (isInt<8>(Imm))
388      return X86::SUB32ri8;
389    return X86::SUB32ri;
390  }
391}
392
393static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
394  if (is64Bit) {
395    if (isInt<8>(Imm))
396      return X86::ADD64ri8;
397    return X86::ADD64ri32;
398  } else {
399    if (isInt<8>(Imm))
400      return X86::ADD32ri8;
401    return X86::ADD32ri;
402  }
403}
404
405void X86RegisterInfo::
406eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
407                              MachineBasicBlock::iterator I) const {
408  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
409  bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
410  int Opcode = I->getOpcode();
411  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
412  DebugLoc DL = I->getDebugLoc();
413  uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
414  uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
415  I = MBB.erase(I);
416
417  if (!reseveCallFrame) {
418    // If the stack pointer can be changed after prologue, turn the
419    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
420    // adjcallstackdown instruction into 'add ESP, <amt>'
421    // TODO: consider using push / pop instead of sub + store / add
422    if (Amount == 0)
423      return;
424
425    // We need to keep the stack aligned properly.  To do this, we round the
426    // amount of space needed for the outgoing arguments up to the next
427    // alignment boundary.
428    unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
429    Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
430
431    MachineInstr *New = 0;
432    if (Opcode == TII.getCallFrameSetupOpcode()) {
433      New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
434                    StackPtr)
435        .addReg(StackPtr)
436        .addImm(Amount);
437    } else {
438      assert(Opcode == TII.getCallFrameDestroyOpcode());
439
440      // Factor out the amount the callee already popped.
441      Amount -= CalleeAmt;
442
443      if (Amount) {
444        unsigned Opc = getADDriOpcode(Is64Bit, Amount);
445        New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
446          .addReg(StackPtr).addImm(Amount);
447      }
448    }
449
450    if (New) {
451      // The EFLAGS implicit def is dead.
452      New->getOperand(3).setIsDead();
453
454      // Replace the pseudo instruction with a new instruction.
455      MBB.insert(I, New);
456    }
457
458    return;
459  }
460
461  if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
462    // If we are performing frame pointer elimination and if the callee pops
463    // something off the stack pointer, add it back.  We do this until we have
464    // more advanced stack pointer tracking ability.
465    unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
466    MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
467      .addReg(StackPtr).addImm(CalleeAmt);
468
469    // The EFLAGS implicit def is dead.
470    New->getOperand(3).setIsDead();
471
472    // We are not tracking the stack pointer adjustment by the callee, so make
473    // sure we restore the stack pointer immediately after the call, there may
474    // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
475    MachineBasicBlock::iterator B = MBB.begin();
476    while (I != B && !llvm::prior(I)->isCall())
477      --I;
478    MBB.insert(I, New);
479  }
480}
481
482void
483X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
484                                     int SPAdj, RegScavenger *RS) const{
485  assert(SPAdj == 0 && "Unexpected");
486
487  unsigned i = 0;
488  MachineInstr &MI = *II;
489  MachineFunction &MF = *MI.getParent()->getParent();
490  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
491
492  while (!MI.getOperand(i).isFI()) {
493    ++i;
494    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
495  }
496
497  int FrameIndex = MI.getOperand(i).getIndex();
498  unsigned BasePtr;
499
500  unsigned Opc = MI.getOpcode();
501  bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
502  if (needsStackRealignment(MF))
503    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
504  else if (AfterFPPop)
505    BasePtr = StackPtr;
506  else
507    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
508
509  // This must be part of a four operand memory reference.  Replace the
510  // FrameIndex with base register with EBP.  Add an offset to the offset.
511  MI.getOperand(i).ChangeToRegister(BasePtr, false);
512
513  // Now add the frame object offset to the offset from EBP.
514  int FIOffset;
515  if (AfterFPPop) {
516    // Tail call jmp happens after FP is popped.
517    const MachineFrameInfo *MFI = MF.getFrameInfo();
518    FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
519  } else
520    FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
521
522  if (MI.getOperand(i+3).isImm()) {
523    // Offset is a 32-bit integer.
524    int Imm = (int)(MI.getOperand(i + 3).getImm());
525    int Offset = FIOffset + Imm;
526    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
527           "Requesting 64-bit offset in 32-bit immediate!");
528    MI.getOperand(i + 3).ChangeToImmediate(Offset);
529  } else {
530    // Offset is symbolic. This is extremely rare.
531    uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
532    MI.getOperand(i+3).setOffset(Offset);
533  }
534}
535
536unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
537  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
538  return TFI->hasFP(MF) ? FramePtr : StackPtr;
539}
540
541unsigned X86RegisterInfo::getEHExceptionRegister() const {
542  llvm_unreachable("What is the exception register");
543}
544
545unsigned X86RegisterInfo::getEHHandlerRegister() const {
546  llvm_unreachable("What is the exception handler register");
547}
548
549namespace llvm {
550unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
551  switch (VT.getSimpleVT().SimpleTy) {
552  default: return Reg;
553  case MVT::i8:
554    if (High) {
555      switch (Reg) {
556      default: return getX86SubSuperRegister(Reg, MVT::i64, High);
557      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
558        return X86::AH;
559      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
560        return X86::DH;
561      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
562        return X86::CH;
563      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
564        return X86::BH;
565      }
566    } else {
567      switch (Reg) {
568      default: return 0;
569      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
570        return X86::AL;
571      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
572        return X86::DL;
573      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
574        return X86::CL;
575      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
576        return X86::BL;
577      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
578        return X86::SIL;
579      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
580        return X86::DIL;
581      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
582        return X86::BPL;
583      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
584        return X86::SPL;
585      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
586        return X86::R8B;
587      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
588        return X86::R9B;
589      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
590        return X86::R10B;
591      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
592        return X86::R11B;
593      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
594        return X86::R12B;
595      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
596        return X86::R13B;
597      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
598        return X86::R14B;
599      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
600        return X86::R15B;
601      }
602    }
603  case MVT::i16:
604    switch (Reg) {
605    default: return Reg;
606    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
607      return X86::AX;
608    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
609      return X86::DX;
610    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
611      return X86::CX;
612    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
613      return X86::BX;
614    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
615      return X86::SI;
616    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
617      return X86::DI;
618    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
619      return X86::BP;
620    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
621      return X86::SP;
622    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
623      return X86::R8W;
624    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
625      return X86::R9W;
626    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
627      return X86::R10W;
628    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
629      return X86::R11W;
630    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
631      return X86::R12W;
632    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
633      return X86::R13W;
634    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
635      return X86::R14W;
636    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
637      return X86::R15W;
638    }
639  case MVT::i32:
640    switch (Reg) {
641    default: return Reg;
642    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
643      return X86::EAX;
644    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
645      return X86::EDX;
646    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
647      return X86::ECX;
648    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
649      return X86::EBX;
650    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
651      return X86::ESI;
652    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
653      return X86::EDI;
654    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
655      return X86::EBP;
656    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
657      return X86::ESP;
658    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
659      return X86::R8D;
660    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
661      return X86::R9D;
662    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
663      return X86::R10D;
664    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
665      return X86::R11D;
666    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
667      return X86::R12D;
668    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
669      return X86::R13D;
670    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
671      return X86::R14D;
672    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
673      return X86::R15D;
674    }
675  case MVT::i64:
676    // For 64-bit mode if we've requested a "high" register and the
677    // Q or r constraints we want one of these high registers or
678    // just the register name otherwise.
679    if (High) {
680      switch (Reg) {
681      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
682        return X86::SI;
683      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
684        return X86::DI;
685      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
686        return X86::BP;
687      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
688        return X86::SP;
689      // Fallthrough.
690      }
691    }
692    switch (Reg) {
693    default: return Reg;
694    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
695      return X86::RAX;
696    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
697      return X86::RDX;
698    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
699      return X86::RCX;
700    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
701      return X86::RBX;
702    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
703      return X86::RSI;
704    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
705      return X86::RDI;
706    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
707      return X86::RBP;
708    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
709      return X86::RSP;
710    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
711      return X86::R8;
712    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
713      return X86::R9;
714    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
715      return X86::R10;
716    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
717      return X86::R11;
718    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
719      return X86::R12;
720    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
721      return X86::R13;
722    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
723      return X86::R14;
724    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
725      return X86::R15;
726    }
727  }
728}
729}
730
731namespace {
732  struct MSAH : public MachineFunctionPass {
733    static char ID;
734    MSAH() : MachineFunctionPass(ID) {}
735
736    virtual bool runOnMachineFunction(MachineFunction &MF) {
737      const X86TargetMachine *TM =
738        static_cast<const X86TargetMachine *>(&MF.getTarget());
739      const TargetFrameLowering *TFI = TM->getFrameLowering();
740      MachineRegisterInfo &RI = MF.getRegInfo();
741      X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
742      unsigned StackAlignment = TFI->getStackAlignment();
743
744      // Be over-conservative: scan over all vreg defs and find whether vector
745      // registers are used. If yes, there is a possibility that vector register
746      // will be spilled and thus require dynamic stack realignment.
747      for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
748        unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
749        if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
750          FuncInfo->setForceFramePointer(true);
751          return true;
752        }
753      }
754      // Nothing to do
755      return false;
756    }
757
758    virtual const char *getPassName() const {
759      return "X86 Maximal Stack Alignment Check";
760    }
761
762    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
763      AU.setPreservesCFG();
764      MachineFunctionPass::getAnalysisUsage(AU);
765    }
766  };
767
768  char MSAH::ID = 0;
769}
770
771FunctionPass*
772llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
773