X86RegisterInfo.cpp revision 623d2e618f4e672c47edff9ec63ed6d733ac81d3 
1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86RegisterInfo.h"
17#include "X86.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/ValueTypes.h"
31#include "llvm/IR/Constants.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/Type.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Target/TargetFrameLowering.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Target/TargetOptions.h"
41
42#define GET_REGINFO_TARGET_DESC
43#include "X86GenRegisterInfo.inc"
44
45using namespace llvm;
46
47cl::opt<bool>
48ForceStackAlign("force-align-stack",
49                 cl::desc("Force align the stack to the minimum alignment"
50                           " needed for the function."),
51                 cl::init(false), cl::Hidden);
52
53static cl::opt<bool>
54EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm)
58  : X86GenRegisterInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
59                         ? X86::RIP : X86::EIP),
60                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
61                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true),
62                       (tm.getSubtarget<X86Subtarget>().is64Bit()
63                         ? X86::RIP : X86::EIP)),
64                       TM(tm) {
65  X86_MC::InitLLVM2SEHRegisterMapping(this);
66
67  // Cache some information.
68  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
69  Is64Bit = Subtarget->is64Bit();
70  IsWin64 = Subtarget->isTargetWin64();
71
72  if (Is64Bit) {
73    SlotSize = 8;
74    StackPtr = X86::RSP;
75    FramePtr = X86::RBP;
76  } else {
77    SlotSize = 4;
78    StackPtr = X86::ESP;
79    FramePtr = X86::EBP;
80  }
81  // Use a callee-saved register as the base pointer.  These registers must
82  // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
83  // requires GOT in the EBX register before function calls via PLT GOT pointer.
84  BasePtr = Is64Bit ? X86::RBX : X86::ESI;
85}
86
87/// getCompactUnwindRegNum - This function maps the register to the number for
88/// compact unwind encoding. Return -1 if the register isn't valid.
89int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
90  switch (getLLVMRegNum(RegNum, isEH)) {
91  case X86::EBX: case X86::RBX: return 1;
92  case X86::ECX: case X86::R12: return 2;
93  case X86::EDX: case X86::R13: return 3;
94  case X86::EDI: case X86::R14: return 4;
95  case X86::ESI: case X86::R15: return 5;
96  case X86::EBP: case X86::RBP: return 6;
97  }
98
99  return -1;
100}
101
102bool
103X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
104  // ExeDepsFixer and PostRAScheduler require liveness.
105  return true;
106}
107
108int
109X86RegisterInfo::getSEHRegNum(unsigned i) const {
110  return getEncodingValue(i);
111}
112
113const TargetRegisterClass *
114X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
115                                       unsigned Idx) const {
116  // The sub_8bit sub-register index is more constrained in 32-bit mode.
117  // It behaves just like the sub_8bit_hi index.
118  if (!Is64Bit && Idx == X86::sub_8bit)
119    Idx = X86::sub_8bit_hi;
120
121  // Forward to TableGen's default version.
122  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
123}
124
125const TargetRegisterClass *
126X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
127                                          const TargetRegisterClass *B,
128                                          unsigned SubIdx) const {
129  // The sub_8bit sub-register index is more constrained in 32-bit mode.
130  if (!Is64Bit && SubIdx == X86::sub_8bit) {
131    A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
132    if (!A)
133      return 0;
134  }
135  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
136}
137
138const TargetRegisterClass*
139X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
140  // Don't allow super-classes of GR8_NOREX.  This class is only used after
141  // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
142  // to the full GR8 register class in 64-bit mode, so we cannot allow the
143  // reigster class inflation.
144  //
145  // The GR8_NOREX class is always used in a way that won't be constrained to a
146  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
147  // full GR8 class.
148  if (RC == &X86::GR8_NOREXRegClass)
149    return RC;
150
151  const TargetRegisterClass *Super = RC;
152  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
153  do {
154    switch (Super->getID()) {
155    case X86::GR8RegClassID:
156    case X86::GR16RegClassID:
157    case X86::GR32RegClassID:
158    case X86::GR64RegClassID:
159    case X86::FR32RegClassID:
160    case X86::FR64RegClassID:
161    case X86::RFP32RegClassID:
162    case X86::RFP64RegClassID:
163    case X86::RFP80RegClassID:
164    case X86::VR128RegClassID:
165    case X86::VR256RegClassID:
166      // Don't return a super-class that would shrink the spill size.
167      // That can happen with the vector and float classes.
168      if (Super->getSize() == RC->getSize())
169        return Super;
170    }
171    Super = *I++;
172  } while (Super);
173  return RC;
174}
175
176const TargetRegisterClass *
177X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
178                                                                         const {
179  const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
180  switch (Kind) {
181  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
182  case 0: // Normal GPRs.
183    if (Subtarget.isTarget64BitLP64())
184      return &X86::GR64RegClass;
185    return &X86::GR32RegClass;
186  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
187    if (Subtarget.isTarget64BitLP64())
188      return &X86::GR64_NOSPRegClass;
189    return &X86::GR32_NOSPRegClass;
190  case 2: // Available for tailcall (not callee-saved GPRs).
191    if (Subtarget.isTargetWin64())
192      return &X86::GR64_TCW64RegClass;
193    else if (Subtarget.is64Bit())
194      return &X86::GR64_TCRegClass;
195
196    const Function *F = MF.getFunction();
197    bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
198    if (hasHipeCC)
199      return &X86::GR32RegClass;
200    return &X86::GR32_TCRegClass;
201  }
202}
203
204const TargetRegisterClass *
205X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
206  if (RC == &X86::CCRRegClass) {
207    if (Is64Bit)
208      return &X86::GR64RegClass;
209    else
210      return &X86::GR32RegClass;
211  }
212  return RC;
213}
214
215unsigned
216X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
217                                     MachineFunction &MF) const {
218  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
219
220  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
221  switch (RC->getID()) {
222  default:
223    return 0;
224  case X86::GR32RegClassID:
225    return 4 - FPDiff;
226  case X86::GR64RegClassID:
227    return 12 - FPDiff;
228  case X86::VR128RegClassID:
229    return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
230  case X86::VR64RegClassID:
231    return 4;
232  }
233}
234
235const uint16_t *
236X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
237  switch (MF->getFunction()->getCallingConv()) {
238  case CallingConv::GHC:
239  case CallingConv::HiPE:
240    return CSR_NoRegs_SaveList;
241
242  case CallingConv::WebKit_JS:
243  case CallingConv::AnyReg:
244    return CSR_MostRegs_64_SaveList;
245
246  case CallingConv::Intel_OCL_BI: {
247    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
248    bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
249    if (HasAVX512 && IsWin64)
250      return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
251    if (HasAVX512 && Is64Bit)
252      return CSR_64_Intel_OCL_BI_AVX512_SaveList;
253    if (HasAVX && IsWin64)
254      return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
255    if (HasAVX && Is64Bit)
256      return CSR_64_Intel_OCL_BI_AVX_SaveList;
257    if (!HasAVX && !IsWin64 && Is64Bit)
258      return CSR_64_Intel_OCL_BI_SaveList;
259    break;
260  }
261
262  case CallingConv::Cold:
263    if (Is64Bit)
264      return CSR_MostRegs_64_SaveList;
265    break;
266
267  default:
268    break;
269  }
270
271  bool CallsEHReturn = MF->getMMI().callsEHReturn();
272  if (Is64Bit) {
273    if (IsWin64)
274      return CSR_Win64_SaveList;
275    if (CallsEHReturn)
276      return CSR_64EHRet_SaveList;
277    return CSR_64_SaveList;
278  }
279  if (CallsEHReturn)
280    return CSR_32EHRet_SaveList;
281  return CSR_32_SaveList;
282}
283
284const uint32_t*
285X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
286  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
287  bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
288
289  if (CC == CallingConv::Intel_OCL_BI) {
290    if (IsWin64 && HasAVX512)
291      return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
292    if (Is64Bit && HasAVX512)
293      return CSR_64_Intel_OCL_BI_AVX512_RegMask;
294    if (IsWin64 && HasAVX)
295      return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
296    if (Is64Bit && HasAVX)
297      return CSR_64_Intel_OCL_BI_AVX_RegMask;
298    if (!HasAVX && !IsWin64 && Is64Bit)
299      return CSR_64_Intel_OCL_BI_RegMask;
300  }
301  if (CC == CallingConv::GHC || CC == CallingConv::HiPE)
302    return CSR_NoRegs_RegMask;
303  if (CC == CallingConv::WebKit_JS || CC == CallingConv::AnyReg)
304    return CSR_MostRegs_64_RegMask;
305  if (!Is64Bit)
306    return CSR_32_RegMask;
307  if (CC == CallingConv::Cold)
308    return CSR_MostRegs_64_RegMask;
309  if (IsWin64)
310    return CSR_Win64_RegMask;
311  return CSR_64_RegMask;
312}
313
314const uint32_t*
315X86RegisterInfo::getNoPreservedMask() const {
316  return CSR_NoRegs_RegMask;
317}
318
319BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
320  BitVector Reserved(getNumRegs());
321  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
322
323  // Set the stack-pointer register and its aliases as reserved.
324  for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
325       ++I)
326    Reserved.set(*I);
327
328  // Set the instruction pointer register and its aliases as reserved.
329  for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
330       ++I)
331    Reserved.set(*I);
332
333  // Set the frame-pointer register and its aliases as reserved if needed.
334  if (TFI->hasFP(MF)) {
335    for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
336         ++I)
337      Reserved.set(*I);
338  }
339
340  // Set the base-pointer register and its aliases as reserved if needed.
341  if (hasBasePointer(MF)) {
342    CallingConv::ID CC = MF.getFunction()->getCallingConv();
343    const uint32_t* RegMask = getCallPreservedMask(CC);
344    if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
345      report_fatal_error(
346        "Stack realignment in presence of dynamic allocas is not supported with"
347        "this calling convention.");
348
349    for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
350         I.isValid(); ++I)
351      Reserved.set(*I);
352  }
353
354  // Mark the segment registers as reserved.
355  Reserved.set(X86::CS);
356  Reserved.set(X86::SS);
357  Reserved.set(X86::DS);
358  Reserved.set(X86::ES);
359  Reserved.set(X86::FS);
360  Reserved.set(X86::GS);
361
362  // Mark the floating point stack registers as reserved.
363  for (unsigned n = 0; n != 8; ++n)
364    Reserved.set(X86::ST0 + n);
365
366  // Reserve the registers that only exist in 64-bit mode.
367  if (!Is64Bit) {
368    // These 8-bit registers are part of the x86-64 extension even though their
369    // super-registers are old 32-bits.
370    Reserved.set(X86::SIL);
371    Reserved.set(X86::DIL);
372    Reserved.set(X86::BPL);
373    Reserved.set(X86::SPL);
374
375    for (unsigned n = 0; n != 8; ++n) {
376      // R8, R9, ...
377      for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
378        Reserved.set(*AI);
379
380      // XMM8, XMM9, ...
381      for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
382        Reserved.set(*AI);
383    }
384  }
385  if (!Is64Bit || !TM.getSubtarget<X86Subtarget>().hasAVX512()) {
386    for (unsigned n = 16; n != 32; ++n) {
387      for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
388        Reserved.set(*AI);
389    }
390  }
391
392  return Reserved;
393}
394
395//===----------------------------------------------------------------------===//
396// Stack Frame Processing methods
397//===----------------------------------------------------------------------===//
398
399bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
400   const MachineFrameInfo *MFI = MF.getFrameInfo();
401
402   if (!EnableBasePointer)
403     return false;
404
405   // When we need stack realignment and there are dynamic allocas, we can't
406   // reference off of the stack pointer, so we reserve a base pointer.
407   //
408   // This is also true if the function contain MS-style inline assembly.  We
409   // do this because if any stack changes occur in the inline assembly, e.g.,
410   // "pusha", then any C local variable or C argument references in the
411   // inline assembly will be wrong because the SP is not properly tracked.
412   if ((needsStackRealignment(MF) && MFI->hasVarSizedObjects()) ||
413       MF.hasMSInlineAsm())
414     return true;
415
416   return false;
417}
418
419bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
420  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
421    return false;
422
423  const MachineFrameInfo *MFI = MF.getFrameInfo();
424  const MachineRegisterInfo *MRI = &MF.getRegInfo();
425
426  // Stack realignment requires a frame pointer.  If we already started
427  // register allocation with frame pointer elimination, it is too late now.
428  if (!MRI->canReserveReg(FramePtr))
429    return false;
430
431  // If a base pointer is necessary.  Check that it isn't too late to reserve
432  // it.
433  if (MFI->hasVarSizedObjects())
434    return MRI->canReserveReg(BasePtr);
435  return true;
436}
437
438bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
439  const MachineFrameInfo *MFI = MF.getFrameInfo();
440  const Function *F = MF.getFunction();
441  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
442  bool requiresRealignment =
443    ((MFI->getMaxAlignment() > StackAlign) ||
444     F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
445                                     Attribute::StackAlignment));
446
447  // If we've requested that we force align the stack do so now.
448  if (ForceStackAlign)
449    return canRealignStack(MF);
450
451  return requiresRealignment && canRealignStack(MF);
452}
453
454bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
455                                           unsigned Reg, int &FrameIdx) const {
456  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
457
458  if (Reg == FramePtr && TFI->hasFP(MF)) {
459    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
460    return true;
461  }
462  return false;
463}
464
465void
466X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
467                                     int SPAdj, unsigned FIOperandNum,
468                                     RegScavenger *RS) const {
469  assert(SPAdj == 0 && "Unexpected");
470
471  MachineInstr &MI = *II;
472  MachineFunction &MF = *MI.getParent()->getParent();
473  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
474  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
475  unsigned BasePtr;
476
477  unsigned Opc = MI.getOpcode();
478  bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
479  if (hasBasePointer(MF))
480    BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
481  else if (needsStackRealignment(MF))
482    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
483  else if (AfterFPPop)
484    BasePtr = StackPtr;
485  else
486    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
487
488  // This must be part of a four operand memory reference.  Replace the
489  // FrameIndex with base register with EBP.  Add an offset to the offset.
490  MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
491
492  // Now add the frame object offset to the offset from EBP.
493  int FIOffset;
494  if (AfterFPPop) {
495    // Tail call jmp happens after FP is popped.
496    const MachineFrameInfo *MFI = MF.getFrameInfo();
497    FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
498  } else
499    FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
500
501  if (MI.getOperand(FIOperandNum+3).isImm()) {
502    // Offset is a 32-bit integer.
503    int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
504    int Offset = FIOffset + Imm;
505    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
506           "Requesting 64-bit offset in 32-bit immediate!");
507    MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
508  } else {
509    // Offset is symbolic. This is extremely rare.
510    uint64_t Offset = FIOffset +
511      (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
512    MI.getOperand(FIOperandNum + 3).setOffset(Offset);
513  }
514}
515
516unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
517  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
518  return TFI->hasFP(MF) ? FramePtr : StackPtr;
519}
520
521namespace llvm {
522unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
523                                bool High) {
524  switch (VT) {
525  default: llvm_unreachable("Unexpected VT");
526  case MVT::i8:
527    if (High) {
528      switch (Reg) {
529      default: return getX86SubSuperRegister(Reg, MVT::i64);
530      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
531        return X86::SI;
532      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
533        return X86::DI;
534      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
535        return X86::BP;
536      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
537        return X86::SP;
538      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
539        return X86::AH;
540      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
541        return X86::DH;
542      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
543        return X86::CH;
544      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
545        return X86::BH;
546      }
547    } else {
548      switch (Reg) {
549      default: llvm_unreachable("Unexpected register");
550      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
551        return X86::AL;
552      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
553        return X86::DL;
554      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
555        return X86::CL;
556      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
557        return X86::BL;
558      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
559        return X86::SIL;
560      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
561        return X86::DIL;
562      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
563        return X86::BPL;
564      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
565        return X86::SPL;
566      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
567        return X86::R8B;
568      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
569        return X86::R9B;
570      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
571        return X86::R10B;
572      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
573        return X86::R11B;
574      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
575        return X86::R12B;
576      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
577        return X86::R13B;
578      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
579        return X86::R14B;
580      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
581        return X86::R15B;
582      }
583    }
584  case MVT::i16:
585    switch (Reg) {
586    default: llvm_unreachable("Unexpected register");
587    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
588      return X86::AX;
589    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
590      return X86::DX;
591    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
592      return X86::CX;
593    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
594      return X86::BX;
595    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
596      return X86::SI;
597    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
598      return X86::DI;
599    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
600      return X86::BP;
601    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
602      return X86::SP;
603    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
604      return X86::R8W;
605    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
606      return X86::R9W;
607    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
608      return X86::R10W;
609    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
610      return X86::R11W;
611    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
612      return X86::R12W;
613    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
614      return X86::R13W;
615    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
616      return X86::R14W;
617    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
618      return X86::R15W;
619    }
620  case MVT::i32:
621    switch (Reg) {
622    default: llvm_unreachable("Unexpected register");
623    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
624      return X86::EAX;
625    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
626      return X86::EDX;
627    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
628      return X86::ECX;
629    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
630      return X86::EBX;
631    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
632      return X86::ESI;
633    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
634      return X86::EDI;
635    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
636      return X86::EBP;
637    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
638      return X86::ESP;
639    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
640      return X86::R8D;
641    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
642      return X86::R9D;
643    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
644      return X86::R10D;
645    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
646      return X86::R11D;
647    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
648      return X86::R12D;
649    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
650      return X86::R13D;
651    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
652      return X86::R14D;
653    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
654      return X86::R15D;
655    }
656  case MVT::i64:
657    switch (Reg) {
658    default: llvm_unreachable("Unexpected register");
659    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
660      return X86::RAX;
661    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
662      return X86::RDX;
663    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
664      return X86::RCX;
665    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
666      return X86::RBX;
667    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
668      return X86::RSI;
669    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
670      return X86::RDI;
671    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
672      return X86::RBP;
673    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
674      return X86::RSP;
675    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
676      return X86::R8;
677    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
678      return X86::R9;
679    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
680      return X86::R10;
681    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
682      return X86::R11;
683    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
684      return X86::R12;
685    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
686      return X86::R13;
687    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
688      return X86::R14;
689    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
690      return X86::R15;
691    }
692  }
693}
694
695unsigned get512BitSuperRegister(unsigned Reg) {
696  if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
697    return X86::ZMM0 + (Reg - X86::XMM0);
698  if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
699    return X86::ZMM0 + (Reg - X86::YMM0);
700  if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
701    return Reg;
702  llvm_unreachable("Unexpected SIMD register");
703}
704
705}
706