X86RegisterInfo.cpp revision 66413b61f0fee8f8177aeadb27d16e8eb7d30472 
1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86RegisterInfo.h"
17#include "X86.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineModuleInfo.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/MC/MCAsmInfo.h"
33#include "llvm/Target/TargetFrameLowering.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/STLExtras.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/CommandLine.h"
41
42#define GET_REGINFO_TARGET_DESC
43#include "X86GenRegisterInfo.inc"
44
45using namespace llvm;
46
47cl::opt<bool>
48ForceStackAlign("force-align-stack",
49                 cl::desc("Force align the stack to the minimum alignment"
50                           " needed for the function."),
51                 cl::init(false), cl::Hidden);
52
53X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
54                                 const TargetInstrInfo &tii)
55  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
56                         ? X86::RIP : X86::EIP,
57                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
58                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
59                       TM(tm), TII(tii) {
60  X86_MC::InitLLVM2SEHRegisterMapping(this);
61
62  // Cache some information.
63  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64  Is64Bit = Subtarget->is64Bit();
65  IsWin64 = Subtarget->isTargetWin64();
66
67  if (Is64Bit) {
68    SlotSize = 8;
69    StackPtr = X86::RSP;
70    FramePtr = X86::RBP;
71  } else {
72    SlotSize = 4;
73    StackPtr = X86::ESP;
74    FramePtr = X86::EBP;
75  }
76}
77
78/// getCompactUnwindRegNum - This function maps the register to the number for
79/// compact unwind encoding. Return -1 if the register isn't valid.
80int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
81  switch (getLLVMRegNum(RegNum, isEH)) {
82  case X86::EBX: case X86::RBX: return 1;
83  case X86::ECX: case X86::R12: return 2;
84  case X86::EDX: case X86::R13: return 3;
85  case X86::EDI: case X86::R14: return 4;
86  case X86::ESI: case X86::R15: return 5;
87  case X86::EBP: case X86::RBP: return 6;
88  }
89
90  return -1;
91}
92
93bool
94X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
95  // Only enable when post-RA scheduling is enabled and this is needed.
96  return TM.getSubtargetImpl()->postRAScheduler();
97}
98
99int
100X86RegisterInfo::getSEHRegNum(unsigned i) const {
101  int reg = X86_MC::getX86RegNum(i);
102  switch (i) {
103  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
104  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
105  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
106  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
107  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
108  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
109  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
110  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
111  case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
112  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
113  case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
114  case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
115    reg += 8;
116  }
117  return reg;
118}
119
120const TargetRegisterClass *
121X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
122                                       unsigned Idx) const {
123  // The sub_8bit sub-register index is more constrained in 32-bit mode.
124  // It behaves just like the sub_8bit_hi index.
125  if (!Is64Bit && Idx == X86::sub_8bit)
126    Idx = X86::sub_8bit_hi;
127
128  // Forward to TableGen's default version.
129  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
130}
131
132const TargetRegisterClass *
133X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
134                                          const TargetRegisterClass *B,
135                                          unsigned SubIdx) const {
136  // The sub_8bit sub-register index is more constrained in 32-bit mode.
137  if (!Is64Bit && SubIdx == X86::sub_8bit) {
138    A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
139    if (!A)
140      return 0;
141  }
142  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
143}
144
145const TargetRegisterClass*
146X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
147  // Don't allow super-classes of GR8_NOREX.  This class is only used after
148  // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
149  // to the full GR8 register class in 64-bit mode, so we cannot allow the
150  // reigster class inflation.
151  //
152  // The GR8_NOREX class is always used in a way that won't be constrained to a
153  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
154  // full GR8 class.
155  if (RC == &X86::GR8_NOREXRegClass)
156    return RC;
157
158  const TargetRegisterClass *Super = RC;
159  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
160  do {
161    switch (Super->getID()) {
162    case X86::GR8RegClassID:
163    case X86::GR16RegClassID:
164    case X86::GR32RegClassID:
165    case X86::GR64RegClassID:
166    case X86::FR32RegClassID:
167    case X86::FR64RegClassID:
168    case X86::RFP32RegClassID:
169    case X86::RFP64RegClassID:
170    case X86::RFP80RegClassID:
171    case X86::VR128RegClassID:
172    case X86::VR256RegClassID:
173      // Don't return a super-class that would shrink the spill size.
174      // That can happen with the vector and float classes.
175      if (Super->getSize() == RC->getSize())
176        return Super;
177    }
178    Super = *I++;
179  } while (Super);
180  return RC;
181}
182
183const TargetRegisterClass *
184X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
185  switch (Kind) {
186  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
187  case 0: // Normal GPRs.
188    if (TM.getSubtarget<X86Subtarget>().is64Bit())
189      return &X86::GR64RegClass;
190    return &X86::GR32RegClass;
191  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
192    if (TM.getSubtarget<X86Subtarget>().is64Bit())
193      return &X86::GR64_NOSPRegClass;
194    return &X86::GR32_NOSPRegClass;
195  case 2: // Available for tailcall (not callee-saved GPRs).
196    if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
197      return &X86::GR64_TCW64RegClass;
198    if (TM.getSubtarget<X86Subtarget>().is64Bit())
199      return &X86::GR64_TCRegClass;
200    return &X86::GR32_TCRegClass;
201  }
202}
203
204const TargetRegisterClass *
205X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
206  if (RC == &X86::CCRRegClass) {
207    if (Is64Bit)
208      return &X86::GR64RegClass;
209    else
210      return &X86::GR32RegClass;
211  }
212  return RC;
213}
214
215unsigned
216X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
217                                     MachineFunction &MF) const {
218  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
219
220  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
221  switch (RC->getID()) {
222  default:
223    return 0;
224  case X86::GR32RegClassID:
225    return 4 - FPDiff;
226  case X86::GR64RegClassID:
227    return 12 - FPDiff;
228  case X86::VR128RegClassID:
229    return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
230  case X86::VR64RegClassID:
231    return 4;
232  }
233}
234
235const uint16_t *
236X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
237  bool callsEHReturn = false;
238  bool ghcCall = false;
239
240  if (MF) {
241    callsEHReturn = MF->getMMI().callsEHReturn();
242    const Function *F = MF->getFunction();
243    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
244  }
245
246  if (ghcCall)
247    return CSR_Ghc_SaveList;
248  if (Is64Bit) {
249    if (IsWin64)
250      return CSR_Win64_SaveList;
251    if (callsEHReturn)
252      return CSR_64EHRet_SaveList;
253    return CSR_64_SaveList;
254  }
255  if (callsEHReturn)
256    return CSR_32EHRet_SaveList;
257  return CSR_32_SaveList;
258}
259
260const uint32_t*
261X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
262  if (CC == CallingConv::GHC)
263    return CSR_Ghc_RegMask;
264  if (!Is64Bit)
265    return CSR_32_RegMask;
266  if (IsWin64)
267    return CSR_Win64_RegMask;
268  return CSR_64_RegMask;
269}
270
271BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
272  BitVector Reserved(getNumRegs());
273  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
274
275  // Set the stack-pointer register and its aliases as reserved.
276  Reserved.set(X86::RSP);
277  Reserved.set(X86::ESP);
278  Reserved.set(X86::SP);
279  Reserved.set(X86::SPL);
280
281  // Set the instruction pointer register and its aliases as reserved.
282  Reserved.set(X86::RIP);
283  Reserved.set(X86::EIP);
284  Reserved.set(X86::IP);
285
286  // Set the frame-pointer register and its aliases as reserved if needed.
287  if (TFI->hasFP(MF)) {
288    Reserved.set(X86::RBP);
289    Reserved.set(X86::EBP);
290    Reserved.set(X86::BP);
291    Reserved.set(X86::BPL);
292  }
293
294  // Mark the segment registers as reserved.
295  Reserved.set(X86::CS);
296  Reserved.set(X86::SS);
297  Reserved.set(X86::DS);
298  Reserved.set(X86::ES);
299  Reserved.set(X86::FS);
300  Reserved.set(X86::GS);
301
302  // Mark the floating point stack registers as reserved.
303  Reserved.set(X86::ST0);
304  Reserved.set(X86::ST1);
305  Reserved.set(X86::ST2);
306  Reserved.set(X86::ST3);
307  Reserved.set(X86::ST4);
308  Reserved.set(X86::ST5);
309  Reserved.set(X86::ST6);
310  Reserved.set(X86::ST7);
311
312  // Reserve the registers that only exist in 64-bit mode.
313  if (!Is64Bit) {
314    // These 8-bit registers are part of the x86-64 extension even though their
315    // super-registers are old 32-bits.
316    Reserved.set(X86::SIL);
317    Reserved.set(X86::DIL);
318    Reserved.set(X86::BPL);
319    Reserved.set(X86::SPL);
320
321    for (unsigned n = 0; n != 8; ++n) {
322      // R8, R9, ...
323      static const uint16_t GPR64[] = {
324        X86::R8,  X86::R9,  X86::R10, X86::R11,
325        X86::R12, X86::R13, X86::R14, X86::R15
326      };
327      for (const uint16_t *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
328        Reserved.set(Reg);
329
330      // XMM8, XMM9, ...
331      assert(X86::XMM15 == X86::XMM8+7);
332      for (const uint16_t *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
333           ++AI)
334        Reserved.set(Reg);
335    }
336  }
337
338  return Reserved;
339}
340
341//===----------------------------------------------------------------------===//
342// Stack Frame Processing methods
343//===----------------------------------------------------------------------===//
344
345bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
346  const MachineFrameInfo *MFI = MF.getFrameInfo();
347  return (MF.getTarget().Options.RealignStack &&
348          !MFI->hasVarSizedObjects());
349}
350
351bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
352  const MachineFrameInfo *MFI = MF.getFrameInfo();
353  const Function *F = MF.getFunction();
354  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
355  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
356                               F->hasFnAttr(Attribute::StackAlignment));
357
358  // FIXME: Currently we don't support stack realignment for functions with
359  //        variable-sized allocas.
360  // FIXME: It's more complicated than this...
361  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
362    report_fatal_error(
363      "Stack realignment in presence of dynamic allocas is not supported");
364
365  // If we've requested that we force align the stack do so now.
366  if (ForceStackAlign)
367    return canRealignStack(MF);
368
369  return requiresRealignment && canRealignStack(MF);
370}
371
372bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
373                                           unsigned Reg, int &FrameIdx) const {
374  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
375
376  if (Reg == FramePtr && TFI->hasFP(MF)) {
377    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
378    return true;
379  }
380  return false;
381}
382
383static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
384  if (is64Bit) {
385    if (isInt<8>(Imm))
386      return X86::SUB64ri8;
387    return X86::SUB64ri32;
388  } else {
389    if (isInt<8>(Imm))
390      return X86::SUB32ri8;
391    return X86::SUB32ri;
392  }
393}
394
395static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
396  if (is64Bit) {
397    if (isInt<8>(Imm))
398      return X86::ADD64ri8;
399    return X86::ADD64ri32;
400  } else {
401    if (isInt<8>(Imm))
402      return X86::ADD32ri8;
403    return X86::ADD32ri;
404  }
405}
406
407void X86RegisterInfo::
408eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
409                              MachineBasicBlock::iterator I) const {
410  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
411  bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
412  int Opcode = I->getOpcode();
413  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
414  DebugLoc DL = I->getDebugLoc();
415  uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
416  uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
417  I = MBB.erase(I);
418
419  if (!reseveCallFrame) {
420    // If the stack pointer can be changed after prologue, turn the
421    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
422    // adjcallstackdown instruction into 'add ESP, <amt>'
423    // TODO: consider using push / pop instead of sub + store / add
424    if (Amount == 0)
425      return;
426
427    // We need to keep the stack aligned properly.  To do this, we round the
428    // amount of space needed for the outgoing arguments up to the next
429    // alignment boundary.
430    unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
431    Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
432
433    MachineInstr *New = 0;
434    if (Opcode == TII.getCallFrameSetupOpcode()) {
435      New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
436                    StackPtr)
437        .addReg(StackPtr)
438        .addImm(Amount);
439    } else {
440      assert(Opcode == TII.getCallFrameDestroyOpcode());
441
442      // Factor out the amount the callee already popped.
443      Amount -= CalleeAmt;
444
445      if (Amount) {
446        unsigned Opc = getADDriOpcode(Is64Bit, Amount);
447        New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
448          .addReg(StackPtr).addImm(Amount);
449      }
450    }
451
452    if (New) {
453      // The EFLAGS implicit def is dead.
454      New->getOperand(3).setIsDead();
455
456      // Replace the pseudo instruction with a new instruction.
457      MBB.insert(I, New);
458    }
459
460    return;
461  }
462
463  if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
464    // If we are performing frame pointer elimination and if the callee pops
465    // something off the stack pointer, add it back.  We do this until we have
466    // more advanced stack pointer tracking ability.
467    unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
468    MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
469      .addReg(StackPtr).addImm(CalleeAmt);
470
471    // The EFLAGS implicit def is dead.
472    New->getOperand(3).setIsDead();
473
474    // We are not tracking the stack pointer adjustment by the callee, so make
475    // sure we restore the stack pointer immediately after the call, there may
476    // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
477    MachineBasicBlock::iterator B = MBB.begin();
478    while (I != B && !llvm::prior(I)->isCall())
479      --I;
480    MBB.insert(I, New);
481  }
482}
483
484void
485X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
486                                     int SPAdj, RegScavenger *RS) const{
487  assert(SPAdj == 0 && "Unexpected");
488
489  unsigned i = 0;
490  MachineInstr &MI = *II;
491  MachineFunction &MF = *MI.getParent()->getParent();
492  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
493
494  while (!MI.getOperand(i).isFI()) {
495    ++i;
496    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
497  }
498
499  int FrameIndex = MI.getOperand(i).getIndex();
500  unsigned BasePtr;
501
502  unsigned Opc = MI.getOpcode();
503  bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
504  if (needsStackRealignment(MF))
505    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
506  else if (AfterFPPop)
507    BasePtr = StackPtr;
508  else
509    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
510
511  // This must be part of a four operand memory reference.  Replace the
512  // FrameIndex with base register with EBP.  Add an offset to the offset.
513  MI.getOperand(i).ChangeToRegister(BasePtr, false);
514
515  // Now add the frame object offset to the offset from EBP.
516  int FIOffset;
517  if (AfterFPPop) {
518    // Tail call jmp happens after FP is popped.
519    const MachineFrameInfo *MFI = MF.getFrameInfo();
520    FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
521  } else
522    FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
523
524  if (MI.getOperand(i+3).isImm()) {
525    // Offset is a 32-bit integer.
526    int Imm = (int)(MI.getOperand(i + 3).getImm());
527    int Offset = FIOffset + Imm;
528    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
529           "Requesting 64-bit offset in 32-bit immediate!");
530    MI.getOperand(i + 3).ChangeToImmediate(Offset);
531  } else {
532    // Offset is symbolic. This is extremely rare.
533    uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
534    MI.getOperand(i+3).setOffset(Offset);
535  }
536}
537
538unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
539  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
540  return TFI->hasFP(MF) ? FramePtr : StackPtr;
541}
542
543unsigned X86RegisterInfo::getEHExceptionRegister() const {
544  llvm_unreachable("What is the exception register");
545}
546
547unsigned X86RegisterInfo::getEHHandlerRegister() const {
548  llvm_unreachable("What is the exception handler register");
549}
550
551namespace llvm {
552unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
553  switch (VT.getSimpleVT().SimpleTy) {
554  default: return Reg;
555  case MVT::i8:
556    if (High) {
557      switch (Reg) {
558      default: return getX86SubSuperRegister(Reg, MVT::i64, High);
559      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
560        return X86::AH;
561      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
562        return X86::DH;
563      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
564        return X86::CH;
565      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
566        return X86::BH;
567      }
568    } else {
569      switch (Reg) {
570      default: return 0;
571      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
572        return X86::AL;
573      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
574        return X86::DL;
575      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
576        return X86::CL;
577      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
578        return X86::BL;
579      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
580        return X86::SIL;
581      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
582        return X86::DIL;
583      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
584        return X86::BPL;
585      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
586        return X86::SPL;
587      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
588        return X86::R8B;
589      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
590        return X86::R9B;
591      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
592        return X86::R10B;
593      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
594        return X86::R11B;
595      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
596        return X86::R12B;
597      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
598        return X86::R13B;
599      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
600        return X86::R14B;
601      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
602        return X86::R15B;
603      }
604    }
605  case MVT::i16:
606    switch (Reg) {
607    default: return Reg;
608    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
609      return X86::AX;
610    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
611      return X86::DX;
612    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
613      return X86::CX;
614    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
615      return X86::BX;
616    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
617      return X86::SI;
618    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
619      return X86::DI;
620    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
621      return X86::BP;
622    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
623      return X86::SP;
624    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
625      return X86::R8W;
626    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
627      return X86::R9W;
628    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
629      return X86::R10W;
630    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
631      return X86::R11W;
632    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
633      return X86::R12W;
634    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
635      return X86::R13W;
636    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
637      return X86::R14W;
638    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
639      return X86::R15W;
640    }
641  case MVT::i32:
642    switch (Reg) {
643    default: return Reg;
644    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
645      return X86::EAX;
646    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
647      return X86::EDX;
648    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
649      return X86::ECX;
650    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
651      return X86::EBX;
652    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
653      return X86::ESI;
654    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
655      return X86::EDI;
656    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
657      return X86::EBP;
658    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
659      return X86::ESP;
660    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
661      return X86::R8D;
662    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
663      return X86::R9D;
664    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
665      return X86::R10D;
666    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
667      return X86::R11D;
668    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
669      return X86::R12D;
670    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
671      return X86::R13D;
672    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
673      return X86::R14D;
674    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
675      return X86::R15D;
676    }
677  case MVT::i64:
678    // For 64-bit mode if we've requested a "high" register and the
679    // Q or r constraints we want one of these high registers or
680    // just the register name otherwise.
681    if (High) {
682      switch (Reg) {
683      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
684        return X86::SI;
685      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
686        return X86::DI;
687      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
688        return X86::BP;
689      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
690        return X86::SP;
691      // Fallthrough.
692      }
693    }
694    switch (Reg) {
695    default: return Reg;
696    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
697      return X86::RAX;
698    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
699      return X86::RDX;
700    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
701      return X86::RCX;
702    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
703      return X86::RBX;
704    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
705      return X86::RSI;
706    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
707      return X86::RDI;
708    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
709      return X86::RBP;
710    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
711      return X86::RSP;
712    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
713      return X86::R8;
714    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
715      return X86::R9;
716    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
717      return X86::R10;
718    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
719      return X86::R11;
720    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
721      return X86::R12;
722    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
723      return X86::R13;
724    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
725      return X86::R14;
726    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
727      return X86::R15;
728    }
729  }
730}
731}
732
733namespace {
734  struct MSAH : public MachineFunctionPass {
735    static char ID;
736    MSAH() : MachineFunctionPass(ID) {}
737
738    virtual bool runOnMachineFunction(MachineFunction &MF) {
739      const X86TargetMachine *TM =
740        static_cast<const X86TargetMachine *>(&MF.getTarget());
741      const TargetFrameLowering *TFI = TM->getFrameLowering();
742      MachineRegisterInfo &RI = MF.getRegInfo();
743      X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
744      unsigned StackAlignment = TFI->getStackAlignment();
745
746      // Be over-conservative: scan over all vreg defs and find whether vector
747      // registers are used. If yes, there is a possibility that vector register
748      // will be spilled and thus require dynamic stack realignment.
749      for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
750        unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
751        if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
752          FuncInfo->setForceFramePointer(true);
753          return true;
754        }
755      }
756      // Nothing to do
757      return false;
758    }
759
760    virtual const char *getPassName() const {
761      return "X86 Maximal Stack Alignment Check";
762    }
763
764    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
765      AU.setPreservesCFG();
766      MachineFunctionPass::getAnalysisUsage(AU);
767    }
768  };
769
770  char MSAH::ID = 0;
771}
772
773FunctionPass*
774llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
775