X86RegisterInfo.cpp revision 66c6324fcf0db0f834e34dbb0e82a5038672eda3
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetRegisterInfo class. 11// This file is responsible for the frame pointer elimination optimization 12// on X86. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86RegisterInfo.h" 18#include "X86InstrBuilder.h" 19#include "X86MachineFunctionInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/Constants.h" 23#include "llvm/Function.h" 24#include "llvm/Type.h" 25#include "llvm/CodeGen/ValueTypes.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineLocation.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/Target/TargetAsmInfo.h" 34#include "llvm/Target/TargetFrameInfo.h" 35#include "llvm/Target/TargetInstrInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/BitVector.h" 39#include "llvm/ADT/STLExtras.h" 40#include "llvm/Support/Compiler.h" 41using namespace llvm; 42 43X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, 44 const TargetInstrInfo &tii) 45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ? 46 X86::ADJCALLSTACKDOWN64 : 47 X86::ADJCALLSTACKDOWN32, 48 tm.getSubtarget<X86Subtarget>().is64Bit() ? 49 X86::ADJCALLSTACKUP64 : 50 X86::ADJCALLSTACKUP32), 51 TM(tm), TII(tii) { 52 // Cache some information. 53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 54 Is64Bit = Subtarget->is64Bit(); 55 IsWin64 = Subtarget->isTargetWin64(); 56 StackAlign = TM.getFrameInfo()->getStackAlignment(); 57 if (Is64Bit) { 58 SlotSize = 8; 59 StackPtr = X86::RSP; 60 FramePtr = X86::RBP; 61 } else { 62 SlotSize = 4; 63 StackPtr = X86::ESP; 64 FramePtr = X86::EBP; 65 } 66} 67 68// getDwarfRegNum - This function maps LLVM register identifiers to the 69// Dwarf specific numbering, used in debug info and exception tables. 70 71int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { 72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 73 unsigned Flavour = DWARFFlavour::X86_64; 74 if (!Subtarget->is64Bit()) { 75 if (Subtarget->isTargetDarwin()) { 76 if (isEH) 77 Flavour = DWARFFlavour::X86_32_DarwinEH; 78 else 79 Flavour = DWARFFlavour::X86_32_Generic; 80 } else if (Subtarget->isTargetCygMing()) { 81 // Unsupported by now, just quick fallback 82 Flavour = DWARFFlavour::X86_32_Generic; 83 } else { 84 Flavour = DWARFFlavour::X86_32_Generic; 85 } 86 } 87 88 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour); 89} 90 91// getX86RegNum - This function maps LLVM register identifiers to their X86 92// specific numbering, which is used in various places encoding instructions. 93// 94unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { 95 switch(RegNo) { 96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; 97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; 98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; 99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; 100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: 101 return N86::ESP; 102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: 103 return N86::EBP; 104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: 105 return N86::ESI; 106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: 107 return N86::EDI; 108 109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 110 return N86::EAX; 111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 112 return N86::ECX; 113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 114 return N86::EDX; 115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 116 return N86::EBX; 117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 118 return N86::ESP; 119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 120 return N86::EBP; 121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 122 return N86::ESI; 123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 124 return N86::EDI; 125 126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3: 127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7: 128 return RegNo-X86::ST0; 129 130 case X86::XMM0: case X86::XMM8: case X86::MM0: 131 return 0; 132 case X86::XMM1: case X86::XMM9: case X86::MM1: 133 return 1; 134 case X86::XMM2: case X86::XMM10: case X86::MM2: 135 return 2; 136 case X86::XMM3: case X86::XMM11: case X86::MM3: 137 return 3; 138 case X86::XMM4: case X86::XMM12: case X86::MM4: 139 return 4; 140 case X86::XMM5: case X86::XMM13: case X86::MM5: 141 return 5; 142 case X86::XMM6: case X86::XMM14: case X86::MM6: 143 return 6; 144 case X86::XMM7: case X86::XMM15: case X86::MM7: 145 return 7; 146 147 default: 148 assert(isVirtualRegister(RegNo) && "Unknown physical register!"); 149 assert(0 && "Register allocator hasn't allocated reg correctly yet!"); 150 return 0; 151 } 152} 153 154const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const { 155 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 156 if (Subtarget->is64Bit()) 157 return &X86::GR64RegClass; 158 else 159 return &X86::GR32RegClass; 160} 161 162const TargetRegisterClass * 163X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 164 if (RC == &X86::CCRRegClass) { 165 if (Is64Bit) 166 return &X86::GR64RegClass; 167 else 168 return &X86::GR32RegClass; 169 } 170 return NULL; 171} 172 173const unsigned * 174X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 175 bool callsEHReturn = false; 176 177 if (MF) { 178 const MachineFrameInfo *MFI = MF->getFrameInfo(); 179 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 180 callsEHReturn = (MMI ? MMI->callsEHReturn() : false); 181 } 182 183 static const unsigned CalleeSavedRegs32Bit[] = { 184 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 185 }; 186 187 static const unsigned CalleeSavedRegs32EHRet[] = { 188 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 189 }; 190 191 static const unsigned CalleeSavedRegs64Bit[] = { 192 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 193 }; 194 195 static const unsigned CalleeSavedRegs64EHRet[] = { 196 X86::RAX, X86::RDX, X86::RBX, X86::R12, 197 X86::R13, X86::R14, X86::R15, X86::RBP, 0 198 }; 199 200 static const unsigned CalleeSavedRegsWin64[] = { 201 X86::RBX, X86::RBP, X86::RDI, X86::RSI, 202 X86::R12, X86::R13, X86::R14, X86::R15, 203 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, 204 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, 205 X86::XMM14, X86::XMM15, 0 206 }; 207 208 if (Is64Bit) { 209 if (IsWin64) 210 return CalleeSavedRegsWin64; 211 else 212 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit); 213 } else { 214 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit); 215 } 216} 217 218const TargetRegisterClass* const* 219X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 220 bool callsEHReturn = false; 221 222 if (MF) { 223 const MachineFrameInfo *MFI = MF->getFrameInfo(); 224 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 225 callsEHReturn = (MMI ? MMI->callsEHReturn() : false); 226 } 227 228 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = { 229 &X86::GR32RegClass, &X86::GR32RegClass, 230 &X86::GR32RegClass, &X86::GR32RegClass, 0 231 }; 232 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = { 233 &X86::GR32RegClass, &X86::GR32RegClass, 234 &X86::GR32RegClass, &X86::GR32RegClass, 235 &X86::GR32RegClass, &X86::GR32RegClass, 0 236 }; 237 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = { 238 &X86::GR64RegClass, &X86::GR64RegClass, 239 &X86::GR64RegClass, &X86::GR64RegClass, 240 &X86::GR64RegClass, &X86::GR64RegClass, 0 241 }; 242 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = { 243 &X86::GR64RegClass, &X86::GR64RegClass, 244 &X86::GR64RegClass, &X86::GR64RegClass, 245 &X86::GR64RegClass, &X86::GR64RegClass, 246 &X86::GR64RegClass, &X86::GR64RegClass, 0 247 }; 248 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = { 249 &X86::GR64RegClass, &X86::GR64RegClass, 250 &X86::GR64RegClass, &X86::GR64RegClass, 251 &X86::GR64RegClass, &X86::GR64RegClass, 252 &X86::GR64RegClass, &X86::GR64RegClass, 253 &X86::VR128RegClass, &X86::VR128RegClass, 254 &X86::VR128RegClass, &X86::VR128RegClass, 255 &X86::VR128RegClass, &X86::VR128RegClass, 256 &X86::VR128RegClass, &X86::VR128RegClass, 257 &X86::VR128RegClass, &X86::VR128RegClass, 0 258 }; 259 260 if (Is64Bit) { 261 if (IsWin64) 262 return CalleeSavedRegClassesWin64; 263 else 264 return (callsEHReturn ? 265 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit); 266 } else { 267 return (callsEHReturn ? 268 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit); 269 } 270} 271 272BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 273 BitVector Reserved(getNumRegs()); 274 // Set the stack-pointer register and its aliases as reserved. 275 Reserved.set(X86::RSP); 276 Reserved.set(X86::ESP); 277 Reserved.set(X86::SP); 278 Reserved.set(X86::SPL); 279 // Set the frame-pointer register and its aliases as reserved if needed. 280 if (hasFP(MF)) { 281 Reserved.set(X86::RBP); 282 Reserved.set(X86::EBP); 283 Reserved.set(X86::BP); 284 Reserved.set(X86::BPL); 285 } 286 // Mark the x87 stack registers as reserved, since they don't 287 // behave normally with respect to liveness. We don't fully 288 // model the effects of x87 stack pushes and pops after 289 // stackification. 290 Reserved.set(X86::ST0); 291 Reserved.set(X86::ST1); 292 Reserved.set(X86::ST2); 293 Reserved.set(X86::ST3); 294 Reserved.set(X86::ST4); 295 Reserved.set(X86::ST5); 296 Reserved.set(X86::ST6); 297 Reserved.set(X86::ST7); 298 return Reserved; 299} 300 301//===----------------------------------------------------------------------===// 302// Stack Frame Processing methods 303//===----------------------------------------------------------------------===// 304 305static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) { 306 unsigned MaxAlign = 0; 307 for (int i = FFI->getObjectIndexBegin(), 308 e = FFI->getObjectIndexEnd(); i != e; ++i) { 309 if (FFI->isDeadObjectIndex(i)) 310 continue; 311 unsigned Align = FFI->getObjectAlignment(i); 312 MaxAlign = std::max(MaxAlign, Align); 313 } 314 315 return MaxAlign; 316} 317 318// hasFP - Return true if the specified function should have a dedicated frame 319// pointer register. This is true if the function has variable sized allocas or 320// if frame pointer elimination is disabled. 321// 322bool X86RegisterInfo::hasFP(const MachineFunction &MF) const { 323 const MachineFrameInfo *MFI = MF.getFrameInfo(); 324 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 325 326 return (NoFramePointerElim || 327 needsStackRealignment(MF) || 328 MFI->hasVarSizedObjects() || 329 MFI->isFrameAddressTaken() || 330 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() || 331 (MMI && MMI->callsUnwindInit())); 332} 333 334bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 335 const MachineFrameInfo *MFI = MF.getFrameInfo(); 336 337 // FIXME: Currently we don't support stack realignment for functions with 338 // variable-sized allocas 339 return (RealignStack && 340 (MFI->getMaxAlignment() > StackAlign && 341 !MFI->hasVarSizedObjects())); 342} 343 344bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { 345 return !MF.getFrameInfo()->hasVarSizedObjects(); 346} 347 348int 349X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { 350 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize; 351 uint64_t StackSize = MF.getFrameInfo()->getStackSize(); 352 353 if (needsStackRealignment(MF)) { 354 if (FI < 0) 355 // Skip the saved EBP 356 Offset += SlotSize; 357 else { 358 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI); 359 assert( (-(Offset + StackSize)) % Align == 0); 360 Align = 0; 361 return Offset + StackSize; 362 } 363 364 // FIXME: Support tail calls 365 } else { 366 if (!hasFP(MF)) 367 return Offset + StackSize; 368 369 // Skip the saved EBP 370 Offset += SlotSize; 371 372 // Skip the RETADDR move area 373 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 374 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 375 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta; 376 } 377 378 return Offset; 379} 380 381void X86RegisterInfo:: 382eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 383 MachineBasicBlock::iterator I) const { 384 if (!hasReservedCallFrame(MF)) { 385 // If the stack pointer can be changed after prologue, turn the 386 // adjcallstackup instruction into a 'sub ESP, <amt>' and the 387 // adjcallstackdown instruction into 'add ESP, <amt>' 388 // TODO: consider using push / pop instead of sub + store / add 389 MachineInstr *Old = I; 390 uint64_t Amount = Old->getOperand(0).getImm(); 391 if (Amount != 0) { 392 // We need to keep the stack aligned properly. To do this, we round the 393 // amount of space needed for the outgoing arguments up to the next 394 // alignment boundary. 395 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; 396 397 MachineInstr *New = 0; 398 if (Old->getOpcode() == getCallFrameSetupOpcode()) { 399 New = BuildMI(MF, Old->getDebugLoc(), 400 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), 401 StackPtr).addReg(StackPtr).addImm(Amount); 402 } else { 403 assert(Old->getOpcode() == getCallFrameDestroyOpcode()); 404 // factor out the amount the callee already popped. 405 uint64_t CalleeAmt = Old->getOperand(1).getImm(); 406 Amount -= CalleeAmt; 407 if (Amount) { 408 unsigned Opc = (Amount < 128) ? 409 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : 410 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); 411 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr) 412 .addReg(StackPtr).addImm(Amount); 413 } 414 } 415 416 if (New) { 417 // The EFLAGS implicit def is dead. 418 New->getOperand(3).setIsDead(); 419 420 // Replace the pseudo instruction with a new instruction... 421 MBB.insert(I, New); 422 } 423 } 424 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) { 425 // If we are performing frame pointer elimination and if the callee pops 426 // something off the stack pointer, add it back. We do this until we have 427 // more advanced stack pointer tracking ability. 428 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) { 429 unsigned Opc = (CalleeAmt < 128) ? 430 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : 431 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); 432 MachineInstr *Old = I; 433 MachineInstr *New = 434 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), 435 StackPtr).addReg(StackPtr).addImm(CalleeAmt); 436 // The EFLAGS implicit def is dead. 437 New->getOperand(3).setIsDead(); 438 439 MBB.insert(I, New); 440 } 441 } 442 443 MBB.erase(I); 444} 445 446void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 447 int SPAdj, RegScavenger *RS) const{ 448 assert(SPAdj == 0 && "Unexpected"); 449 450 unsigned i = 0; 451 MachineInstr &MI = *II; 452 MachineFunction &MF = *MI.getParent()->getParent(); 453 while (!MI.getOperand(i).isFI()) { 454 ++i; 455 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 456 } 457 458 int FrameIndex = MI.getOperand(i).getIndex(); 459 460 unsigned BasePtr; 461 if (needsStackRealignment(MF)) 462 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); 463 else 464 BasePtr = (hasFP(MF) ? FramePtr : StackPtr); 465 466 // This must be part of a four operand memory reference. Replace the 467 // FrameIndex with base register with EBP. Add an offset to the offset. 468 MI.getOperand(i).ChangeToRegister(BasePtr, false); 469 470 // Now add the frame object offset to the offset from EBP. 471 if (MI.getOperand(i+3).isImm()) { 472 // Offset is a 32-bit integer. 473 int Offset = getFrameIndexOffset(MF, FrameIndex) + 474 (int)(MI.getOperand(i+3).getImm()); 475 476 MI.getOperand(i+3).ChangeToImmediate(Offset); 477 } else { 478 // Offset is symbolic. This is extremely rare. 479 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) + 480 (uint64_t)MI.getOperand(i+3).getOffset(); 481 MI.getOperand(i+3).setOffset(Offset); 482 } 483} 484 485void 486X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 487 RegScavenger *RS) const { 488 MachineFrameInfo *FFI = MF.getFrameInfo(); 489 490 // Calculate and set max stack object alignment early, so we can decide 491 // whether we will need stack realignment (and thus FP). 492 unsigned MaxAlign = std::max(FFI->getMaxAlignment(), 493 calculateMaxStackAlignment(FFI)); 494 495 FFI->setMaxAlignment(MaxAlign); 496} 497 498void 499X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{ 500 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 501 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 502 if (TailCallReturnAddrDelta < 0) { 503 // create RETURNADDR area 504 // arg 505 // arg 506 // RETADDR 507 // { ... 508 // RETADDR area 509 // ... 510 // } 511 // [EBP] 512 MF.getFrameInfo()-> 513 CreateFixedObject(-TailCallReturnAddrDelta, 514 (-1*SlotSize)+TailCallReturnAddrDelta); 515 } 516 if (hasFP(MF)) { 517 assert((TailCallReturnAddrDelta <= 0) && 518 "The Delta should always be zero or negative"); 519 // Create a frame entry for the EBP register that must be saved. 520 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, 521 (int)SlotSize * -2+ 522 TailCallReturnAddrDelta); 523 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && 524 "Slot for EBP register must be last in order to be found!"); 525 FrameIdx = 0; 526 } 527} 528 529/// emitSPUpdate - Emit a series of instructions to increment / decrement the 530/// stack pointer by a constant value. 531static 532void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 533 unsigned StackPtr, int64_t NumBytes, bool Is64Bit, 534 const TargetInstrInfo &TII) { 535 bool isSub = NumBytes < 0; 536 uint64_t Offset = isSub ? -NumBytes : NumBytes; 537 unsigned Opc = isSub 538 ? ((Offset < 128) ? 539 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : 540 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri)) 541 : ((Offset < 128) ? 542 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : 543 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri)); 544 uint64_t Chunk = (1LL << 31) - 1; 545 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() : 546 DebugLoc::getUnknownLoc()); 547 548 while (Offset) { 549 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; 550 MachineInstr *MI = 551 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 552 .addReg(StackPtr).addImm(ThisVal); 553 // The EFLAGS implicit def is dead. 554 MI->getOperand(3).setIsDead(); 555 Offset -= ThisVal; 556 } 557} 558 559// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator. 560static 561void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 562 unsigned StackPtr, uint64_t *NumBytes = NULL) { 563 if (MBBI == MBB.begin()) return; 564 565 MachineBasicBlock::iterator PI = prior(MBBI); 566 unsigned Opc = PI->getOpcode(); 567 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 568 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 569 PI->getOperand(0).getReg() == StackPtr) { 570 if (NumBytes) 571 *NumBytes += PI->getOperand(2).getImm(); 572 MBB.erase(PI); 573 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 574 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 575 PI->getOperand(0).getReg() == StackPtr) { 576 if (NumBytes) 577 *NumBytes -= PI->getOperand(2).getImm(); 578 MBB.erase(PI); 579 } 580} 581 582// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator. 583static 584void mergeSPUpdatesDown(MachineBasicBlock &MBB, 585 MachineBasicBlock::iterator &MBBI, 586 unsigned StackPtr, uint64_t *NumBytes = NULL) { 587 return; 588 589 if (MBBI == MBB.end()) return; 590 591 MachineBasicBlock::iterator NI = next(MBBI); 592 if (NI == MBB.end()) return; 593 594 unsigned Opc = NI->getOpcode(); 595 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 596 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 597 NI->getOperand(0).getReg() == StackPtr) { 598 if (NumBytes) 599 *NumBytes -= NI->getOperand(2).getImm(); 600 MBB.erase(NI); 601 MBBI = NI; 602 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 603 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 604 NI->getOperand(0).getReg() == StackPtr) { 605 if (NumBytes) 606 *NumBytes += NI->getOperand(2).getImm(); 607 MBB.erase(NI); 608 MBBI = NI; 609 } 610} 611 612/// mergeSPUpdates - Checks the instruction before/after the passed 613/// instruction. If it is an ADD/SUB instruction it is deleted 614/// argument and the stack adjustment is returned as a positive value for ADD 615/// and a negative for SUB. 616static int mergeSPUpdates(MachineBasicBlock &MBB, 617 MachineBasicBlock::iterator &MBBI, 618 unsigned StackPtr, 619 bool doMergeWithPrevious) { 620 621 if ((doMergeWithPrevious && MBBI == MBB.begin()) || 622 (!doMergeWithPrevious && MBBI == MBB.end())) 623 return 0; 624 625 int Offset = 0; 626 627 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI; 628 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI); 629 unsigned Opc = PI->getOpcode(); 630 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 631 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 632 PI->getOperand(0).getReg() == StackPtr){ 633 Offset += PI->getOperand(2).getImm(); 634 MBB.erase(PI); 635 if (!doMergeWithPrevious) MBBI = NI; 636 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 637 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 638 PI->getOperand(0).getReg() == StackPtr) { 639 Offset -= PI->getOperand(2).getImm(); 640 MBB.erase(PI); 641 if (!doMergeWithPrevious) MBBI = NI; 642 } 643 644 return Offset; 645} 646 647void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF, 648 unsigned LabelId) const { 649 MachineFrameInfo *MFI = MF.getFrameInfo(); 650 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 651 if (!MMI) return; 652 653 // Add callee saved registers to move list. 654 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 655 if (CSI.empty()) return; 656 657 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 658 const TargetData *TD = MF.getTarget().getTargetData(); 659 660 // Calculate amount of bytes used for return address storing 661 int stackGrowth = 662 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() == 663 TargetFrameInfo::StackGrowsUp ? 664 TD->getPointerSize() : -TD->getPointerSize()); 665 666 // FIXME: This is dirty hack. The code itself is pretty mess right now. 667 // It should be rewritten from scratch and generalized sometimes. 668 669 // Determine maximum offset (minumum due to stack growth) 670 int64_t MaxOffset = 0; 671 for (std::vector<CalleeSavedInfo>::const_iterator 672 I = CSI.begin(), E = CSI.end(); I != E; ++I) 673 MaxOffset = std::min(MaxOffset, 674 MFI->getObjectOffset(I->getFrameIdx())); 675 676 // Calculate offsets. 677 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2) * stackGrowth; 678 for (std::vector<CalleeSavedInfo>::const_iterator 679 I = CSI.begin(), E = CSI.end(); I != E; ++I) { 680 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 681 unsigned Reg = I->getReg(); 682 Offset = MaxOffset - Offset + saveAreaOffset; 683 684 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 685 MachineLocation CSSrc(Reg); 686 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc)); 687 } 688} 689 690void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { 691 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 692 MachineFrameInfo *MFI = MF.getFrameInfo(); 693 const Function* Fn = MF.getFunction(); 694 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>(); 695 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 696 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 697 MachineBasicBlock::iterator MBBI = MBB.begin(); 698 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || 699 !Fn->doesNotThrow() || 700 UnwindTablesMandatory; 701 bool HasFP = hasFP(MF); 702 DebugLoc DL; 703 704 // Get the number of bytes to allocate from the FrameInfo. 705 uint64_t StackSize = MFI->getStackSize(); 706 707 // Get desired stack alignment 708 uint64_t MaxAlign = MFI->getMaxAlignment(); 709 710 // Add RETADDR move area to callee saved frame size. 711 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 712 if (TailCallReturnAddrDelta < 0) 713 X86FI->setCalleeSavedFrameSize( 714 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta)); 715 716 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf 717 // function, and use up to 128 bytes of stack space, don't have a frame 718 // pointer, calls, or dynamic alloca then we do not need to adjust the 719 // stack pointer (we fit in the Red Zone). 720 bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone); 721 if (Is64Bit && !DisableRedZone && 722 !needsStackRealignment(MF) && 723 !MFI->hasVarSizedObjects() && // No dynamic alloca. 724 !MFI->hasCalls() && // No calls. 725 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone 726 uint64_t MinSize = X86FI->getCalleeSavedFrameSize(); 727 if (HasFP) MinSize += SlotSize; 728 StackSize = std::max(MinSize, 729 StackSize > 128 ? StackSize - 128 : 0); 730 MFI->setStackSize(StackSize); 731 } 732 733 // Insert stack pointer adjustment for later moving of return addr. Only 734 // applies to tail call optimized functions where the callee argument stack 735 // size is bigger than the callers. 736 if (TailCallReturnAddrDelta < 0) { 737 MachineInstr *MI = 738 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri), 739 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta); 740 // The EFLAGS implicit def is dead. 741 MI->getOperand(3).setIsDead(); 742 } 743 744 // uint64_t StackSize = MFI->getStackSize(); 745 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 746 const TargetData *TD = MF.getTarget().getTargetData(); 747 int stackGrowth = 748 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() == 749 TargetFrameInfo::StackGrowsUp ? 750 TD->getPointerSize() : -TD->getPointerSize()); 751 752 uint64_t NumBytes = 0; 753 if (HasFP) { 754 // Calculate required stack adjustment 755 uint64_t FrameSize = StackSize - SlotSize; 756 if (needsStackRealignment(MF)) 757 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign; 758 759 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize(); 760 761 // Get the offset of the stack slot for the EBP register, which is 762 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 763 // Update the frame offset adjustment. 764 MFI->setOffsetAdjustment(-NumBytes); 765 766 // Save EBP/RBP into the appropriate stack slot... 767 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) 768 .addReg(FramePtr, RegState::Kill); 769 770 if (needsFrameMoves) { 771 // Mark effective beginning of when frame pointer becomes valid. 772 unsigned FrameLabelId = MMI->NextLabelID(); 773 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); 774 775 // Define the current CFA rule to use the provided offset. 776 if (StackSize) { 777 MachineLocation SPDst(MachineLocation::VirtualFP); 778 MachineLocation SPSrc(MachineLocation::VirtualFP, 779 HasFP ? 2 * stackGrowth : 780 -StackSize + stackGrowth); 781 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 782 } else { 783 // FIXME: Verify & implement for FP 784 MachineLocation SPDst(StackPtr); 785 MachineLocation SPSrc(StackPtr, stackGrowth); 786 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 787 } 788 789 // Change the rule for the FramePtr to be an "offset" rule. 790 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth); 791 MachineLocation FPSrc(FramePtr); 792 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 793 } 794 795 // Update EBP with the new base value... 796 BuildMI(MBB, MBBI, DL, 797 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) 798 .addReg(StackPtr); 799 800 if (needsFrameMoves) { 801 unsigned FrameLabelId = MMI->NextLabelID(); 802 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); 803 804 // Define the current CFA to use the EBP/RBP register. 805 MachineLocation FPDst(FramePtr); 806 MachineLocation FPSrc(MachineLocation::VirtualFP); 807 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 808 } 809 810 // Mark the FramePtr as live-in in every block except the entry. 811 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end(); 812 I != E; ++I) 813 I->addLiveIn(FramePtr); 814 815 // Realign stack 816 if (needsStackRealignment(MF)) { 817 MachineInstr *MI = 818 BuildMI(MBB, MBBI, DL, 819 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), 820 StackPtr).addReg(StackPtr).addImm(-MaxAlign); 821 // The EFLAGS implicit def is dead. 822 MI->getOperand(3).setIsDead(); 823 } 824 } else { 825 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); 826 } 827 828 // Skip the callee-saved push instructions. 829 bool RegsSaved = false; 830 while (MBBI != MBB.end() && 831 (MBBI->getOpcode() == X86::PUSH32r || 832 MBBI->getOpcode() == X86::PUSH64r)) { 833 RegsSaved = true; 834 ++MBBI; 835 } 836 837 if (RegsSaved && needsFrameMoves) { 838 // Mark end of callee-saved push instructions. 839 unsigned LabelId = MMI->NextLabelID(); 840 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId); 841 842 // Emit DWARF info specifying the offsets of the callee-saved registers. 843 emitCalleeSavedFrameMoves(MF, LabelId); 844 } 845 846 if (MBBI != MBB.end()) 847 DL = MBBI->getDebugLoc(); 848 849 // Adjust stack pointer: ESP -= numbytes. 850 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) { 851 // Check, whether EAX is livein for this function. 852 bool isEAXAlive = false; 853 for (MachineRegisterInfo::livein_iterator 854 II = MF.getRegInfo().livein_begin(), 855 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) { 856 unsigned Reg = II->first; 857 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX || 858 Reg == X86::AH || Reg == X86::AL); 859 } 860 861 // Function prologue calls _alloca to probe the stack when allocating more 862 // than 4k bytes in one go. Touching the stack at 4K increments is necessary 863 // to ensure that the guard pages used by the OS virtual memory manager are 864 // allocated in correct sequence. 865 if (!isEAXAlive) { 866 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) 867 .addImm(NumBytes); 868 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) 869 .addExternalSymbol("_alloca"); 870 } else { 871 // Save EAX 872 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) 873 .addReg(X86::EAX, RegState::Kill); 874 875 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already 876 // allocated bytes for EAX. 877 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) 878 .addImm(NumBytes - 4); 879 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) 880 .addExternalSymbol("_alloca"); 881 882 // Restore EAX 883 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), 884 X86::EAX), 885 StackPtr, false, NumBytes - 4); 886 MBB.insert(MBBI, MI); 887 } 888 } else if (NumBytes) { 889 // If there is an SUB32ri of ESP immediately before this instruction, merge 890 // the two. This can be the case when tail call elimination is enabled and 891 // the callee has more arguments then the caller. 892 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true); 893 894 // If there is an ADD32ri or SUB32ri of ESP immediately after this 895 // instruction, merge the two instructions. 896 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes); 897 898 if (NumBytes) 899 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII); 900 } 901} 902 903void X86RegisterInfo::emitEpilogue(MachineFunction &MF, 904 MachineBasicBlock &MBB) const { 905 const MachineFrameInfo *MFI = MF.getFrameInfo(); 906 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 907 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 908 unsigned RetOpcode = MBBI->getOpcode(); 909 DebugLoc DL = MBBI->getDebugLoc(); 910 911 switch (RetOpcode) { 912 case X86::RET: 913 case X86::RETI: 914 case X86::TCRETURNdi: 915 case X86::TCRETURNri: 916 case X86::TCRETURNri64: 917 case X86::TCRETURNdi64: 918 case X86::EH_RETURN: 919 case X86::EH_RETURN64: 920 case X86::TAILJMPd: 921 case X86::TAILJMPr: 922 case X86::TAILJMPm: break; // These are ok 923 default: 924 assert(0 && "Can only insert epilog into returning blocks"); 925 } 926 927 // Get the number of bytes to allocate from the FrameInfo 928 uint64_t StackSize = MFI->getStackSize(); 929 uint64_t MaxAlign = MFI->getMaxAlignment(); 930 unsigned CSSize = X86FI->getCalleeSavedFrameSize(); 931 uint64_t NumBytes = 0; 932 933 if (hasFP(MF)) { 934 // Calculate required stack adjustment 935 uint64_t FrameSize = StackSize - SlotSize; 936 if (needsStackRealignment(MF)) 937 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign; 938 939 NumBytes = FrameSize - CSSize; 940 941 // pop EBP. 942 BuildMI(MBB, MBBI, DL, 943 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); 944 } else { 945 NumBytes = StackSize - CSSize; 946 } 947 948 // Skip the callee-saved pop instructions. 949 MachineBasicBlock::iterator LastCSPop = MBBI; 950 while (MBBI != MBB.begin()) { 951 MachineBasicBlock::iterator PI = prior(MBBI); 952 unsigned Opc = PI->getOpcode(); 953 if (Opc != X86::POP32r && Opc != X86::POP64r && 954 !PI->getDesc().isTerminator()) 955 break; 956 --MBBI; 957 } 958 959 DL = MBBI->getDebugLoc(); 960 961 // If there is an ADD32ri or SUB32ri of ESP immediately before this 962 // instruction, merge the two instructions. 963 if (NumBytes || MFI->hasVarSizedObjects()) 964 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); 965 966 // If dynamic alloca is used, then reset esp to point to the last callee-saved 967 // slot before popping them off! Same applies for the case, when stack was 968 // realigned 969 if (needsStackRealignment(MF)) { 970 // We cannot use LEA here, because stack pointer was realigned. We need to 971 // deallocate local frame back 972 if (CSSize) { 973 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII); 974 MBBI = prior(LastCSPop); 975 } 976 977 BuildMI(MBB, MBBI, DL, 978 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), 979 StackPtr).addReg(FramePtr); 980 } else if (MFI->hasVarSizedObjects()) { 981 if (CSSize) { 982 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; 983 MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr), 984 FramePtr, false, -CSSize); 985 MBB.insert(MBBI, MI); 986 } else 987 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), 988 StackPtr).addReg(FramePtr); 989 990 } else { 991 // adjust stack pointer back: ESP += numbytes 992 if (NumBytes) 993 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII); 994 } 995 996 // We're returning from function via eh_return. 997 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { 998 MBBI = prior(MBB.end()); 999 MachineOperand &DestAddr = MBBI->getOperand(0); 1000 assert(DestAddr.isReg() && "Offset should be in register!"); 1001 BuildMI(MBB, MBBI, DL, 1002 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), 1003 StackPtr).addReg(DestAddr.getReg()); 1004 // Tail call return: adjust the stack pointer and jump to callee 1005 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || 1006 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) { 1007 MBBI = prior(MBB.end()); 1008 MachineOperand &JumpTarget = MBBI->getOperand(0); 1009 MachineOperand &StackAdjust = MBBI->getOperand(1); 1010 assert(StackAdjust.isImm() && "Expecting immediate value."); 1011 1012 // Adjust stack pointer. 1013 int StackAdj = StackAdjust.getImm(); 1014 int MaxTCDelta = X86FI->getTCReturnAddrDelta(); 1015 int Offset = 0; 1016 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive"); 1017 // Incoporate the retaddr area. 1018 Offset = StackAdj-MaxTCDelta; 1019 assert(Offset >= 0 && "Offset should never be negative"); 1020 1021 if (Offset) { 1022 // Check for possible merge with preceeding ADD instruction. 1023 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true); 1024 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII); 1025 } 1026 1027 // Jump to label or value in register. 1028 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64) 1029 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)). 1030 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1031 else if (RetOpcode== X86::TCRETURNri64) 1032 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); 1033 else 1034 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg()); 1035 1036 // Delete the pseudo instruction TCRETURN. 1037 MBB.erase(MBBI); 1038 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && 1039 (X86FI->getTCReturnAddrDelta() < 0)) { 1040 // Add the return addr area delta back since we are not tail calling. 1041 int delta = -1*X86FI->getTCReturnAddrDelta(); 1042 MBBI = prior(MBB.end()); 1043 // Check for possible merge with preceeding ADD instruction. 1044 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true); 1045 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII); 1046 } 1047} 1048 1049unsigned X86RegisterInfo::getRARegister() const { 1050 if (Is64Bit) 1051 return X86::RIP; // Should have dwarf #16 1052 else 1053 return X86::EIP; // Should have dwarf #8 1054} 1055 1056unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const { 1057 return hasFP(MF) ? FramePtr : StackPtr; 1058} 1059 1060void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1061 const { 1062 // Calculate amount of bytes used for return address storing 1063 int stackGrowth = (Is64Bit ? -8 : -4); 1064 1065 // Initial state of the frame pointer is esp+4. 1066 MachineLocation Dst(MachineLocation::VirtualFP); 1067 MachineLocation Src(StackPtr, stackGrowth); 1068 Moves.push_back(MachineMove(0, Dst, Src)); 1069 1070 // Add return address to move list 1071 MachineLocation CSDst(StackPtr, stackGrowth); 1072 MachineLocation CSSrc(getRARegister()); 1073 Moves.push_back(MachineMove(0, CSDst, CSSrc)); 1074} 1075 1076unsigned X86RegisterInfo::getEHExceptionRegister() const { 1077 assert(0 && "What is the exception register"); 1078 return 0; 1079} 1080 1081unsigned X86RegisterInfo::getEHHandlerRegister() const { 1082 assert(0 && "What is the exception handler register"); 1083 return 0; 1084} 1085 1086namespace llvm { 1087unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) { 1088 switch (VT.getSimpleVT()) { 1089 default: return Reg; 1090 case MVT::i8: 1091 if (High) { 1092 switch (Reg) { 1093 default: return 0; 1094 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1095 return X86::AH; 1096 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1097 return X86::DH; 1098 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1099 return X86::CH; 1100 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1101 return X86::BH; 1102 } 1103 } else { 1104 switch (Reg) { 1105 default: return 0; 1106 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1107 return X86::AL; 1108 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1109 return X86::DL; 1110 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1111 return X86::CL; 1112 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1113 return X86::BL; 1114 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 1115 return X86::SIL; 1116 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 1117 return X86::DIL; 1118 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 1119 return X86::BPL; 1120 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 1121 return X86::SPL; 1122 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 1123 return X86::R8B; 1124 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 1125 return X86::R9B; 1126 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 1127 return X86::R10B; 1128 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 1129 return X86::R11B; 1130 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 1131 return X86::R12B; 1132 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 1133 return X86::R13B; 1134 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 1135 return X86::R14B; 1136 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 1137 return X86::R15B; 1138 } 1139 } 1140 case MVT::i16: 1141 switch (Reg) { 1142 default: return Reg; 1143 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1144 return X86::AX; 1145 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1146 return X86::DX; 1147 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1148 return X86::CX; 1149 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1150 return X86::BX; 1151 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 1152 return X86::SI; 1153 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 1154 return X86::DI; 1155 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 1156 return X86::BP; 1157 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 1158 return X86::SP; 1159 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 1160 return X86::R8W; 1161 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 1162 return X86::R9W; 1163 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 1164 return X86::R10W; 1165 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 1166 return X86::R11W; 1167 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 1168 return X86::R12W; 1169 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 1170 return X86::R13W; 1171 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 1172 return X86::R14W; 1173 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 1174 return X86::R15W; 1175 } 1176 case MVT::i32: 1177 switch (Reg) { 1178 default: return Reg; 1179 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1180 return X86::EAX; 1181 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1182 return X86::EDX; 1183 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1184 return X86::ECX; 1185 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1186 return X86::EBX; 1187 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 1188 return X86::ESI; 1189 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 1190 return X86::EDI; 1191 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 1192 return X86::EBP; 1193 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 1194 return X86::ESP; 1195 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 1196 return X86::R8D; 1197 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 1198 return X86::R9D; 1199 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 1200 return X86::R10D; 1201 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 1202 return X86::R11D; 1203 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 1204 return X86::R12D; 1205 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 1206 return X86::R13D; 1207 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 1208 return X86::R14D; 1209 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 1210 return X86::R15D; 1211 } 1212 case MVT::i64: 1213 switch (Reg) { 1214 default: return Reg; 1215 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1216 return X86::RAX; 1217 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1218 return X86::RDX; 1219 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1220 return X86::RCX; 1221 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1222 return X86::RBX; 1223 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 1224 return X86::RSI; 1225 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 1226 return X86::RDI; 1227 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 1228 return X86::RBP; 1229 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 1230 return X86::RSP; 1231 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 1232 return X86::R8; 1233 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 1234 return X86::R9; 1235 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 1236 return X86::R10; 1237 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 1238 return X86::R11; 1239 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 1240 return X86::R12; 1241 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 1242 return X86::R13; 1243 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 1244 return X86::R14; 1245 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 1246 return X86::R15; 1247 } 1248 } 1249 1250 return Reg; 1251} 1252} 1253 1254#include "X86GenRegisterInfo.inc" 1255 1256namespace { 1257 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass { 1258 static char ID; 1259 MSAC() : MachineFunctionPass(&ID) {} 1260 1261 virtual bool runOnMachineFunction(MachineFunction &MF) { 1262 MachineFrameInfo *FFI = MF.getFrameInfo(); 1263 MachineRegisterInfo &RI = MF.getRegInfo(); 1264 1265 // Calculate max stack alignment of all already allocated stack objects. 1266 unsigned MaxAlign = calculateMaxStackAlignment(FFI); 1267 1268 // Be over-conservative: scan over all vreg defs and find, whether vector 1269 // registers are used. If yes - there is probability, that vector register 1270 // will be spilled and thus stack needs to be aligned properly. 1271 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister; 1272 RegNum < RI.getLastVirtReg(); ++RegNum) 1273 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment()); 1274 1275 FFI->setMaxAlignment(MaxAlign); 1276 1277 return false; 1278 } 1279 1280 virtual const char *getPassName() const { 1281 return "X86 Maximal Stack Alignment Calculator"; 1282 } 1283 }; 1284 1285 char MSAC::ID = 0; 1286} 1287 1288FunctionPass* 1289llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); } 1290