X86RegisterInfo.cpp revision 7f70559bc47877bafc6dfa92b7df6b64650445fb 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the MRegisterInfo class.  This
11// file is responsible for the frame pointer elimination optimization on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86RegisterInfo.h"
17#include "X86InstrBuilder.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/Type.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineLocation.h"
29#include "llvm/Target/TargetFrameInfo.h"
30#include "llvm/Target/TargetInstrInfo.h"
31#include "llvm/Target/TargetMachine.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/ADT/STLExtras.h"
35using namespace llvm;
36
37namespace {
38  cl::opt<bool>
39  NoFusing("disable-spill-fusing",
40           cl::desc("Disable fusing of spill code into instructions"));
41  cl::opt<bool>
42  PrintFailedFusing("print-failed-fuse-candidates",
43                    cl::desc("Print instructions that the allocator wants to"
44                             " fuse, but the X86 backend currently can't"),
45                    cl::Hidden);
46}
47
48X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
49                                 const TargetInstrInfo &tii)
50  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
51    TM(tm), TII(tii) {
52  // Cache some information.
53  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54  Is64Bit = Subtarget->is64Bit();
55  if (Is64Bit) {
56    SlotSize = 8;
57    StackPtr = X86::RSP;
58    FramePtr = X86::RBP;
59  } else {
60    SlotSize = 4;
61    StackPtr = X86::ESP;
62    FramePtr = X86::EBP;
63  }
64}
65
66void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
67                                          MachineBasicBlock::iterator MI,
68                                          unsigned SrcReg, int FrameIdx,
69                                          const TargetRegisterClass *RC) const {
70  unsigned Opc;
71  if (RC == &X86::GR64RegClass) {
72    Opc = X86::MOV64mr;
73  } else if (RC == &X86::GR32RegClass) {
74    Opc = X86::MOV32mr;
75  } else if (RC == &X86::GR16RegClass) {
76    Opc = X86::MOV16mr;
77  } else if (RC == &X86::GR8RegClass) {
78    Opc = X86::MOV8mr;
79  } else if (RC == &X86::GR32_RegClass) {
80    Opc = X86::MOV32_mr;
81  } else if (RC == &X86::GR16_RegClass) {
82    Opc = X86::MOV16_mr;
83  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
84    Opc = X86::FpST64m;
85  } else if (RC == &X86::FR32RegClass) {
86    Opc = X86::MOVSSmr;
87  } else if (RC == &X86::FR64RegClass) {
88    Opc = X86::MOVSDmr;
89  } else if (RC == &X86::VR128RegClass) {
90    Opc = X86::MOVAPSmr;
91  } else {
92    assert(0 && "Unknown regclass");
93    abort();
94  }
95  addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
96}
97
98void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
99                                           MachineBasicBlock::iterator MI,
100                                           unsigned DestReg, int FrameIdx,
101                                           const TargetRegisterClass *RC) const{
102  unsigned Opc;
103  if (RC == &X86::GR64RegClass) {
104    Opc = X86::MOV64rm;
105  } else if (RC == &X86::GR32RegClass) {
106    Opc = X86::MOV32rm;
107  } else if (RC == &X86::GR16RegClass) {
108    Opc = X86::MOV16rm;
109  } else if (RC == &X86::GR8RegClass) {
110    Opc = X86::MOV8rm;
111  } else if (RC == &X86::GR32_RegClass) {
112    Opc = X86::MOV32_rm;
113  } else if (RC == &X86::GR16_RegClass) {
114    Opc = X86::MOV16_rm;
115  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
116    Opc = X86::FpLD64m;
117  } else if (RC == &X86::FR32RegClass) {
118    Opc = X86::MOVSSrm;
119  } else if (RC == &X86::FR64RegClass) {
120    Opc = X86::MOVSDrm;
121  } else if (RC == &X86::VR128RegClass) {
122    Opc = X86::MOVAPSrm;
123  } else {
124    assert(0 && "Unknown regclass");
125    abort();
126  }
127  addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
128}
129
130void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
131                                   MachineBasicBlock::iterator MI,
132                                   unsigned DestReg, unsigned SrcReg,
133                                   const TargetRegisterClass *RC) const {
134  unsigned Opc;
135  if (RC == &X86::GR64RegClass) {
136    Opc = X86::MOV64rr;
137  } else if (RC == &X86::GR32RegClass) {
138    Opc = X86::MOV32rr;
139  } else if (RC == &X86::GR16RegClass) {
140    Opc = X86::MOV16rr;
141  } else if (RC == &X86::GR8RegClass) {
142    Opc = X86::MOV8rr;
143  } else if (RC == &X86::GR32_RegClass) {
144    Opc = X86::MOV32_rr;
145  } else if (RC == &X86::GR16_RegClass) {
146    Opc = X86::MOV16_rr;
147  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
148    Opc = X86::FpMOV;
149  } else if (RC == &X86::FR32RegClass) {
150    Opc = X86::FsMOVAPSrr;
151  } else if (RC == &X86::FR64RegClass) {
152    Opc = X86::FsMOVAPDrr;
153  } else if (RC == &X86::VR128RegClass) {
154    Opc = X86::MOVAPSrr;
155  } else {
156    assert(0 && "Unknown regclass");
157    abort();
158  }
159  BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
160}
161
162static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
163                                     MachineInstr *MI,
164                                     const TargetInstrInfo &TII) {
165  unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
166  // Create the base instruction with the memory operand as the first part.
167  MachineInstrBuilder MIB = addFrameReference(BuildMI(TII.get(Opcode)),
168                                              FrameIndex);
169
170  // Loop over the rest of the ri operands, converting them over.
171  for (unsigned i = 0; i != NumOps; ++i) {
172    MachineOperand &MO = MI->getOperand(i+2);
173    if (MO.isReg())
174      MIB = MIB.addReg(MO.getReg(), false, MO.isImplicit());
175    else if (MO.isImm())
176      MIB = MIB.addImm(MO.getImm());
177    else if (MO.isGlobalAddress())
178      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
179    else if (MO.isJumpTableIndex())
180      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
181    else if (MO.isExternalSymbol())
182      MIB = MIB.addExternalSymbol(MO.getSymbolName());
183    else
184      assert(0 && "Unknown operand type!");
185  }
186  return MIB;
187}
188
189static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
190                              unsigned FrameIndex, MachineInstr *MI,
191                              const TargetInstrInfo &TII) {
192  MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
193
194  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
195    MachineOperand &MO = MI->getOperand(i);
196    if (i == OpNo) {
197      assert(MO.isReg() && "Expected to fold into reg operand!");
198      MIB = addFrameReference(MIB, FrameIndex);
199    } else if (MO.isReg())
200      MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
201    else if (MO.isImm())
202      MIB = MIB.addImm(MO.getImm());
203    else if (MO.isGlobalAddress())
204      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
205    else if (MO.isJumpTableIndex())
206      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
207    else if (MO.isExternalSymbol())
208      MIB = MIB.addExternalSymbol(MO.getSymbolName());
209    else
210      assert(0 && "Unknown operand for FuseInst!");
211  }
212  return MIB;
213}
214
215static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII,
216                                unsigned Opcode, unsigned FrameIndex,
217                                MachineInstr *MI) {
218  return addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex).addImm(0);
219}
220
221
222//===----------------------------------------------------------------------===//
223// Efficient Lookup Table Support
224//===----------------------------------------------------------------------===//
225
226namespace {
227  /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
228  ///
229  struct TableEntry {
230    unsigned from;                      // Original opcode.
231    unsigned to;                        // New opcode.
232
233    // less operators used by STL search.
234    bool operator<(const TableEntry &TE) const { return from < TE.from; }
235    friend bool operator<(const TableEntry &TE, unsigned V) {
236      return TE.from < V;
237    }
238    friend bool operator<(unsigned V, const TableEntry &TE) {
239      return V < TE.from;
240    }
241  };
242}
243
244/// TableIsSorted - Return true if the table is in 'from' opcode order.
245///
246static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
247  for (unsigned i = 1; i != NumEntries; ++i)
248    if (!(Table[i-1] < Table[i])) {
249      cerr << "Entries out of order " << Table[i-1].from
250           << " " << Table[i].from << "\n";
251      return false;
252    }
253  return true;
254}
255
256/// TableLookup - Return the table entry matching the specified opcode.
257/// Otherwise return NULL.
258static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
259                                unsigned Opcode) {
260  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
261  if (I != Table+N && I->from == Opcode)
262    return I;
263  return NULL;
264}
265
266#define ARRAY_SIZE(TABLE)  \
267   (sizeof(TABLE)/sizeof(TABLE[0]))
268
269#ifdef NDEBUG
270#define ASSERT_SORTED(TABLE)
271#else
272#define ASSERT_SORTED(TABLE)                                              \
273  { static bool TABLE##Checked = false;                                   \
274    if (!TABLE##Checked) {                                                \
275       assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) &&                  \
276              "All lookup tables must be sorted for efficient access!");  \
277       TABLE##Checked = true;                                             \
278    }                                                                     \
279  }
280#endif
281
282
283MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
284                                                 unsigned i,
285                                                 int FrameIndex) const {
286  // Check switch flag
287  if (NoFusing) return NULL;
288
289  // Table (and size) to search
290  const TableEntry *OpcodeTablePtr = NULL;
291  unsigned OpcodeTableSize = 0;
292  bool isTwoAddrFold = false;
293  unsigned NumOps = TII.getNumOperands(MI->getOpcode());
294  bool isTwoAddr = NumOps > 1 &&
295    MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
296
297  MachineInstr *NewMI = NULL;
298  // Folding a memory location into the two-address part of a two-address
299  // instruction is different than folding it other places.  It requires
300  // replacing the *two* registers with the memory location.
301  if (isTwoAddr && NumOps >= 2 && i < 2 &&
302      MI->getOperand(0).isReg() &&
303      MI->getOperand(1).isReg() &&
304      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
305    static const TableEntry OpcodeTable[] = {
306      { X86::ADC32ri,     X86::ADC32mi },
307      { X86::ADC32ri8,    X86::ADC32mi8 },
308      { X86::ADC32rr,     X86::ADC32mr },
309      { X86::ADC64ri32,   X86::ADC64mi32 },
310      { X86::ADC64ri8,    X86::ADC64mi8 },
311      { X86::ADC64rr,     X86::ADC64mr },
312      { X86::ADD16ri,     X86::ADD16mi },
313      { X86::ADD16ri8,    X86::ADD16mi8 },
314      { X86::ADD16rr,     X86::ADD16mr },
315      { X86::ADD32ri,     X86::ADD32mi },
316      { X86::ADD32ri8,    X86::ADD32mi8 },
317      { X86::ADD32rr,     X86::ADD32mr },
318      { X86::ADD64ri32,   X86::ADD64mi32 },
319      { X86::ADD64ri8,    X86::ADD64mi8 },
320      { X86::ADD64rr,     X86::ADD64mr },
321      { X86::ADD8ri,      X86::ADD8mi },
322      { X86::ADD8rr,      X86::ADD8mr },
323      { X86::AND16ri,     X86::AND16mi },
324      { X86::AND16ri8,    X86::AND16mi8 },
325      { X86::AND16rr,     X86::AND16mr },
326      { X86::AND32ri,     X86::AND32mi },
327      { X86::AND32ri8,    X86::AND32mi8 },
328      { X86::AND32rr,     X86::AND32mr },
329      { X86::AND64ri32,   X86::AND64mi32 },
330      { X86::AND64ri8,    X86::AND64mi8 },
331      { X86::AND64rr,     X86::AND64mr },
332      { X86::AND8ri,      X86::AND8mi },
333      { X86::AND8rr,      X86::AND8mr },
334      { X86::DEC16r,      X86::DEC16m },
335      { X86::DEC32r,      X86::DEC32m },
336      { X86::DEC64_16r,   X86::DEC16m },
337      { X86::DEC64_32r,   X86::DEC32m },
338      { X86::DEC64r,      X86::DEC64m },
339      { X86::DEC8r,       X86::DEC8m },
340      { X86::INC16r,      X86::INC16m },
341      { X86::INC32r,      X86::INC32m },
342      { X86::INC64_16r,   X86::INC16m },
343      { X86::INC64_32r,   X86::INC32m },
344      { X86::INC64r,      X86::INC64m },
345      { X86::INC8r,       X86::INC8m },
346      { X86::NEG16r,      X86::NEG16m },
347      { X86::NEG32r,      X86::NEG32m },
348      { X86::NEG64r,      X86::NEG64m },
349      { X86::NEG8r,       X86::NEG8m },
350      { X86::NOT16r,      X86::NOT16m },
351      { X86::NOT32r,      X86::NOT32m },
352      { X86::NOT64r,      X86::NOT64m },
353      { X86::NOT8r,       X86::NOT8m },
354      { X86::OR16ri,      X86::OR16mi },
355      { X86::OR16ri8,     X86::OR16mi8 },
356      { X86::OR16rr,      X86::OR16mr },
357      { X86::OR32ri,      X86::OR32mi },
358      { X86::OR32ri8,     X86::OR32mi8 },
359      { X86::OR32rr,      X86::OR32mr },
360      { X86::OR64ri32,    X86::OR64mi32 },
361      { X86::OR64ri8,     X86::OR64mi8 },
362      { X86::OR64rr,      X86::OR64mr },
363      { X86::OR8ri,       X86::OR8mi },
364      { X86::OR8rr,       X86::OR8mr },
365      { X86::ROL16r1,     X86::ROL16m1 },
366      { X86::ROL16rCL,    X86::ROL16mCL },
367      { X86::ROL16ri,     X86::ROL16mi },
368      { X86::ROL32r1,     X86::ROL32m1 },
369      { X86::ROL32rCL,    X86::ROL32mCL },
370      { X86::ROL32ri,     X86::ROL32mi },
371      { X86::ROL64r1,     X86::ROL64m1 },
372      { X86::ROL64rCL,    X86::ROL64mCL },
373      { X86::ROL64ri,     X86::ROL64mi },
374      { X86::ROL8r1,      X86::ROL8m1 },
375      { X86::ROL8rCL,     X86::ROL8mCL },
376      { X86::ROL8ri,      X86::ROL8mi },
377      { X86::ROR16r1,     X86::ROR16m1 },
378      { X86::ROR16rCL,    X86::ROR16mCL },
379      { X86::ROR16ri,     X86::ROR16mi },
380      { X86::ROR32r1,     X86::ROR32m1 },
381      { X86::ROR32rCL,    X86::ROR32mCL },
382      { X86::ROR32ri,     X86::ROR32mi },
383      { X86::ROR64r1,     X86::ROR64m1 },
384      { X86::ROR64rCL,    X86::ROR64mCL },
385      { X86::ROR64ri,     X86::ROR64mi },
386      { X86::ROR8r1,      X86::ROR8m1 },
387      { X86::ROR8rCL,     X86::ROR8mCL },
388      { X86::ROR8ri,      X86::ROR8mi },
389      { X86::SAR16r1,     X86::SAR16m1 },
390      { X86::SAR16rCL,    X86::SAR16mCL },
391      { X86::SAR16ri,     X86::SAR16mi },
392      { X86::SAR32r1,     X86::SAR32m1 },
393      { X86::SAR32rCL,    X86::SAR32mCL },
394      { X86::SAR32ri,     X86::SAR32mi },
395      { X86::SAR64r1,     X86::SAR64m1 },
396      { X86::SAR64rCL,    X86::SAR64mCL },
397      { X86::SAR64ri,     X86::SAR64mi },
398      { X86::SAR8r1,      X86::SAR8m1 },
399      { X86::SAR8rCL,     X86::SAR8mCL },
400      { X86::SAR8ri,      X86::SAR8mi },
401      { X86::SBB32ri,     X86::SBB32mi },
402      { X86::SBB32ri8,    X86::SBB32mi8 },
403      { X86::SBB32rr,     X86::SBB32mr },
404      { X86::SBB64ri32,   X86::SBB64mi32 },
405      { X86::SBB64ri8,    X86::SBB64mi8 },
406      { X86::SBB64rr,     X86::SBB64mr },
407      { X86::SHL16r1,     X86::SHL16m1 },
408      { X86::SHL16rCL,    X86::SHL16mCL },
409      { X86::SHL16ri,     X86::SHL16mi },
410      { X86::SHL32r1,     X86::SHL32m1 },
411      { X86::SHL32rCL,    X86::SHL32mCL },
412      { X86::SHL32ri,     X86::SHL32mi },
413      { X86::SHL64r1,     X86::SHL64m1 },
414      { X86::SHL64rCL,    X86::SHL64mCL },
415      { X86::SHL64ri,     X86::SHL64mi },
416      { X86::SHL8r1,      X86::SHL8m1 },
417      { X86::SHL8rCL,     X86::SHL8mCL },
418      { X86::SHL8ri,      X86::SHL8mi },
419      { X86::SHLD16rrCL,  X86::SHLD16mrCL },
420      { X86::SHLD16rri8,  X86::SHLD16mri8 },
421      { X86::SHLD32rrCL,  X86::SHLD32mrCL },
422      { X86::SHLD32rri8,  X86::SHLD32mri8 },
423      { X86::SHLD64rrCL,  X86::SHLD64mrCL },
424      { X86::SHLD64rri8,  X86::SHLD64mri8 },
425      { X86::SHR16r1,     X86::SHR16m1 },
426      { X86::SHR16rCL,    X86::SHR16mCL },
427      { X86::SHR16ri,     X86::SHR16mi },
428      { X86::SHR32r1,     X86::SHR32m1 },
429      { X86::SHR32rCL,    X86::SHR32mCL },
430      { X86::SHR32ri,     X86::SHR32mi },
431      { X86::SHR64r1,     X86::SHR64m1 },
432      { X86::SHR64rCL,    X86::SHR64mCL },
433      { X86::SHR64ri,     X86::SHR64mi },
434      { X86::SHR8r1,      X86::SHR8m1 },
435      { X86::SHR8rCL,     X86::SHR8mCL },
436      { X86::SHR8ri,      X86::SHR8mi },
437      { X86::SHRD16rrCL,  X86::SHRD16mrCL },
438      { X86::SHRD16rri8,  X86::SHRD16mri8 },
439      { X86::SHRD32rrCL,  X86::SHRD32mrCL },
440      { X86::SHRD32rri8,  X86::SHRD32mri8 },
441      { X86::SHRD64rrCL,  X86::SHRD64mrCL },
442      { X86::SHRD64rri8,  X86::SHRD64mri8 },
443      { X86::SUB16ri,     X86::SUB16mi },
444      { X86::SUB16ri8,    X86::SUB16mi8 },
445      { X86::SUB16rr,     X86::SUB16mr },
446      { X86::SUB32ri,     X86::SUB32mi },
447      { X86::SUB32ri8,    X86::SUB32mi8 },
448      { X86::SUB32rr,     X86::SUB32mr },
449      { X86::SUB64ri32,   X86::SUB64mi32 },
450      { X86::SUB64ri8,    X86::SUB64mi8 },
451      { X86::SUB64rr,     X86::SUB64mr },
452      { X86::SUB8ri,      X86::SUB8mi },
453      { X86::SUB8rr,      X86::SUB8mr },
454      { X86::XOR16ri,     X86::XOR16mi },
455      { X86::XOR16ri8,    X86::XOR16mi8 },
456      { X86::XOR16rr,     X86::XOR16mr },
457      { X86::XOR32ri,     X86::XOR32mi },
458      { X86::XOR32ri8,    X86::XOR32mi8 },
459      { X86::XOR32rr,     X86::XOR32mr },
460      { X86::XOR64ri32,   X86::XOR64mi32 },
461      { X86::XOR64ri8,    X86::XOR64mi8 },
462      { X86::XOR64rr,     X86::XOR64mr },
463      { X86::XOR8ri,      X86::XOR8mi },
464      { X86::XOR8rr,      X86::XOR8mr }
465    };
466    ASSERT_SORTED(OpcodeTable);
467    OpcodeTablePtr = OpcodeTable;
468    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
469    isTwoAddrFold = true;
470  } else if (i == 0) { // If operand 0
471    if (MI->getOpcode() == X86::MOV16r0)
472      NewMI = MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI);
473    else if (MI->getOpcode() == X86::MOV32r0)
474      NewMI = MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI);
475    else if (MI->getOpcode() == X86::MOV64r0)
476      NewMI = MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI);
477    else if (MI->getOpcode() == X86::MOV8r0)
478      NewMI = MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI);
479    if (NewMI) {
480      NewMI->copyKillDeadInfo(MI);
481      return NewMI;
482    }
483
484    static const TableEntry OpcodeTable[] = {
485      { X86::CMP16ri,     X86::CMP16mi },
486      { X86::CMP16ri8,    X86::CMP16mi8 },
487      { X86::CMP32ri,     X86::CMP32mi },
488      { X86::CMP32ri8,    X86::CMP32mi8 },
489      { X86::CMP8ri,      X86::CMP8mi },
490      { X86::DIV16r,      X86::DIV16m },
491      { X86::DIV32r,      X86::DIV32m },
492      { X86::DIV64r,      X86::DIV64m },
493      { X86::DIV8r,       X86::DIV8m },
494      { X86::FsMOVAPDrr,  X86::MOVSDmr },
495      { X86::FsMOVAPSrr,  X86::MOVSSmr },
496      { X86::IDIV16r,     X86::IDIV16m },
497      { X86::IDIV32r,     X86::IDIV32m },
498      { X86::IDIV64r,     X86::IDIV64m },
499      { X86::IDIV8r,      X86::IDIV8m },
500      { X86::IMUL16r,     X86::IMUL16m },
501      { X86::IMUL32r,     X86::IMUL32m },
502      { X86::IMUL64r,     X86::IMUL64m },
503      { X86::IMUL8r,      X86::IMUL8m },
504      { X86::MOV16ri,     X86::MOV16mi },
505      { X86::MOV16rr,     X86::MOV16mr },
506      { X86::MOV32ri,     X86::MOV32mi },
507      { X86::MOV32rr,     X86::MOV32mr },
508      { X86::MOV64ri32,   X86::MOV64mi32 },
509      { X86::MOV64rr,     X86::MOV64mr },
510      { X86::MOV8ri,      X86::MOV8mi },
511      { X86::MOV8rr,      X86::MOV8mr },
512      { X86::MOVAPDrr,    X86::MOVAPDmr },
513      { X86::MOVAPSrr,    X86::MOVAPSmr },
514      { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
515      { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
516      { X86::MOVPS2SSrr,  X86::MOVPS2SSmr },
517      { X86::MOVSDrr,     X86::MOVSDmr },
518      { X86::MOVSDto64rr, X86::MOVSDto64mr },
519      { X86::MOVSS2DIrr,  X86::MOVSS2DImr },
520      { X86::MOVSSrr,     X86::MOVSSmr },
521      { X86::MOVUPDrr,    X86::MOVUPDmr },
522      { X86::MOVUPSrr,    X86::MOVUPSmr },
523      { X86::MUL16r,      X86::MUL16m },
524      { X86::MUL32r,      X86::MUL32m },
525      { X86::MUL64r,      X86::MUL64m },
526      { X86::MUL8r,       X86::MUL8m },
527      { X86::SETAEr,      X86::SETAEm },
528      { X86::SETAr,       X86::SETAm },
529      { X86::SETBEr,      X86::SETBEm },
530      { X86::SETBr,       X86::SETBm },
531      { X86::SETEr,       X86::SETEm },
532      { X86::SETGEr,      X86::SETGEm },
533      { X86::SETGr,       X86::SETGm },
534      { X86::SETLEr,      X86::SETLEm },
535      { X86::SETLr,       X86::SETLm },
536      { X86::SETNEr,      X86::SETNEm },
537      { X86::SETNPr,      X86::SETNPm },
538      { X86::SETNSr,      X86::SETNSm },
539      { X86::SETPr,       X86::SETPm },
540      { X86::SETSr,       X86::SETSm },
541      { X86::TEST16ri,    X86::TEST16mi },
542      { X86::TEST32ri,    X86::TEST32mi },
543      { X86::TEST64ri32,  X86::TEST64mi32 },
544      { X86::TEST8ri,     X86::TEST8mi },
545      { X86::XCHG16rr,    X86::XCHG16mr },
546      { X86::XCHG32rr,    X86::XCHG32mr },
547      { X86::XCHG64rr,    X86::XCHG64mr },
548      { X86::XCHG8rr,     X86::XCHG8mr }
549    };
550    ASSERT_SORTED(OpcodeTable);
551    OpcodeTablePtr = OpcodeTable;
552    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
553  } else if (i == 1) {
554    static const TableEntry OpcodeTable[] = {
555      { X86::CMP16rr,         X86::CMP16rm },
556      { X86::CMP32rr,         X86::CMP32rm },
557      { X86::CMP64ri32,       X86::CMP64mi32 },
558      { X86::CMP64ri8,        X86::CMP64mi8 },
559      { X86::CMP64rr,         X86::CMP64rm },
560      { X86::CMP8rr,          X86::CMP8rm },
561      { X86::CMPPDrri,        X86::CMPPDrmi },
562      { X86::CMPPSrri,        X86::CMPPSrmi },
563      { X86::CMPSDrr,         X86::CMPSDrm },
564      { X86::CMPSSrr,         X86::CMPSSrm },
565      { X86::CVTSD2SSrr,      X86::CVTSD2SSrm },
566      { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm },
567      { X86::CVTSI2SDrr,      X86::CVTSI2SDrm },
568      { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm },
569      { X86::CVTSI2SSrr,      X86::CVTSI2SSrm },
570      { X86::CVTSS2SDrr,      X86::CVTSS2SDrm },
571      { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm },
572      { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm },
573      { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm },
574      { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm },
575      { X86::FsMOVAPDrr,      X86::MOVSDrm },
576      { X86::FsMOVAPSrr,      X86::MOVSSrm },
577      { X86::IMUL16rri,       X86::IMUL16rmi },
578      { X86::IMUL16rri8,      X86::IMUL16rmi8 },
579      { X86::IMUL32rri,       X86::IMUL32rmi },
580      { X86::IMUL32rri8,      X86::IMUL32rmi8 },
581      { X86::IMUL64rr,        X86::IMUL64rm },
582      { X86::IMUL64rri32,     X86::IMUL64rmi32 },
583      { X86::IMUL64rri8,      X86::IMUL64rmi8 },
584      { X86::Int_CMPSDrr,     X86::Int_CMPSDrm },
585      { X86::Int_CMPSSrr,     X86::Int_CMPSSrm },
586      { X86::Int_COMISDrr,    X86::Int_COMISDrm },
587      { X86::Int_COMISSrr,    X86::Int_COMISSrm },
588      { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm },
589      { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm },
590      { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm },
591      { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm },
592      { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm },
593      { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm },
594      { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
595      { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm },
596      { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm },
597      { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
598      { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm },
599      { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
600      { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm },
601      { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm },
602      { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
603      { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm },
604      { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
605      { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
606      { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
607      { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
608      { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
609      { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
610      { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm },
611      { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm },
612      { X86::MOV16rr,         X86::MOV16rm },
613      { X86::MOV32rr,         X86::MOV32rm },
614      { X86::MOV64rr,         X86::MOV64rm },
615      { X86::MOV64toPQIrr,    X86::MOV64toPQIrm },
616      { X86::MOV64toSDrr,     X86::MOV64toSDrm },
617      { X86::MOV8rr,          X86::MOV8rm },
618      { X86::MOVAPDrr,        X86::MOVAPDrm },
619      { X86::MOVAPSrr,        X86::MOVAPSrm },
620      { X86::MOVDDUPrr,       X86::MOVDDUPrm },
621      { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm },
622      { X86::MOVDI2SSrr,      X86::MOVDI2SSrm },
623      { X86::MOVSD2PDrr,      X86::MOVSD2PDrm },
624      { X86::MOVSDrr,         X86::MOVSDrm },
625      { X86::MOVSHDUPrr,      X86::MOVSHDUPrm },
626      { X86::MOVSLDUPrr,      X86::MOVSLDUPrm },
627      { X86::MOVSS2PSrr,      X86::MOVSS2PSrm },
628      { X86::MOVSSrr,         X86::MOVSSrm },
629      { X86::MOVSX16rr8,      X86::MOVSX16rm8 },
630      { X86::MOVSX32rr16,     X86::MOVSX32rm16 },
631      { X86::MOVSX32rr8,      X86::MOVSX32rm8 },
632      { X86::MOVSX64rr16,     X86::MOVSX64rm16 },
633      { X86::MOVSX64rr32,     X86::MOVSX64rm32 },
634      { X86::MOVSX64rr8,      X86::MOVSX64rm8 },
635      { X86::MOVUPDrr,        X86::MOVUPDrm },
636      { X86::MOVUPSrr,        X86::MOVUPSrm },
637      { X86::MOVZX16rr8,      X86::MOVZX16rm8 },
638      { X86::MOVZX32rr16,     X86::MOVZX32rm16 },
639      { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
640      { X86::MOVZX64rr16,     X86::MOVZX64rm16 },
641      { X86::MOVZX64rr8,      X86::MOVZX64rm8 },
642      { X86::PSHUFDri,        X86::PSHUFDmi },
643      { X86::PSHUFHWri,       X86::PSHUFHWmi },
644      { X86::PSHUFLWri,       X86::PSHUFLWmi },
645      { X86::PsMOVZX64rr32,   X86::PsMOVZX64rm32 },
646      { X86::TEST16rr,        X86::TEST16rm },
647      { X86::TEST32rr,        X86::TEST32rm },
648      { X86::TEST64rr,        X86::TEST64rm },
649      { X86::TEST8rr,         X86::TEST8rm },
650      // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
651      { X86::UCOMISDrr,       X86::UCOMISDrm },
652      { X86::UCOMISSrr,       X86::UCOMISSrm },
653      { X86::XCHG16rr,        X86::XCHG16rm },
654      { X86::XCHG32rr,        X86::XCHG32rm },
655      { X86::XCHG64rr,        X86::XCHG64rm },
656      { X86::XCHG8rr,         X86::XCHG8rm }
657    };
658    ASSERT_SORTED(OpcodeTable);
659    OpcodeTablePtr = OpcodeTable;
660    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
661  } else if (i == 2) {
662    static const TableEntry OpcodeTable[] = {
663      { X86::ADC32rr,         X86::ADC32rm },
664      { X86::ADC64rr,         X86::ADC64rm },
665      { X86::ADD16rr,         X86::ADD16rm },
666      { X86::ADD32rr,         X86::ADD32rm },
667      { X86::ADD64rr,         X86::ADD64rm },
668      { X86::ADD8rr,          X86::ADD8rm },
669      { X86::ADDPDrr,         X86::ADDPDrm },
670      { X86::ADDPSrr,         X86::ADDPSrm },
671      { X86::ADDSDrr,         X86::ADDSDrm },
672      { X86::ADDSSrr,         X86::ADDSSrm },
673      { X86::ADDSUBPDrr,      X86::ADDSUBPDrm },
674      { X86::ADDSUBPSrr,      X86::ADDSUBPSrm },
675      { X86::AND16rr,         X86::AND16rm },
676      { X86::AND32rr,         X86::AND32rm },
677      { X86::AND64rr,         X86::AND64rm },
678      { X86::AND8rr,          X86::AND8rm },
679      { X86::ANDNPDrr,        X86::ANDNPDrm },
680      { X86::ANDNPSrr,        X86::ANDNPSrm },
681      { X86::ANDPDrr,         X86::ANDPDrm },
682      { X86::ANDPSrr,         X86::ANDPSrm },
683      { X86::CMOVA16rr,       X86::CMOVA16rm },
684      { X86::CMOVA32rr,       X86::CMOVA32rm },
685      { X86::CMOVA64rr,       X86::CMOVA64rm },
686      { X86::CMOVAE16rr,      X86::CMOVAE16rm },
687      { X86::CMOVAE32rr,      X86::CMOVAE32rm },
688      { X86::CMOVAE64rr,      X86::CMOVAE64rm },
689      { X86::CMOVB16rr,       X86::CMOVB16rm },
690      { X86::CMOVB32rr,       X86::CMOVB32rm },
691      { X86::CMOVB64rr,       X86::CMOVB64rm },
692      { X86::CMOVBE16rr,      X86::CMOVBE16rm },
693      { X86::CMOVBE32rr,      X86::CMOVBE32rm },
694      { X86::CMOVBE64rr,      X86::CMOVBE64rm },
695      { X86::CMOVE16rr,       X86::CMOVE16rm },
696      { X86::CMOVE32rr,       X86::CMOVE32rm },
697      { X86::CMOVE64rr,       X86::CMOVE64rm },
698      { X86::CMOVG16rr,       X86::CMOVG16rm },
699      { X86::CMOVG32rr,       X86::CMOVG32rm },
700      { X86::CMOVG64rr,       X86::CMOVG64rm },
701      { X86::CMOVGE16rr,      X86::CMOVGE16rm },
702      { X86::CMOVGE32rr,      X86::CMOVGE32rm },
703      { X86::CMOVGE64rr,      X86::CMOVGE64rm },
704      { X86::CMOVL16rr,       X86::CMOVL16rm },
705      { X86::CMOVL32rr,       X86::CMOVL32rm },
706      { X86::CMOVL64rr,       X86::CMOVL64rm },
707      { X86::CMOVLE16rr,      X86::CMOVLE16rm },
708      { X86::CMOVLE32rr,      X86::CMOVLE32rm },
709      { X86::CMOVLE64rr,      X86::CMOVLE64rm },
710      { X86::CMOVNE16rr,      X86::CMOVNE16rm },
711      { X86::CMOVNE32rr,      X86::CMOVNE32rm },
712      { X86::CMOVNE64rr,      X86::CMOVNE64rm },
713      { X86::CMOVNP16rr,      X86::CMOVNP16rm },
714      { X86::CMOVNP32rr,      X86::CMOVNP32rm },
715      { X86::CMOVNP64rr,      X86::CMOVNP64rm },
716      { X86::CMOVNS16rr,      X86::CMOVNS16rm },
717      { X86::CMOVNS32rr,      X86::CMOVNS32rm },
718      { X86::CMOVNS64rr,      X86::CMOVNS64rm },
719      { X86::CMOVP16rr,       X86::CMOVP16rm },
720      { X86::CMOVP32rr,       X86::CMOVP32rm },
721      { X86::CMOVP64rr,       X86::CMOVP64rm },
722      { X86::CMOVS16rr,       X86::CMOVS16rm },
723      { X86::CMOVS32rr,       X86::CMOVS32rm },
724      { X86::CMOVS64rr,       X86::CMOVS64rm },
725      { X86::DIVPDrr,         X86::DIVPDrm },
726      { X86::DIVPSrr,         X86::DIVPSrm },
727      { X86::DIVSDrr,         X86::DIVSDrm },
728      { X86::DIVSSrr,         X86::DIVSSrm },
729      { X86::HADDPDrr,        X86::HADDPDrm },
730      { X86::HADDPSrr,        X86::HADDPSrm },
731      { X86::HSUBPDrr,        X86::HSUBPDrm },
732      { X86::HSUBPSrr,        X86::HSUBPSrm },
733      { X86::IMUL16rr,        X86::IMUL16rm },
734      { X86::IMUL32rr,        X86::IMUL32rm },
735      { X86::MAXPDrr,         X86::MAXPDrm },
736      { X86::MAXPSrr,         X86::MAXPSrm },
737      { X86::MINPDrr,         X86::MINPDrm },
738      { X86::MINPSrr,         X86::MINPSrm },
739      { X86::MULPDrr,         X86::MULPDrm },
740      { X86::MULPSrr,         X86::MULPSrm },
741      { X86::MULSDrr,         X86::MULSDrm },
742      { X86::MULSSrr,         X86::MULSSrm },
743      { X86::OR16rr,          X86::OR16rm },
744      { X86::OR32rr,          X86::OR32rm },
745      { X86::OR64rr,          X86::OR64rm },
746      { X86::OR8rr,           X86::OR8rm },
747      { X86::ORPDrr,          X86::ORPDrm },
748      { X86::ORPSrr,          X86::ORPSrm },
749      { X86::PACKSSDWrr,      X86::PACKSSDWrm },
750      { X86::PACKSSWBrr,      X86::PACKSSWBrm },
751      { X86::PACKUSWBrr,      X86::PACKUSWBrm },
752      { X86::PADDBrr,         X86::PADDBrm },
753      { X86::PADDDrr,         X86::PADDDrm },
754      { X86::PADDSBrr,        X86::PADDSBrm },
755      { X86::PADDSWrr,        X86::PADDSWrm },
756      { X86::PADDWrr,         X86::PADDWrm },
757      { X86::PANDNrr,         X86::PANDNrm },
758      { X86::PANDrr,          X86::PANDrm },
759      { X86::PAVGBrr,         X86::PAVGBrm },
760      { X86::PAVGWrr,         X86::PAVGWrm },
761      { X86::PCMPEQBrr,       X86::PCMPEQBrm },
762      { X86::PCMPEQDrr,       X86::PCMPEQDrm },
763      { X86::PCMPEQWrr,       X86::PCMPEQWrm },
764      { X86::PCMPGTBrr,       X86::PCMPGTBrm },
765      { X86::PCMPGTDrr,       X86::PCMPGTDrm },
766      { X86::PCMPGTWrr,       X86::PCMPGTWrm },
767      { X86::PINSRWrri,       X86::PINSRWrmi },
768      { X86::PMADDWDrr,       X86::PMADDWDrm },
769      { X86::PMAXSWrr,        X86::PMAXSWrm },
770      { X86::PMAXUBrr,        X86::PMAXUBrm },
771      { X86::PMINSWrr,        X86::PMINSWrm },
772      { X86::PMINUBrr,        X86::PMINUBrm },
773      { X86::PMULHUWrr,       X86::PMULHUWrm },
774      { X86::PMULHWrr,        X86::PMULHWrm },
775      { X86::PMULLWrr,        X86::PMULLWrm },
776      { X86::PMULUDQrr,       X86::PMULUDQrm },
777      { X86::PORrr,           X86::PORrm },
778      { X86::PSADBWrr,        X86::PSADBWrm },
779      { X86::PSLLDrr,         X86::PSLLDrm },
780      { X86::PSLLQrr,         X86::PSLLQrm },
781      { X86::PSLLWrr,         X86::PSLLWrm },
782      { X86::PSRADrr,         X86::PSRADrm },
783      { X86::PSRAWrr,         X86::PSRAWrm },
784      { X86::PSRLDrr,         X86::PSRLDrm },
785      { X86::PSRLQrr,         X86::PSRLQrm },
786      { X86::PSRLWrr,         X86::PSRLWrm },
787      { X86::PSUBBrr,         X86::PSUBBrm },
788      { X86::PSUBDrr,         X86::PSUBDrm },
789      { X86::PSUBSBrr,        X86::PSUBSBrm },
790      { X86::PSUBSWrr,        X86::PSUBSWrm },
791      { X86::PSUBWrr,         X86::PSUBWrm },
792      { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm },
793      { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm },
794      { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm },
795      { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm },
796      { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm },
797      { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm },
798      { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm },
799      { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm },
800      { X86::PXORrr,          X86::PXORrm },
801      { X86::RCPPSr,          X86::RCPPSm },
802      { X86::RSQRTPSr,        X86::RSQRTPSm },
803      { X86::SBB32rr,         X86::SBB32rm },
804      { X86::SBB64rr,         X86::SBB64rm },
805      { X86::SHUFPDrri,       X86::SHUFPDrmi },
806      { X86::SHUFPSrri,       X86::SHUFPSrmi },
807      { X86::SQRTPDr,         X86::SQRTPDm },
808      { X86::SQRTPSr,         X86::SQRTPSm },
809      { X86::SQRTSDr,         X86::SQRTSDm },
810      { X86::SQRTSSr,         X86::SQRTSSm },
811      { X86::SUB16rr,         X86::SUB16rm },
812      { X86::SUB32rr,         X86::SUB32rm },
813      { X86::SUB64rr,         X86::SUB64rm },
814      { X86::SUB8rr,          X86::SUB8rm },
815      { X86::SUBPDrr,         X86::SUBPDrm },
816      { X86::SUBPSrr,         X86::SUBPSrm },
817      { X86::SUBSDrr,         X86::SUBSDrm },
818      { X86::SUBSSrr,         X86::SUBSSrm },
819      // FIXME: TEST*rr -> swapped operand of TEST*mr.
820      { X86::UNPCKHPDrr,      X86::UNPCKHPDrm },
821      { X86::UNPCKHPSrr,      X86::UNPCKHPSrm },
822      { X86::UNPCKLPDrr,      X86::UNPCKLPDrm },
823      { X86::UNPCKLPSrr,      X86::UNPCKLPSrm },
824      { X86::XOR16rr,         X86::XOR16rm },
825      { X86::XOR32rr,         X86::XOR32rm },
826      { X86::XOR64rr,         X86::XOR64rm },
827      { X86::XOR8rr,          X86::XOR8rm },
828      { X86::XORPDrr,         X86::XORPDrm },
829      { X86::XORPSrr,         X86::XORPSrm }
830    };
831    ASSERT_SORTED(OpcodeTable);
832    OpcodeTablePtr = OpcodeTable;
833    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
834  }
835
836  // If table selected...
837  if (OpcodeTablePtr) {
838    // Find the Opcode to fuse
839    unsigned fromOpcode = MI->getOpcode();
840    // Lookup fromOpcode in table
841    if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
842                                              fromOpcode)) {
843      if (isTwoAddrFold)
844        NewMI = FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
845      else
846        NewMI = FuseInst(Entry->to, i, FrameIndex, MI, TII);
847      NewMI->copyKillDeadInfo(MI);
848      return NewMI;
849    }
850  }
851
852  // No fusion
853  if (PrintFailedFusing)
854    cerr << "We failed to fuse ("
855         << ((i == 1) ? "r" : "s") << "): " << *MI;
856  return NULL;
857}
858
859
860const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
861  static const unsigned CalleeSavedRegs32Bit[] = {
862    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
863  };
864  static const unsigned CalleeSavedRegs64Bit[] = {
865    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
866  };
867
868  return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
869}
870
871const TargetRegisterClass* const*
872X86RegisterInfo::getCalleeSavedRegClasses() const {
873  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
874    &X86::GR32RegClass, &X86::GR32RegClass,
875    &X86::GR32RegClass, &X86::GR32RegClass,  0
876  };
877  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
878    &X86::GR64RegClass, &X86::GR64RegClass,
879    &X86::GR64RegClass, &X86::GR64RegClass,
880    &X86::GR64RegClass, &X86::GR64RegClass, 0
881  };
882
883  return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
884}
885
886//===----------------------------------------------------------------------===//
887// Stack Frame Processing methods
888//===----------------------------------------------------------------------===//
889
890// hasFP - Return true if the specified function should have a dedicated frame
891// pointer register.  This is true if the function has variable sized allocas or
892// if frame pointer elimination is disabled.
893//
894static bool hasFP(const MachineFunction &MF) {
895  return (NoFramePointerElim ||
896          MF.getFrameInfo()->hasVarSizedObjects() ||
897          MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
898}
899
900void X86RegisterInfo::
901eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
902                              MachineBasicBlock::iterator I) const {
903  if (hasFP(MF)) {
904    // If we have a frame pointer, turn the adjcallstackup instruction into a
905    // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
906    // <amt>'
907    MachineInstr *Old = I;
908    unsigned Amount = Old->getOperand(0).getImmedValue();
909    if (Amount != 0) {
910      // We need to keep the stack aligned properly.  To do this, we round the
911      // amount of space needed for the outgoing arguments up to the next
912      // alignment boundary.
913      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
914      Amount = (Amount+Align-1)/Align*Align;
915
916      MachineInstr *New = 0;
917      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
918        New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
919          .addReg(StackPtr).addImm(Amount);
920      } else {
921        assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
922        // factor out the amount the callee already popped.
923        unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
924        Amount -= CalleeAmt;
925        if (Amount) {
926          unsigned Opc = (Amount < 128) ?
927            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
928            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
929          New = BuildMI(TII.get(Opc),  StackPtr).addReg(StackPtr).addImm(Amount);
930        }
931      }
932
933      // Replace the pseudo instruction with a new instruction...
934      if (New) MBB.insert(I, New);
935    }
936  } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
937    // If we are performing frame pointer elimination and if the callee pops
938    // something off the stack pointer, add it back.  We do this until we have
939    // more advanced stack pointer tracking ability.
940    if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
941      unsigned Opc = (CalleeAmt < 128) ?
942        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
943        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
944      MachineInstr *New =
945        BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
946      MBB.insert(I, New);
947    }
948  }
949
950  MBB.erase(I);
951}
952
953void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
954  unsigned i = 0;
955  MachineInstr &MI = *II;
956  MachineFunction &MF = *MI.getParent()->getParent();
957  while (!MI.getOperand(i).isFrameIndex()) {
958    ++i;
959    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
960  }
961
962  int FrameIndex = MI.getOperand(i).getFrameIndex();
963  // This must be part of a four operand memory reference.  Replace the
964  // FrameIndex with base register with EBP.  Add an offset to the offset.
965  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
966
967  // Now add the frame object offset to the offset from EBP.
968  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
969               MI.getOperand(i+3).getImmedValue()+SlotSize;
970
971  if (!hasFP(MF))
972    Offset += MF.getFrameInfo()->getStackSize();
973  else
974    Offset += SlotSize;  // Skip the saved EBP
975
976  MI.getOperand(i+3).ChangeToImmediate(Offset);
977}
978
979void
980X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
981  if (hasFP(MF)) {
982    // Create a frame entry for the EBP register that must be saved.
983    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,SlotSize * -2);
984    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
985           "Slot for EBP register must be last in order to be found!");
986  }
987}
988
989void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
990  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
991  MachineBasicBlock::iterator MBBI = MBB.begin();
992  MachineFrameInfo *MFI = MF.getFrameInfo();
993  unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
994  const Function* Fn = MF.getFunction();
995  const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
996  MachineInstr *MI;
997
998  // Get the number of bytes to allocate from the FrameInfo
999  unsigned NumBytes = MFI->getStackSize();
1000  if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
1001    // When we have no frame pointer, we reserve argument space for call sites
1002    // in the function immediately on entry to the current function.  This
1003    // eliminates the need for add/sub ESP brackets around call sites.
1004    //
1005    if (!hasFP(MF))
1006      NumBytes += MFI->getMaxCallFrameSize();
1007
1008    // Round the size to a multiple of the alignment (don't forget the 4/8 byte
1009    // offset though).
1010    NumBytes = ((NumBytes+SlotSize)+Align-1)/Align*Align - SlotSize;
1011  }
1012
1013  // Update frame info to pretend that this is part of the stack...
1014  MFI->setStackSize(NumBytes);
1015
1016  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
1017    if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1018      // Function prologue calls _alloca to probe the stack when allocating
1019      // more than 4k bytes in one go. Touching the stack at 4K increments is
1020      // necessary to ensure that the guard pages used by the OS virtual memory
1021      // manager are allocated in correct sequence.
1022      MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1023      MBB.insert(MBBI, MI);
1024      MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1025      MBB.insert(MBBI, MI);
1026    } else {
1027      unsigned Opc = (NumBytes < 128) ?
1028        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1029        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1030      MI= BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
1031      MBB.insert(MBBI, MI);
1032    }
1033  }
1034
1035  if (hasFP(MF)) {
1036    // Get the offset of the stack slot for the EBP register... which is
1037    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1038    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize;
1039    // Update the frame offset adjustment.
1040    MFI->setOffsetAdjustment(SlotSize-NumBytes);
1041
1042    // Save EBP into the appropriate stack slot...
1043    // mov [ESP-<offset>], EBP
1044    MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::MOV64mr : X86::MOV32mr)),
1045                      StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
1046    MBB.insert(MBBI, MI);
1047
1048    // Update EBP with the new base value...
1049    if (NumBytes == SlotSize)    // mov EBP, ESP
1050      MI = BuildMI(TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr).
1051        addReg(StackPtr);
1052    else                  // lea EBP, [ESP+StackSize]
1053      MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::LEA64r : X86::LEA32r),
1054                                FramePtr), StackPtr, NumBytes-SlotSize);
1055
1056    MBB.insert(MBBI, MI);
1057  }
1058
1059  // If it's main() on Cygwin\Mingw32 we should align stack as well
1060  if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1061      Subtarget->isTargetCygMing()) {
1062    MI= BuildMI(TII.get(X86::AND32ri), X86::ESP).addReg(X86::ESP).addImm(-Align);
1063    MBB.insert(MBBI, MI);
1064
1065    // Probe the stack
1066    MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
1067    MBB.insert(MBBI, MI);
1068    MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1069    MBB.insert(MBBI, MI);
1070  }
1071}
1072
1073void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1074                                   MachineBasicBlock &MBB) const {
1075  const MachineFrameInfo *MFI = MF.getFrameInfo();
1076  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1077
1078  switch (MBBI->getOpcode()) {
1079  case X86::RET:
1080  case X86::RETI:
1081  case X86::TAILJMPd:
1082  case X86::TAILJMPr:
1083  case X86::TAILJMPm: break;  // These are ok
1084  default:
1085    assert(0 && "Can only insert epilog into returning blocks");
1086  }
1087
1088  if (hasFP(MF)) {
1089    // mov ESP, EBP
1090    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1091      addReg(FramePtr);
1092
1093    // pop EBP
1094    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1095  } else {
1096    // Get the number of bytes allocated from the FrameInfo...
1097    unsigned NumBytes = MFI->getStackSize();
1098
1099    if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
1100      // If there is an ADD32ri or SUB32ri of ESP immediately before this
1101      // instruction, merge the two instructions.
1102      if (MBBI != MBB.begin()) {
1103        MachineBasicBlock::iterator PI = prior(MBBI);
1104        unsigned Opc = PI->getOpcode();
1105        if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1106             Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1107            PI->getOperand(0).getReg() == StackPtr) {
1108          NumBytes += PI->getOperand(2).getImmedValue();
1109          MBB.erase(PI);
1110        } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1111                    Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1112                   PI->getOperand(0).getReg() == StackPtr) {
1113          NumBytes -= PI->getOperand(2).getImmedValue();
1114          MBB.erase(PI);
1115        }
1116      }
1117
1118      if (NumBytes > 0) {
1119        unsigned Opc = (NumBytes < 128) ?
1120          (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1121          (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1122        BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
1123      } else if ((int)NumBytes < 0) {
1124        unsigned Opc = (-NumBytes < 128) ?
1125          (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1126          (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1127        BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(-NumBytes);
1128      }
1129    }
1130  }
1131}
1132
1133unsigned X86RegisterInfo::getRARegister() const {
1134  return X86::ST0;  // use a non-register register
1135}
1136
1137unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1138  return hasFP(MF) ? FramePtr : StackPtr;
1139}
1140
1141namespace llvm {
1142unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1143  switch (VT) {
1144  default: return Reg;
1145  case MVT::i8:
1146    if (High) {
1147      switch (Reg) {
1148      default: return 0;
1149      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1150        return X86::AH;
1151      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1152        return X86::DH;
1153      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1154        return X86::CH;
1155      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1156        return X86::BH;
1157      }
1158    } else {
1159      switch (Reg) {
1160      default: return 0;
1161      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1162        return X86::AL;
1163      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1164        return X86::DL;
1165      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1166        return X86::CL;
1167      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1168        return X86::BL;
1169      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1170        return X86::SIL;
1171      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1172        return X86::DIL;
1173      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1174        return X86::BPL;
1175      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1176        return X86::SPL;
1177      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1178        return X86::R8B;
1179      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1180        return X86::R9B;
1181      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1182        return X86::R10B;
1183      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1184        return X86::R11B;
1185      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1186        return X86::R12B;
1187      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1188        return X86::R13B;
1189      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1190        return X86::R14B;
1191      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1192        return X86::R15B;
1193      }
1194    }
1195  case MVT::i16:
1196    switch (Reg) {
1197    default: return Reg;
1198    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1199      return X86::AX;
1200    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1201      return X86::DX;
1202    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1203      return X86::CX;
1204    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1205      return X86::BX;
1206    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1207      return X86::SI;
1208    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1209      return X86::DI;
1210    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1211      return X86::BP;
1212    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1213      return X86::SP;
1214    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1215      return X86::R8W;
1216    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1217      return X86::R9W;
1218    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1219      return X86::R10W;
1220    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1221      return X86::R11W;
1222    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1223      return X86::R12W;
1224    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1225      return X86::R13W;
1226    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1227      return X86::R14W;
1228    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1229      return X86::R15W;
1230    }
1231  case MVT::i32:
1232    switch (Reg) {
1233    default: return Reg;
1234    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1235      return X86::EAX;
1236    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1237      return X86::EDX;
1238    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1239      return X86::ECX;
1240    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1241      return X86::EBX;
1242    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1243      return X86::ESI;
1244    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1245      return X86::EDI;
1246    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1247      return X86::EBP;
1248    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1249      return X86::ESP;
1250    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1251      return X86::R8D;
1252    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1253      return X86::R9D;
1254    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1255      return X86::R10D;
1256    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1257      return X86::R11D;
1258    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1259      return X86::R12D;
1260    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1261      return X86::R13D;
1262    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1263      return X86::R14D;
1264    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1265      return X86::R15D;
1266    }
1267  case MVT::i64:
1268    switch (Reg) {
1269    default: return Reg;
1270    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1271      return X86::RAX;
1272    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1273      return X86::RDX;
1274    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1275      return X86::RCX;
1276    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1277      return X86::RBX;
1278    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1279      return X86::RSI;
1280    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1281      return X86::RDI;
1282    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1283      return X86::RBP;
1284    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1285      return X86::RSP;
1286    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1287      return X86::R8;
1288    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1289      return X86::R9;
1290    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1291      return X86::R10;
1292    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1293      return X86::R11;
1294    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1295      return X86::R12;
1296    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1297      return X86::R13;
1298    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1299      return X86::R14;
1300    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1301      return X86::R15;
1302    }
1303  }
1304
1305  return Reg;
1306}
1307}
1308
1309#include "X86GenRegisterInfo.inc"
1310
1311