X86RegisterInfo.cpp revision b371f457b0ea4a652a9f526ba4375c80ae542252 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the MRegisterInfo class.  This
11// file is responsible for the frame pointer elimination optimization on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86RegisterInfo.h"
17#include "X86InstrBuilder.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/Type.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineLocation.h"
29#include "llvm/Target/TargetFrameInfo.h"
30#include "llvm/Target/TargetInstrInfo.h"
31#include "llvm/Target/TargetMachine.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/STLExtras.h"
36using namespace llvm;
37
38namespace {
39  cl::opt<bool>
40  NoFusing("disable-spill-fusing",
41           cl::desc("Disable fusing of spill code into instructions"));
42  cl::opt<bool>
43  PrintFailedFusing("print-failed-fuse-candidates",
44                    cl::desc("Print instructions that the allocator wants to"
45                             " fuse, but the X86 backend currently can't"),
46                    cl::Hidden);
47}
48
49X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
50                                 const TargetInstrInfo &tii)
51  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
52    TM(tm), TII(tii) {
53  // Cache some information.
54  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55  Is64Bit = Subtarget->is64Bit();
56  if (Is64Bit) {
57    SlotSize = 8;
58    StackPtr = X86::RSP;
59    FramePtr = X86::RBP;
60  } else {
61    SlotSize = 4;
62    StackPtr = X86::ESP;
63    FramePtr = X86::EBP;
64  }
65}
66
67void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
68                                          MachineBasicBlock::iterator MI,
69                                          unsigned SrcReg, int FrameIdx,
70                                          const TargetRegisterClass *RC) const {
71  unsigned Opc;
72  if (RC == &X86::GR64RegClass) {
73    Opc = X86::MOV64mr;
74  } else if (RC == &X86::GR32RegClass) {
75    Opc = X86::MOV32mr;
76  } else if (RC == &X86::GR16RegClass) {
77    Opc = X86::MOV16mr;
78  } else if (RC == &X86::GR8RegClass) {
79    Opc = X86::MOV8mr;
80  } else if (RC == &X86::GR32_RegClass) {
81    Opc = X86::MOV32_mr;
82  } else if (RC == &X86::GR16_RegClass) {
83    Opc = X86::MOV16_mr;
84  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
85    Opc = X86::FpST64m;
86  } else if (RC == &X86::FR32RegClass) {
87    Opc = X86::MOVSSmr;
88  } else if (RC == &X86::FR64RegClass) {
89    Opc = X86::MOVSDmr;
90  } else if (RC == &X86::VR128RegClass) {
91    Opc = X86::MOVAPSmr;
92  } else {
93    assert(0 && "Unknown regclass");
94    abort();
95  }
96  addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
97}
98
99void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
100                                           MachineBasicBlock::iterator MI,
101                                           unsigned DestReg, int FrameIdx,
102                                           const TargetRegisterClass *RC) const{
103  unsigned Opc;
104  if (RC == &X86::GR64RegClass) {
105    Opc = X86::MOV64rm;
106  } else if (RC == &X86::GR32RegClass) {
107    Opc = X86::MOV32rm;
108  } else if (RC == &X86::GR16RegClass) {
109    Opc = X86::MOV16rm;
110  } else if (RC == &X86::GR8RegClass) {
111    Opc = X86::MOV8rm;
112  } else if (RC == &X86::GR32_RegClass) {
113    Opc = X86::MOV32_rm;
114  } else if (RC == &X86::GR16_RegClass) {
115    Opc = X86::MOV16_rm;
116  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
117    Opc = X86::FpLD64m;
118  } else if (RC == &X86::FR32RegClass) {
119    Opc = X86::MOVSSrm;
120  } else if (RC == &X86::FR64RegClass) {
121    Opc = X86::MOVSDrm;
122  } else if (RC == &X86::VR128RegClass) {
123    Opc = X86::MOVAPSrm;
124  } else {
125    assert(0 && "Unknown regclass");
126    abort();
127  }
128  addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
129}
130
131void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
132                                   MachineBasicBlock::iterator MI,
133                                   unsigned DestReg, unsigned SrcReg,
134                                   const TargetRegisterClass *RC) const {
135  unsigned Opc;
136  if (RC == &X86::GR64RegClass) {
137    Opc = X86::MOV64rr;
138  } else if (RC == &X86::GR32RegClass) {
139    Opc = X86::MOV32rr;
140  } else if (RC == &X86::GR16RegClass) {
141    Opc = X86::MOV16rr;
142  } else if (RC == &X86::GR8RegClass) {
143    Opc = X86::MOV8rr;
144  } else if (RC == &X86::GR32_RegClass) {
145    Opc = X86::MOV32_rr;
146  } else if (RC == &X86::GR16_RegClass) {
147    Opc = X86::MOV16_rr;
148  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
149    Opc = X86::FpMOV;
150  } else if (RC == &X86::FR32RegClass) {
151    Opc = X86::FsMOVAPSrr;
152  } else if (RC == &X86::FR64RegClass) {
153    Opc = X86::FsMOVAPDrr;
154  } else if (RC == &X86::VR128RegClass) {
155    Opc = X86::MOVAPSrr;
156  } else {
157    assert(0 && "Unknown regclass");
158    abort();
159  }
160  BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
161}
162
163static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
164                                     MachineInstr *MI,
165                                     const TargetInstrInfo &TII) {
166  unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
167  // Create the base instruction with the memory operand as the first part.
168  MachineInstrBuilder MIB = addFrameReference(BuildMI(TII.get(Opcode)),
169                                              FrameIndex);
170
171  // Loop over the rest of the ri operands, converting them over.
172  for (unsigned i = 0; i != NumOps; ++i) {
173    MachineOperand &MO = MI->getOperand(i+2);
174    if (MO.isReg())
175      MIB = MIB.addReg(MO.getReg(), false, MO.isImplicit());
176    else if (MO.isImm())
177      MIB = MIB.addImm(MO.getImm());
178    else if (MO.isGlobalAddress())
179      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
180    else if (MO.isJumpTableIndex())
181      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
182    else if (MO.isExternalSymbol())
183      MIB = MIB.addExternalSymbol(MO.getSymbolName());
184    else
185      assert(0 && "Unknown operand type!");
186  }
187  return MIB;
188}
189
190static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
191                              unsigned FrameIndex, MachineInstr *MI,
192                              const TargetInstrInfo &TII) {
193  MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
194
195  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
196    MachineOperand &MO = MI->getOperand(i);
197    if (i == OpNo) {
198      assert(MO.isReg() && "Expected to fold into reg operand!");
199      MIB = addFrameReference(MIB, FrameIndex);
200    } else if (MO.isReg())
201      MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
202    else if (MO.isImm())
203      MIB = MIB.addImm(MO.getImm());
204    else if (MO.isGlobalAddress())
205      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
206    else if (MO.isJumpTableIndex())
207      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
208    else if (MO.isExternalSymbol())
209      MIB = MIB.addExternalSymbol(MO.getSymbolName());
210    else
211      assert(0 && "Unknown operand for FuseInst!");
212  }
213  return MIB;
214}
215
216static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII,
217                                unsigned Opcode, unsigned FrameIndex,
218                                MachineInstr *MI) {
219  return addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex).addImm(0);
220}
221
222
223//===----------------------------------------------------------------------===//
224// Efficient Lookup Table Support
225//===----------------------------------------------------------------------===//
226
227namespace {
228  /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
229  ///
230  struct TableEntry {
231    unsigned from;                      // Original opcode.
232    unsigned to;                        // New opcode.
233
234    // less operators used by STL search.
235    bool operator<(const TableEntry &TE) const { return from < TE.from; }
236    friend bool operator<(const TableEntry &TE, unsigned V) {
237      return TE.from < V;
238    }
239    friend bool operator<(unsigned V, const TableEntry &TE) {
240      return V < TE.from;
241    }
242  };
243}
244
245/// TableIsSorted - Return true if the table is in 'from' opcode order.
246///
247static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
248  for (unsigned i = 1; i != NumEntries; ++i)
249    if (!(Table[i-1] < Table[i])) {
250      cerr << "Entries out of order " << Table[i-1].from
251           << " " << Table[i].from << "\n";
252      return false;
253    }
254  return true;
255}
256
257/// TableLookup - Return the table entry matching the specified opcode.
258/// Otherwise return NULL.
259static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
260                                unsigned Opcode) {
261  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
262  if (I != Table+N && I->from == Opcode)
263    return I;
264  return NULL;
265}
266
267#define ARRAY_SIZE(TABLE)  \
268   (sizeof(TABLE)/sizeof(TABLE[0]))
269
270#ifdef NDEBUG
271#define ASSERT_SORTED(TABLE)
272#else
273#define ASSERT_SORTED(TABLE)                                              \
274  { static bool TABLE##Checked = false;                                   \
275    if (!TABLE##Checked) {                                                \
276       assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) &&                  \
277              "All lookup tables must be sorted for efficient access!");  \
278       TABLE##Checked = true;                                             \
279    }                                                                     \
280  }
281#endif
282
283
284MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
285                                                 unsigned i,
286                                                 int FrameIndex) const {
287  // Check switch flag
288  if (NoFusing) return NULL;
289
290  // Table (and size) to search
291  const TableEntry *OpcodeTablePtr = NULL;
292  unsigned OpcodeTableSize = 0;
293  bool isTwoAddrFold = false;
294  unsigned NumOps = TII.getNumOperands(MI->getOpcode());
295  bool isTwoAddr = NumOps > 1 &&
296    MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
297
298  MachineInstr *NewMI = NULL;
299  // Folding a memory location into the two-address part of a two-address
300  // instruction is different than folding it other places.  It requires
301  // replacing the *two* registers with the memory location.
302  if (isTwoAddr && NumOps >= 2 && i < 2 &&
303      MI->getOperand(0).isReg() &&
304      MI->getOperand(1).isReg() &&
305      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
306    static const TableEntry OpcodeTable[] = {
307      { X86::ADC32ri,     X86::ADC32mi },
308      { X86::ADC32ri8,    X86::ADC32mi8 },
309      { X86::ADC32rr,     X86::ADC32mr },
310      { X86::ADC64ri32,   X86::ADC64mi32 },
311      { X86::ADC64ri8,    X86::ADC64mi8 },
312      { X86::ADC64rr,     X86::ADC64mr },
313      { X86::ADD16ri,     X86::ADD16mi },
314      { X86::ADD16ri8,    X86::ADD16mi8 },
315      { X86::ADD16rr,     X86::ADD16mr },
316      { X86::ADD32ri,     X86::ADD32mi },
317      { X86::ADD32ri8,    X86::ADD32mi8 },
318      { X86::ADD32rr,     X86::ADD32mr },
319      { X86::ADD64ri32,   X86::ADD64mi32 },
320      { X86::ADD64ri8,    X86::ADD64mi8 },
321      { X86::ADD64rr,     X86::ADD64mr },
322      { X86::ADD8ri,      X86::ADD8mi },
323      { X86::ADD8rr,      X86::ADD8mr },
324      { X86::AND16ri,     X86::AND16mi },
325      { X86::AND16ri8,    X86::AND16mi8 },
326      { X86::AND16rr,     X86::AND16mr },
327      { X86::AND32ri,     X86::AND32mi },
328      { X86::AND32ri8,    X86::AND32mi8 },
329      { X86::AND32rr,     X86::AND32mr },
330      { X86::AND64ri32,   X86::AND64mi32 },
331      { X86::AND64ri8,    X86::AND64mi8 },
332      { X86::AND64rr,     X86::AND64mr },
333      { X86::AND8ri,      X86::AND8mi },
334      { X86::AND8rr,      X86::AND8mr },
335      { X86::DEC16r,      X86::DEC16m },
336      { X86::DEC32r,      X86::DEC32m },
337      { X86::DEC64_16r,   X86::DEC16m },
338      { X86::DEC64_32r,   X86::DEC32m },
339      { X86::DEC64r,      X86::DEC64m },
340      { X86::DEC8r,       X86::DEC8m },
341      { X86::INC16r,      X86::INC16m },
342      { X86::INC32r,      X86::INC32m },
343      { X86::INC64_16r,   X86::INC16m },
344      { X86::INC64_32r,   X86::INC32m },
345      { X86::INC64r,      X86::INC64m },
346      { X86::INC8r,       X86::INC8m },
347      { X86::NEG16r,      X86::NEG16m },
348      { X86::NEG32r,      X86::NEG32m },
349      { X86::NEG64r,      X86::NEG64m },
350      { X86::NEG8r,       X86::NEG8m },
351      { X86::NOT16r,      X86::NOT16m },
352      { X86::NOT32r,      X86::NOT32m },
353      { X86::NOT64r,      X86::NOT64m },
354      { X86::NOT8r,       X86::NOT8m },
355      { X86::OR16ri,      X86::OR16mi },
356      { X86::OR16ri8,     X86::OR16mi8 },
357      { X86::OR16rr,      X86::OR16mr },
358      { X86::OR32ri,      X86::OR32mi },
359      { X86::OR32ri8,     X86::OR32mi8 },
360      { X86::OR32rr,      X86::OR32mr },
361      { X86::OR64ri32,    X86::OR64mi32 },
362      { X86::OR64ri8,     X86::OR64mi8 },
363      { X86::OR64rr,      X86::OR64mr },
364      { X86::OR8ri,       X86::OR8mi },
365      { X86::OR8rr,       X86::OR8mr },
366      { X86::ROL16r1,     X86::ROL16m1 },
367      { X86::ROL16rCL,    X86::ROL16mCL },
368      { X86::ROL16ri,     X86::ROL16mi },
369      { X86::ROL32r1,     X86::ROL32m1 },
370      { X86::ROL32rCL,    X86::ROL32mCL },
371      { X86::ROL32ri,     X86::ROL32mi },
372      { X86::ROL64r1,     X86::ROL64m1 },
373      { X86::ROL64rCL,    X86::ROL64mCL },
374      { X86::ROL64ri,     X86::ROL64mi },
375      { X86::ROL8r1,      X86::ROL8m1 },
376      { X86::ROL8rCL,     X86::ROL8mCL },
377      { X86::ROL8ri,      X86::ROL8mi },
378      { X86::ROR16r1,     X86::ROR16m1 },
379      { X86::ROR16rCL,    X86::ROR16mCL },
380      { X86::ROR16ri,     X86::ROR16mi },
381      { X86::ROR32r1,     X86::ROR32m1 },
382      { X86::ROR32rCL,    X86::ROR32mCL },
383      { X86::ROR32ri,     X86::ROR32mi },
384      { X86::ROR64r1,     X86::ROR64m1 },
385      { X86::ROR64rCL,    X86::ROR64mCL },
386      { X86::ROR64ri,     X86::ROR64mi },
387      { X86::ROR8r1,      X86::ROR8m1 },
388      { X86::ROR8rCL,     X86::ROR8mCL },
389      { X86::ROR8ri,      X86::ROR8mi },
390      { X86::SAR16r1,     X86::SAR16m1 },
391      { X86::SAR16rCL,    X86::SAR16mCL },
392      { X86::SAR16ri,     X86::SAR16mi },
393      { X86::SAR32r1,     X86::SAR32m1 },
394      { X86::SAR32rCL,    X86::SAR32mCL },
395      { X86::SAR32ri,     X86::SAR32mi },
396      { X86::SAR64r1,     X86::SAR64m1 },
397      { X86::SAR64rCL,    X86::SAR64mCL },
398      { X86::SAR64ri,     X86::SAR64mi },
399      { X86::SAR8r1,      X86::SAR8m1 },
400      { X86::SAR8rCL,     X86::SAR8mCL },
401      { X86::SAR8ri,      X86::SAR8mi },
402      { X86::SBB32ri,     X86::SBB32mi },
403      { X86::SBB32ri8,    X86::SBB32mi8 },
404      { X86::SBB32rr,     X86::SBB32mr },
405      { X86::SBB64ri32,   X86::SBB64mi32 },
406      { X86::SBB64ri8,    X86::SBB64mi8 },
407      { X86::SBB64rr,     X86::SBB64mr },
408      { X86::SHL16r1,     X86::SHL16m1 },
409      { X86::SHL16rCL,    X86::SHL16mCL },
410      { X86::SHL16ri,     X86::SHL16mi },
411      { X86::SHL32r1,     X86::SHL32m1 },
412      { X86::SHL32rCL,    X86::SHL32mCL },
413      { X86::SHL32ri,     X86::SHL32mi },
414      { X86::SHL64r1,     X86::SHL64m1 },
415      { X86::SHL64rCL,    X86::SHL64mCL },
416      { X86::SHL64ri,     X86::SHL64mi },
417      { X86::SHL8r1,      X86::SHL8m1 },
418      { X86::SHL8rCL,     X86::SHL8mCL },
419      { X86::SHL8ri,      X86::SHL8mi },
420      { X86::SHLD16rrCL,  X86::SHLD16mrCL },
421      { X86::SHLD16rri8,  X86::SHLD16mri8 },
422      { X86::SHLD32rrCL,  X86::SHLD32mrCL },
423      { X86::SHLD32rri8,  X86::SHLD32mri8 },
424      { X86::SHLD64rrCL,  X86::SHLD64mrCL },
425      { X86::SHLD64rri8,  X86::SHLD64mri8 },
426      { X86::SHR16r1,     X86::SHR16m1 },
427      { X86::SHR16rCL,    X86::SHR16mCL },
428      { X86::SHR16ri,     X86::SHR16mi },
429      { X86::SHR32r1,     X86::SHR32m1 },
430      { X86::SHR32rCL,    X86::SHR32mCL },
431      { X86::SHR32ri,     X86::SHR32mi },
432      { X86::SHR64r1,     X86::SHR64m1 },
433      { X86::SHR64rCL,    X86::SHR64mCL },
434      { X86::SHR64ri,     X86::SHR64mi },
435      { X86::SHR8r1,      X86::SHR8m1 },
436      { X86::SHR8rCL,     X86::SHR8mCL },
437      { X86::SHR8ri,      X86::SHR8mi },
438      { X86::SHRD16rrCL,  X86::SHRD16mrCL },
439      { X86::SHRD16rri8,  X86::SHRD16mri8 },
440      { X86::SHRD32rrCL,  X86::SHRD32mrCL },
441      { X86::SHRD32rri8,  X86::SHRD32mri8 },
442      { X86::SHRD64rrCL,  X86::SHRD64mrCL },
443      { X86::SHRD64rri8,  X86::SHRD64mri8 },
444      { X86::SUB16ri,     X86::SUB16mi },
445      { X86::SUB16ri8,    X86::SUB16mi8 },
446      { X86::SUB16rr,     X86::SUB16mr },
447      { X86::SUB32ri,     X86::SUB32mi },
448      { X86::SUB32ri8,    X86::SUB32mi8 },
449      { X86::SUB32rr,     X86::SUB32mr },
450      { X86::SUB64ri32,   X86::SUB64mi32 },
451      { X86::SUB64ri8,    X86::SUB64mi8 },
452      { X86::SUB64rr,     X86::SUB64mr },
453      { X86::SUB8ri,      X86::SUB8mi },
454      { X86::SUB8rr,      X86::SUB8mr },
455      { X86::XOR16ri,     X86::XOR16mi },
456      { X86::XOR16ri8,    X86::XOR16mi8 },
457      { X86::XOR16rr,     X86::XOR16mr },
458      { X86::XOR32ri,     X86::XOR32mi },
459      { X86::XOR32ri8,    X86::XOR32mi8 },
460      { X86::XOR32rr,     X86::XOR32mr },
461      { X86::XOR64ri32,   X86::XOR64mi32 },
462      { X86::XOR64ri8,    X86::XOR64mi8 },
463      { X86::XOR64rr,     X86::XOR64mr },
464      { X86::XOR8ri,      X86::XOR8mi },
465      { X86::XOR8rr,      X86::XOR8mr }
466    };
467    ASSERT_SORTED(OpcodeTable);
468    OpcodeTablePtr = OpcodeTable;
469    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
470    isTwoAddrFold = true;
471  } else if (i == 0) { // If operand 0
472    if (MI->getOpcode() == X86::MOV16r0)
473      NewMI = MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI);
474    else if (MI->getOpcode() == X86::MOV32r0)
475      NewMI = MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI);
476    else if (MI->getOpcode() == X86::MOV64r0)
477      NewMI = MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI);
478    else if (MI->getOpcode() == X86::MOV8r0)
479      NewMI = MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI);
480    if (NewMI) {
481      NewMI->copyKillDeadInfo(MI);
482      return NewMI;
483    }
484
485    static const TableEntry OpcodeTable[] = {
486      { X86::CMP16ri,     X86::CMP16mi },
487      { X86::CMP16ri8,    X86::CMP16mi8 },
488      { X86::CMP32ri,     X86::CMP32mi },
489      { X86::CMP32ri8,    X86::CMP32mi8 },
490      { X86::CMP8ri,      X86::CMP8mi },
491      { X86::DIV16r,      X86::DIV16m },
492      { X86::DIV32r,      X86::DIV32m },
493      { X86::DIV64r,      X86::DIV64m },
494      { X86::DIV8r,       X86::DIV8m },
495      { X86::FsMOVAPDrr,  X86::MOVSDmr },
496      { X86::FsMOVAPSrr,  X86::MOVSSmr },
497      { X86::IDIV16r,     X86::IDIV16m },
498      { X86::IDIV32r,     X86::IDIV32m },
499      { X86::IDIV64r,     X86::IDIV64m },
500      { X86::IDIV8r,      X86::IDIV8m },
501      { X86::IMUL16r,     X86::IMUL16m },
502      { X86::IMUL32r,     X86::IMUL32m },
503      { X86::IMUL64r,     X86::IMUL64m },
504      { X86::IMUL8r,      X86::IMUL8m },
505      { X86::MOV16ri,     X86::MOV16mi },
506      { X86::MOV16rr,     X86::MOV16mr },
507      { X86::MOV32ri,     X86::MOV32mi },
508      { X86::MOV32rr,     X86::MOV32mr },
509      { X86::MOV64ri32,   X86::MOV64mi32 },
510      { X86::MOV64rr,     X86::MOV64mr },
511      { X86::MOV8ri,      X86::MOV8mi },
512      { X86::MOV8rr,      X86::MOV8mr },
513      { X86::MOVAPDrr,    X86::MOVAPDmr },
514      { X86::MOVAPSrr,    X86::MOVAPSmr },
515      { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
516      { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
517      { X86::MOVPS2SSrr,  X86::MOVPS2SSmr },
518      { X86::MOVSDrr,     X86::MOVSDmr },
519      { X86::MOVSDto64rr, X86::MOVSDto64mr },
520      { X86::MOVSS2DIrr,  X86::MOVSS2DImr },
521      { X86::MOVSSrr,     X86::MOVSSmr },
522      { X86::MOVUPDrr,    X86::MOVUPDmr },
523      { X86::MOVUPSrr,    X86::MOVUPSmr },
524      { X86::MUL16r,      X86::MUL16m },
525      { X86::MUL32r,      X86::MUL32m },
526      { X86::MUL64r,      X86::MUL64m },
527      { X86::MUL8r,       X86::MUL8m },
528      { X86::SETAEr,      X86::SETAEm },
529      { X86::SETAr,       X86::SETAm },
530      { X86::SETBEr,      X86::SETBEm },
531      { X86::SETBr,       X86::SETBm },
532      { X86::SETEr,       X86::SETEm },
533      { X86::SETGEr,      X86::SETGEm },
534      { X86::SETGr,       X86::SETGm },
535      { X86::SETLEr,      X86::SETLEm },
536      { X86::SETLr,       X86::SETLm },
537      { X86::SETNEr,      X86::SETNEm },
538      { X86::SETNPr,      X86::SETNPm },
539      { X86::SETNSr,      X86::SETNSm },
540      { X86::SETPr,       X86::SETPm },
541      { X86::SETSr,       X86::SETSm },
542      { X86::TEST16ri,    X86::TEST16mi },
543      { X86::TEST32ri,    X86::TEST32mi },
544      { X86::TEST64ri32,  X86::TEST64mi32 },
545      { X86::TEST8ri,     X86::TEST8mi },
546      { X86::XCHG16rr,    X86::XCHG16mr },
547      { X86::XCHG32rr,    X86::XCHG32mr },
548      { X86::XCHG64rr,    X86::XCHG64mr },
549      { X86::XCHG8rr,     X86::XCHG8mr }
550    };
551    ASSERT_SORTED(OpcodeTable);
552    OpcodeTablePtr = OpcodeTable;
553    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
554  } else if (i == 1) {
555    static const TableEntry OpcodeTable[] = {
556      { X86::CMP16rr,         X86::CMP16rm },
557      { X86::CMP32rr,         X86::CMP32rm },
558      { X86::CMP64ri32,       X86::CMP64mi32 },
559      { X86::CMP64ri8,        X86::CMP64mi8 },
560      { X86::CMP64rr,         X86::CMP64rm },
561      { X86::CMP8rr,          X86::CMP8rm },
562      { X86::CMPPDrri,        X86::CMPPDrmi },
563      { X86::CMPPSrri,        X86::CMPPSrmi },
564      { X86::CMPSDrr,         X86::CMPSDrm },
565      { X86::CMPSSrr,         X86::CMPSSrm },
566      { X86::CVTSD2SSrr,      X86::CVTSD2SSrm },
567      { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm },
568      { X86::CVTSI2SDrr,      X86::CVTSI2SDrm },
569      { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm },
570      { X86::CVTSI2SSrr,      X86::CVTSI2SSrm },
571      { X86::CVTSS2SDrr,      X86::CVTSS2SDrm },
572      { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm },
573      { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm },
574      { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm },
575      { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm },
576      { X86::FsMOVAPDrr,      X86::MOVSDrm },
577      { X86::FsMOVAPSrr,      X86::MOVSSrm },
578      { X86::IMUL16rri,       X86::IMUL16rmi },
579      { X86::IMUL16rri8,      X86::IMUL16rmi8 },
580      { X86::IMUL32rri,       X86::IMUL32rmi },
581      { X86::IMUL32rri8,      X86::IMUL32rmi8 },
582      { X86::IMUL64rr,        X86::IMUL64rm },
583      { X86::IMUL64rri32,     X86::IMUL64rmi32 },
584      { X86::IMUL64rri8,      X86::IMUL64rmi8 },
585      { X86::Int_CMPSDrr,     X86::Int_CMPSDrm },
586      { X86::Int_CMPSSrr,     X86::Int_CMPSSrm },
587      { X86::Int_COMISDrr,    X86::Int_COMISDrm },
588      { X86::Int_COMISSrr,    X86::Int_COMISSrm },
589      { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm },
590      { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm },
591      { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm },
592      { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm },
593      { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm },
594      { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm },
595      { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
596      { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm },
597      { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm },
598      { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
599      { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm },
600      { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
601      { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm },
602      { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm },
603      { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
604      { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm },
605      { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
606      { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
607      { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
608      { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
609      { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
610      { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
611      { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm },
612      { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm },
613      { X86::MOV16rr,         X86::MOV16rm },
614      { X86::MOV32rr,         X86::MOV32rm },
615      { X86::MOV64rr,         X86::MOV64rm },
616      { X86::MOV64toPQIrr,    X86::MOV64toPQIrm },
617      { X86::MOV64toSDrr,     X86::MOV64toSDrm },
618      { X86::MOV8rr,          X86::MOV8rm },
619      { X86::MOVAPDrr,        X86::MOVAPDrm },
620      { X86::MOVAPSrr,        X86::MOVAPSrm },
621      { X86::MOVDDUPrr,       X86::MOVDDUPrm },
622      { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm },
623      { X86::MOVDI2SSrr,      X86::MOVDI2SSrm },
624      { X86::MOVSD2PDrr,      X86::MOVSD2PDrm },
625      { X86::MOVSDrr,         X86::MOVSDrm },
626      { X86::MOVSHDUPrr,      X86::MOVSHDUPrm },
627      { X86::MOVSLDUPrr,      X86::MOVSLDUPrm },
628      { X86::MOVSS2PSrr,      X86::MOVSS2PSrm },
629      { X86::MOVSSrr,         X86::MOVSSrm },
630      { X86::MOVSX16rr8,      X86::MOVSX16rm8 },
631      { X86::MOVSX32rr16,     X86::MOVSX32rm16 },
632      { X86::MOVSX32rr8,      X86::MOVSX32rm8 },
633      { X86::MOVSX64rr16,     X86::MOVSX64rm16 },
634      { X86::MOVSX64rr32,     X86::MOVSX64rm32 },
635      { X86::MOVSX64rr8,      X86::MOVSX64rm8 },
636      { X86::MOVUPDrr,        X86::MOVUPDrm },
637      { X86::MOVUPSrr,        X86::MOVUPSrm },
638      { X86::MOVZX16rr8,      X86::MOVZX16rm8 },
639      { X86::MOVZX32rr16,     X86::MOVZX32rm16 },
640      { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
641      { X86::MOVZX64rr16,     X86::MOVZX64rm16 },
642      { X86::MOVZX64rr8,      X86::MOVZX64rm8 },
643      { X86::PSHUFDri,        X86::PSHUFDmi },
644      { X86::PSHUFHWri,       X86::PSHUFHWmi },
645      { X86::PSHUFLWri,       X86::PSHUFLWmi },
646      { X86::PsMOVZX64rr32,   X86::PsMOVZX64rm32 },
647      { X86::TEST16rr,        X86::TEST16rm },
648      { X86::TEST32rr,        X86::TEST32rm },
649      { X86::TEST64rr,        X86::TEST64rm },
650      { X86::TEST8rr,         X86::TEST8rm },
651      // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
652      { X86::UCOMISDrr,       X86::UCOMISDrm },
653      { X86::UCOMISSrr,       X86::UCOMISSrm },
654      { X86::XCHG16rr,        X86::XCHG16rm },
655      { X86::XCHG32rr,        X86::XCHG32rm },
656      { X86::XCHG64rr,        X86::XCHG64rm },
657      { X86::XCHG8rr,         X86::XCHG8rm }
658    };
659    ASSERT_SORTED(OpcodeTable);
660    OpcodeTablePtr = OpcodeTable;
661    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
662  } else if (i == 2) {
663    static const TableEntry OpcodeTable[] = {
664      { X86::ADC32rr,         X86::ADC32rm },
665      { X86::ADC64rr,         X86::ADC64rm },
666      { X86::ADD16rr,         X86::ADD16rm },
667      { X86::ADD32rr,         X86::ADD32rm },
668      { X86::ADD64rr,         X86::ADD64rm },
669      { X86::ADD8rr,          X86::ADD8rm },
670      { X86::ADDPDrr,         X86::ADDPDrm },
671      { X86::ADDPSrr,         X86::ADDPSrm },
672      { X86::ADDSDrr,         X86::ADDSDrm },
673      { X86::ADDSSrr,         X86::ADDSSrm },
674      { X86::ADDSUBPDrr,      X86::ADDSUBPDrm },
675      { X86::ADDSUBPSrr,      X86::ADDSUBPSrm },
676      { X86::AND16rr,         X86::AND16rm },
677      { X86::AND32rr,         X86::AND32rm },
678      { X86::AND64rr,         X86::AND64rm },
679      { X86::AND8rr,          X86::AND8rm },
680      { X86::ANDNPDrr,        X86::ANDNPDrm },
681      { X86::ANDNPSrr,        X86::ANDNPSrm },
682      { X86::ANDPDrr,         X86::ANDPDrm },
683      { X86::ANDPSrr,         X86::ANDPSrm },
684      { X86::CMOVA16rr,       X86::CMOVA16rm },
685      { X86::CMOVA32rr,       X86::CMOVA32rm },
686      { X86::CMOVA64rr,       X86::CMOVA64rm },
687      { X86::CMOVAE16rr,      X86::CMOVAE16rm },
688      { X86::CMOVAE32rr,      X86::CMOVAE32rm },
689      { X86::CMOVAE64rr,      X86::CMOVAE64rm },
690      { X86::CMOVB16rr,       X86::CMOVB16rm },
691      { X86::CMOVB32rr,       X86::CMOVB32rm },
692      { X86::CMOVB64rr,       X86::CMOVB64rm },
693      { X86::CMOVBE16rr,      X86::CMOVBE16rm },
694      { X86::CMOVBE32rr,      X86::CMOVBE32rm },
695      { X86::CMOVBE64rr,      X86::CMOVBE64rm },
696      { X86::CMOVE16rr,       X86::CMOVE16rm },
697      { X86::CMOVE32rr,       X86::CMOVE32rm },
698      { X86::CMOVE64rr,       X86::CMOVE64rm },
699      { X86::CMOVG16rr,       X86::CMOVG16rm },
700      { X86::CMOVG32rr,       X86::CMOVG32rm },
701      { X86::CMOVG64rr,       X86::CMOVG64rm },
702      { X86::CMOVGE16rr,      X86::CMOVGE16rm },
703      { X86::CMOVGE32rr,      X86::CMOVGE32rm },
704      { X86::CMOVGE64rr,      X86::CMOVGE64rm },
705      { X86::CMOVL16rr,       X86::CMOVL16rm },
706      { X86::CMOVL32rr,       X86::CMOVL32rm },
707      { X86::CMOVL64rr,       X86::CMOVL64rm },
708      { X86::CMOVLE16rr,      X86::CMOVLE16rm },
709      { X86::CMOVLE32rr,      X86::CMOVLE32rm },
710      { X86::CMOVLE64rr,      X86::CMOVLE64rm },
711      { X86::CMOVNE16rr,      X86::CMOVNE16rm },
712      { X86::CMOVNE32rr,      X86::CMOVNE32rm },
713      { X86::CMOVNE64rr,      X86::CMOVNE64rm },
714      { X86::CMOVNP16rr,      X86::CMOVNP16rm },
715      { X86::CMOVNP32rr,      X86::CMOVNP32rm },
716      { X86::CMOVNP64rr,      X86::CMOVNP64rm },
717      { X86::CMOVNS16rr,      X86::CMOVNS16rm },
718      { X86::CMOVNS32rr,      X86::CMOVNS32rm },
719      { X86::CMOVNS64rr,      X86::CMOVNS64rm },
720      { X86::CMOVP16rr,       X86::CMOVP16rm },
721      { X86::CMOVP32rr,       X86::CMOVP32rm },
722      { X86::CMOVP64rr,       X86::CMOVP64rm },
723      { X86::CMOVS16rr,       X86::CMOVS16rm },
724      { X86::CMOVS32rr,       X86::CMOVS32rm },
725      { X86::CMOVS64rr,       X86::CMOVS64rm },
726      { X86::DIVPDrr,         X86::DIVPDrm },
727      { X86::DIVPSrr,         X86::DIVPSrm },
728      { X86::DIVSDrr,         X86::DIVSDrm },
729      { X86::DIVSSrr,         X86::DIVSSrm },
730      { X86::HADDPDrr,        X86::HADDPDrm },
731      { X86::HADDPSrr,        X86::HADDPSrm },
732      { X86::HSUBPDrr,        X86::HSUBPDrm },
733      { X86::HSUBPSrr,        X86::HSUBPSrm },
734      { X86::IMUL16rr,        X86::IMUL16rm },
735      { X86::IMUL32rr,        X86::IMUL32rm },
736      { X86::MAXPDrr,         X86::MAXPDrm },
737      { X86::MAXPSrr,         X86::MAXPSrm },
738      { X86::MINPDrr,         X86::MINPDrm },
739      { X86::MINPSrr,         X86::MINPSrm },
740      { X86::MULPDrr,         X86::MULPDrm },
741      { X86::MULPSrr,         X86::MULPSrm },
742      { X86::MULSDrr,         X86::MULSDrm },
743      { X86::MULSSrr,         X86::MULSSrm },
744      { X86::OR16rr,          X86::OR16rm },
745      { X86::OR32rr,          X86::OR32rm },
746      { X86::OR64rr,          X86::OR64rm },
747      { X86::OR8rr,           X86::OR8rm },
748      { X86::ORPDrr,          X86::ORPDrm },
749      { X86::ORPSrr,          X86::ORPSrm },
750      { X86::PACKSSDWrr,      X86::PACKSSDWrm },
751      { X86::PACKSSWBrr,      X86::PACKSSWBrm },
752      { X86::PACKUSWBrr,      X86::PACKUSWBrm },
753      { X86::PADDBrr,         X86::PADDBrm },
754      { X86::PADDDrr,         X86::PADDDrm },
755      { X86::PADDSBrr,        X86::PADDSBrm },
756      { X86::PADDSWrr,        X86::PADDSWrm },
757      { X86::PADDWrr,         X86::PADDWrm },
758      { X86::PANDNrr,         X86::PANDNrm },
759      { X86::PANDrr,          X86::PANDrm },
760      { X86::PAVGBrr,         X86::PAVGBrm },
761      { X86::PAVGWrr,         X86::PAVGWrm },
762      { X86::PCMPEQBrr,       X86::PCMPEQBrm },
763      { X86::PCMPEQDrr,       X86::PCMPEQDrm },
764      { X86::PCMPEQWrr,       X86::PCMPEQWrm },
765      { X86::PCMPGTBrr,       X86::PCMPGTBrm },
766      { X86::PCMPGTDrr,       X86::PCMPGTDrm },
767      { X86::PCMPGTWrr,       X86::PCMPGTWrm },
768      { X86::PINSRWrri,       X86::PINSRWrmi },
769      { X86::PMADDWDrr,       X86::PMADDWDrm },
770      { X86::PMAXSWrr,        X86::PMAXSWrm },
771      { X86::PMAXUBrr,        X86::PMAXUBrm },
772      { X86::PMINSWrr,        X86::PMINSWrm },
773      { X86::PMINUBrr,        X86::PMINUBrm },
774      { X86::PMULHUWrr,       X86::PMULHUWrm },
775      { X86::PMULHWrr,        X86::PMULHWrm },
776      { X86::PMULLWrr,        X86::PMULLWrm },
777      { X86::PMULUDQrr,       X86::PMULUDQrm },
778      { X86::PORrr,           X86::PORrm },
779      { X86::PSADBWrr,        X86::PSADBWrm },
780      { X86::PSLLDrr,         X86::PSLLDrm },
781      { X86::PSLLQrr,         X86::PSLLQrm },
782      { X86::PSLLWrr,         X86::PSLLWrm },
783      { X86::PSRADrr,         X86::PSRADrm },
784      { X86::PSRAWrr,         X86::PSRAWrm },
785      { X86::PSRLDrr,         X86::PSRLDrm },
786      { X86::PSRLQrr,         X86::PSRLQrm },
787      { X86::PSRLWrr,         X86::PSRLWrm },
788      { X86::PSUBBrr,         X86::PSUBBrm },
789      { X86::PSUBDrr,         X86::PSUBDrm },
790      { X86::PSUBSBrr,        X86::PSUBSBrm },
791      { X86::PSUBSWrr,        X86::PSUBSWrm },
792      { X86::PSUBWrr,         X86::PSUBWrm },
793      { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm },
794      { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm },
795      { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm },
796      { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm },
797      { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm },
798      { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm },
799      { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm },
800      { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm },
801      { X86::PXORrr,          X86::PXORrm },
802      { X86::RCPPSr,          X86::RCPPSm },
803      { X86::RSQRTPSr,        X86::RSQRTPSm },
804      { X86::SBB32rr,         X86::SBB32rm },
805      { X86::SBB64rr,         X86::SBB64rm },
806      { X86::SHUFPDrri,       X86::SHUFPDrmi },
807      { X86::SHUFPSrri,       X86::SHUFPSrmi },
808      { X86::SQRTPDr,         X86::SQRTPDm },
809      { X86::SQRTPSr,         X86::SQRTPSm },
810      { X86::SQRTSDr,         X86::SQRTSDm },
811      { X86::SQRTSSr,         X86::SQRTSSm },
812      { X86::SUB16rr,         X86::SUB16rm },
813      { X86::SUB32rr,         X86::SUB32rm },
814      { X86::SUB64rr,         X86::SUB64rm },
815      { X86::SUB8rr,          X86::SUB8rm },
816      { X86::SUBPDrr,         X86::SUBPDrm },
817      { X86::SUBPSrr,         X86::SUBPSrm },
818      { X86::SUBSDrr,         X86::SUBSDrm },
819      { X86::SUBSSrr,         X86::SUBSSrm },
820      // FIXME: TEST*rr -> swapped operand of TEST*mr.
821      { X86::UNPCKHPDrr,      X86::UNPCKHPDrm },
822      { X86::UNPCKHPSrr,      X86::UNPCKHPSrm },
823      { X86::UNPCKLPDrr,      X86::UNPCKLPDrm },
824      { X86::UNPCKLPSrr,      X86::UNPCKLPSrm },
825      { X86::XOR16rr,         X86::XOR16rm },
826      { X86::XOR32rr,         X86::XOR32rm },
827      { X86::XOR64rr,         X86::XOR64rm },
828      { X86::XOR8rr,          X86::XOR8rm },
829      { X86::XORPDrr,         X86::XORPDrm },
830      { X86::XORPSrr,         X86::XORPSrm }
831    };
832    ASSERT_SORTED(OpcodeTable);
833    OpcodeTablePtr = OpcodeTable;
834    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
835  }
836
837  // If table selected...
838  if (OpcodeTablePtr) {
839    // Find the Opcode to fuse
840    unsigned fromOpcode = MI->getOpcode();
841    // Lookup fromOpcode in table
842    if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
843                                              fromOpcode)) {
844      if (isTwoAddrFold)
845        NewMI = FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
846      else
847        NewMI = FuseInst(Entry->to, i, FrameIndex, MI, TII);
848      NewMI->copyKillDeadInfo(MI);
849      return NewMI;
850    }
851  }
852
853  // No fusion
854  if (PrintFailedFusing)
855    cerr << "We failed to fuse ("
856         << ((i == 1) ? "r" : "s") << "): " << *MI;
857  return NULL;
858}
859
860
861const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
862  static const unsigned CalleeSavedRegs32Bit[] = {
863    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
864  };
865  static const unsigned CalleeSavedRegs64Bit[] = {
866    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
867  };
868
869  return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
870}
871
872const TargetRegisterClass* const*
873X86RegisterInfo::getCalleeSavedRegClasses() const {
874  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
875    &X86::GR32RegClass, &X86::GR32RegClass,
876    &X86::GR32RegClass, &X86::GR32RegClass,  0
877  };
878  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
879    &X86::GR64RegClass, &X86::GR64RegClass,
880    &X86::GR64RegClass, &X86::GR64RegClass,
881    &X86::GR64RegClass, &X86::GR64RegClass, 0
882  };
883
884  return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
885}
886
887BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
888  BitVector Reserved(getNumRegs());
889  Reserved.set(X86::RSP);
890  Reserved.set(X86::ESP);
891  Reserved.set(X86::SP);
892  Reserved.set(X86::SPL);
893  if (hasFP(MF)) {
894    Reserved.set(X86::RBP);
895    Reserved.set(X86::EBP);
896    Reserved.set(X86::BP);
897    Reserved.set(X86::BPL);
898  }
899  return Reserved;
900}
901
902//===----------------------------------------------------------------------===//
903// Stack Frame Processing methods
904//===----------------------------------------------------------------------===//
905
906// hasFP - Return true if the specified function should have a dedicated frame
907// pointer register.  This is true if the function has variable sized allocas or
908// if frame pointer elimination is disabled.
909//
910bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
911  return (NoFramePointerElim ||
912          MF.getFrameInfo()->hasVarSizedObjects() ||
913          MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
914}
915
916void X86RegisterInfo::
917eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
918                              MachineBasicBlock::iterator I) const {
919  if (hasFP(MF)) {
920    // If we have a frame pointer, turn the adjcallstackup instruction into a
921    // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
922    // <amt>'
923    MachineInstr *Old = I;
924    unsigned Amount = Old->getOperand(0).getImmedValue();
925    if (Amount != 0) {
926      // We need to keep the stack aligned properly.  To do this, we round the
927      // amount of space needed for the outgoing arguments up to the next
928      // alignment boundary.
929      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
930      Amount = (Amount+Align-1)/Align*Align;
931
932      MachineInstr *New = 0;
933      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
934        New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
935          .addReg(StackPtr).addImm(Amount);
936      } else {
937        assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
938        // factor out the amount the callee already popped.
939        unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
940        Amount -= CalleeAmt;
941        if (Amount) {
942          unsigned Opc = (Amount < 128) ?
943            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
944            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
945          New = BuildMI(TII.get(Opc),  StackPtr)
946                        .addReg(StackPtr).addImm(Amount);
947        }
948      }
949
950      // Replace the pseudo instruction with a new instruction...
951      if (New) MBB.insert(I, New);
952    }
953  } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
954    // If we are performing frame pointer elimination and if the callee pops
955    // something off the stack pointer, add it back.  We do this until we have
956    // more advanced stack pointer tracking ability.
957    if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
958      unsigned Opc = (CalleeAmt < 128) ?
959        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
960        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
961      MachineInstr *New =
962        BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
963      MBB.insert(I, New);
964    }
965  }
966
967  MBB.erase(I);
968}
969
970void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
971  unsigned i = 0;
972  MachineInstr &MI = *II;
973  MachineFunction &MF = *MI.getParent()->getParent();
974  while (!MI.getOperand(i).isFrameIndex()) {
975    ++i;
976    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
977  }
978
979  int FrameIndex = MI.getOperand(i).getFrameIndex();
980  // This must be part of a four operand memory reference.  Replace the
981  // FrameIndex with base register with EBP.  Add an offset to the offset.
982  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
983
984  // Now add the frame object offset to the offset from EBP.
985  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
986               MI.getOperand(i+3).getImmedValue()+SlotSize;
987
988  if (!hasFP(MF))
989    Offset += MF.getFrameInfo()->getStackSize();
990  else
991    Offset += SlotSize;  // Skip the saved EBP
992
993  MI.getOperand(i+3).ChangeToImmediate(Offset);
994}
995
996void
997X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
998  if (hasFP(MF)) {
999    // Create a frame entry for the EBP register that must be saved.
1000    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,SlotSize * -2);
1001    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
1002           "Slot for EBP register must be last in order to be found!");
1003  }
1004}
1005
1006void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
1007  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
1008  MachineBasicBlock::iterator MBBI = MBB.begin();
1009  MachineFrameInfo *MFI = MF.getFrameInfo();
1010  unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1011  const Function* Fn = MF.getFunction();
1012  const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1013  MachineInstr *MI;
1014  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1015
1016  // Prepare for frame info.
1017  unsigned FrameLabelId = 0;
1018
1019  // Get the number of bytes to allocate from the FrameInfo
1020  unsigned NumBytes = MFI->getStackSize();
1021
1022  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
1023    if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1024      // Function prologue calls _alloca to probe the stack when allocating
1025      // more than 4k bytes in one go. Touching the stack at 4K increments is
1026      // necessary to ensure that the guard pages used by the OS virtual memory
1027      // manager are allocated in correct sequence.
1028      MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1029      MBB.insert(MBBI, MI);
1030      MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1031      MBB.insert(MBBI, MI);
1032    } else {
1033      unsigned Opc = (NumBytes < 128) ?
1034        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1035        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1036      MI= BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
1037      MBB.insert(MBBI, MI);
1038    }
1039  }
1040
1041  if (MMI && MMI->needsFrameInfo()) {
1042    // Mark effective beginning of when frame pointer becomes valid.
1043    FrameLabelId = MMI->NextLabelID();
1044    BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
1045  }
1046
1047  if (hasFP(MF)) {
1048    // Get the offset of the stack slot for the EBP register... which is
1049    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1050    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize;
1051    // Update the frame offset adjustment.
1052    MFI->setOffsetAdjustment(SlotSize-NumBytes);
1053
1054    // Save EBP into the appropriate stack slot...
1055    // mov [ESP-<offset>], EBP
1056    MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::MOV64mr : X86::MOV32mr)),
1057                      StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
1058    MBB.insert(MBBI, MI);
1059
1060    // Update EBP with the new base value...
1061    if (NumBytes == SlotSize)    // mov EBP, ESP
1062      MI = BuildMI(TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr).
1063        addReg(StackPtr);
1064    else                  // lea EBP, [ESP+StackSize]
1065      MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::LEA64r : X86::LEA32r),
1066                                FramePtr), StackPtr, NumBytes-SlotSize);
1067
1068    MBB.insert(MBBI, MI);
1069  }
1070
1071  if (MMI && MMI->needsFrameInfo()) {
1072    std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1073
1074    if (NumBytes) {
1075      // Show update of SP.
1076      MachineLocation SPDst(MachineLocation::VirtualFP);
1077      MachineLocation SPSrc(MachineLocation::VirtualFP, -NumBytes);
1078      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1079    } else {
1080      MachineLocation SP(StackPtr);
1081      Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1082    }
1083
1084    // Add callee saved registers to move list.
1085    const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1086    for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1087      int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1088      unsigned Reg = CSI[I].getReg();
1089      MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1090      MachineLocation CSSrc(Reg);
1091      Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1092    }
1093
1094    // Mark effective beginning of when frame pointer is ready.
1095    unsigned ReadyLabelId = MMI->NextLabelID();
1096    BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
1097
1098    MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
1099    MachineLocation FPSrc(MachineLocation::VirtualFP);
1100    Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1101  }
1102
1103  // If it's main() on Cygwin\Mingw32 we should align stack as well
1104  if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1105      Subtarget->isTargetCygMing()) {
1106    MI= BuildMI(TII.get(X86::AND32ri), X86::ESP)
1107                .addReg(X86::ESP).addImm(-Align);
1108    MBB.insert(MBBI, MI);
1109
1110    // Probe the stack
1111    MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
1112    MBB.insert(MBBI, MI);
1113    MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1114    MBB.insert(MBBI, MI);
1115  }
1116}
1117
1118void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1119                                   MachineBasicBlock &MBB) const {
1120  const MachineFrameInfo *MFI = MF.getFrameInfo();
1121  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1122
1123  switch (MBBI->getOpcode()) {
1124  case X86::RET:
1125  case X86::RETI:
1126  case X86::TAILJMPd:
1127  case X86::TAILJMPr:
1128  case X86::TAILJMPm: break;  // These are ok
1129  default:
1130    assert(0 && "Can only insert epilog into returning blocks");
1131  }
1132
1133  if (hasFP(MF)) {
1134    // mov ESP, EBP
1135    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1136      addReg(FramePtr);
1137
1138    // pop EBP
1139    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1140  } else {
1141    // Get the number of bytes allocated from the FrameInfo...
1142    unsigned NumBytes = MFI->getStackSize();
1143
1144    if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
1145      // If there is an ADD32ri or SUB32ri of ESP immediately before this
1146      // instruction, merge the two instructions.
1147      if (MBBI != MBB.begin()) {
1148        MachineBasicBlock::iterator PI = prior(MBBI);
1149        unsigned Opc = PI->getOpcode();
1150        if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1151             Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1152            PI->getOperand(0).getReg() == StackPtr) {
1153          NumBytes += PI->getOperand(2).getImmedValue();
1154          MBB.erase(PI);
1155        } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1156                    Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1157                   PI->getOperand(0).getReg() == StackPtr) {
1158          NumBytes -= PI->getOperand(2).getImmedValue();
1159          MBB.erase(PI);
1160        }
1161      }
1162
1163      if (NumBytes > 0) {
1164        unsigned Opc = (NumBytes < 128) ?
1165          (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1166          (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1167        BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
1168                .addReg(StackPtr).addImm(NumBytes);
1169      } else if ((int)NumBytes < 0) {
1170        unsigned Opc = (-NumBytes < 128) ?
1171          (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1172          (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1173        BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
1174                .addReg(StackPtr).addImm(-NumBytes);
1175      }
1176    }
1177  }
1178}
1179
1180unsigned X86RegisterInfo::getRARegister() const {
1181  return X86::ST0;  // use a non-register register
1182}
1183
1184unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1185  return hasFP(MF) ? FramePtr : StackPtr;
1186}
1187
1188void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1189                                                                         const {
1190  // Initial state of the frame pointer is esp.
1191  MachineLocation Dst(MachineLocation::VirtualFP);
1192  MachineLocation Src(StackPtr, 0);
1193  Moves.push_back(MachineMove(0, Dst, Src));
1194}
1195
1196namespace llvm {
1197unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1198  switch (VT) {
1199  default: return Reg;
1200  case MVT::i8:
1201    if (High) {
1202      switch (Reg) {
1203      default: return 0;
1204      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1205        return X86::AH;
1206      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1207        return X86::DH;
1208      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1209        return X86::CH;
1210      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1211        return X86::BH;
1212      }
1213    } else {
1214      switch (Reg) {
1215      default: return 0;
1216      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1217        return X86::AL;
1218      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1219        return X86::DL;
1220      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1221        return X86::CL;
1222      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1223        return X86::BL;
1224      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1225        return X86::SIL;
1226      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1227        return X86::DIL;
1228      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1229        return X86::BPL;
1230      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1231        return X86::SPL;
1232      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1233        return X86::R8B;
1234      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1235        return X86::R9B;
1236      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1237        return X86::R10B;
1238      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1239        return X86::R11B;
1240      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1241        return X86::R12B;
1242      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1243        return X86::R13B;
1244      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1245        return X86::R14B;
1246      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1247        return X86::R15B;
1248      }
1249    }
1250  case MVT::i16:
1251    switch (Reg) {
1252    default: return Reg;
1253    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1254      return X86::AX;
1255    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1256      return X86::DX;
1257    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1258      return X86::CX;
1259    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1260      return X86::BX;
1261    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1262      return X86::SI;
1263    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1264      return X86::DI;
1265    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1266      return X86::BP;
1267    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1268      return X86::SP;
1269    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1270      return X86::R8W;
1271    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1272      return X86::R9W;
1273    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1274      return X86::R10W;
1275    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1276      return X86::R11W;
1277    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1278      return X86::R12W;
1279    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1280      return X86::R13W;
1281    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1282      return X86::R14W;
1283    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1284      return X86::R15W;
1285    }
1286  case MVT::i32:
1287    switch (Reg) {
1288    default: return Reg;
1289    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1290      return X86::EAX;
1291    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1292      return X86::EDX;
1293    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1294      return X86::ECX;
1295    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1296      return X86::EBX;
1297    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1298      return X86::ESI;
1299    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1300      return X86::EDI;
1301    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1302      return X86::EBP;
1303    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1304      return X86::ESP;
1305    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1306      return X86::R8D;
1307    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1308      return X86::R9D;
1309    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1310      return X86::R10D;
1311    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1312      return X86::R11D;
1313    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1314      return X86::R12D;
1315    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1316      return X86::R13D;
1317    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1318      return X86::R14D;
1319    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1320      return X86::R15D;
1321    }
1322  case MVT::i64:
1323    switch (Reg) {
1324    default: return Reg;
1325    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1326      return X86::RAX;
1327    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1328      return X86::RDX;
1329    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1330      return X86::RCX;
1331    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1332      return X86::RBX;
1333    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1334      return X86::RSI;
1335    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1336      return X86::RDI;
1337    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1338      return X86::RBP;
1339    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1340      return X86::RSP;
1341    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1342      return X86::R8;
1343    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1344      return X86::R9;
1345    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1346      return X86::R10;
1347    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1348      return X86::R11;
1349    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1350      return X86::R12;
1351    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1352      return X86::R13;
1353    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1354      return X86::R14;
1355    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1356      return X86::R15;
1357    }
1358  }
1359
1360  return Reg;
1361}
1362}
1363
1364#include "X86GenRegisterInfo.inc"
1365
1366