X86RegisterInfo.cpp revision c18f4efc5dd24adcc653806455fc7ae8508e9c66 
1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86RegisterInfo.h"
17#include "X86.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/ValueTypes.h"
31#include "llvm/IR/Constants.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/Type.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Target/TargetFrameLowering.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Target/TargetOptions.h"
41
42#define GET_REGINFO_TARGET_DESC
43#include "X86GenRegisterInfo.inc"
44
45using namespace llvm;
46
47cl::opt<bool>
48ForceStackAlign("force-align-stack",
49                 cl::desc("Force align the stack to the minimum alignment"
50                           " needed for the function."),
51                 cl::init(false), cl::Hidden);
52
53static cl::opt<bool>
54EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm)
58  : X86GenRegisterInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
59                         ? X86::RIP : X86::EIP),
60                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
61                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true),
62                       (tm.getSubtarget<X86Subtarget>().is64Bit()
63                         ? X86::RIP : X86::EIP)),
64                       TM(tm) {
65  X86_MC::InitLLVM2SEHRegisterMapping(this);
66
67  // Cache some information.
68  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
69  Is64Bit = Subtarget->is64Bit();
70  IsWin64 = Subtarget->isTargetWin64();
71
72  if (Is64Bit) {
73    SlotSize = 8;
74    StackPtr = X86::RSP;
75    FramePtr = X86::RBP;
76  } else {
77    SlotSize = 4;
78    StackPtr = X86::ESP;
79    FramePtr = X86::EBP;
80  }
81  // Use a callee-saved register as the base pointer.  These registers must
82  // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
83  // requires GOT in the EBX register before function calls via PLT GOT pointer.
84  BasePtr = Is64Bit ? X86::RBX : X86::ESI;
85}
86
87/// getCompactUnwindRegNum - This function maps the register to the number for
88/// compact unwind encoding. Return -1 if the register isn't valid.
89int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
90  switch (getLLVMRegNum(RegNum, isEH)) {
91  case X86::EBX: case X86::RBX: return 1;
92  case X86::ECX: case X86::R12: return 2;
93  case X86::EDX: case X86::R13: return 3;
94  case X86::EDI: case X86::R14: return 4;
95  case X86::ESI: case X86::R15: return 5;
96  case X86::EBP: case X86::RBP: return 6;
97  }
98
99  return -1;
100}
101
102bool
103X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
104  // Only enable when post-RA scheduling is enabled and this is needed.
105  return TM.getSubtargetImpl()->postRAScheduler();
106}
107
108int
109X86RegisterInfo::getSEHRegNum(unsigned i) const {
110  return getEncodingValue(i);
111}
112
113const TargetRegisterClass *
114X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
115                                       unsigned Idx) const {
116  // The sub_8bit sub-register index is more constrained in 32-bit mode.
117  // It behaves just like the sub_8bit_hi index.
118  if (!Is64Bit && Idx == X86::sub_8bit)
119    Idx = X86::sub_8bit_hi;
120
121  // Forward to TableGen's default version.
122  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
123}
124
125const TargetRegisterClass *
126X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
127                                          const TargetRegisterClass *B,
128                                          unsigned SubIdx) const {
129  // The sub_8bit sub-register index is more constrained in 32-bit mode.
130  if (!Is64Bit && SubIdx == X86::sub_8bit) {
131    A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
132    if (!A)
133      return 0;
134  }
135  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
136}
137
138const TargetRegisterClass*
139X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
140  // Don't allow super-classes of GR8_NOREX.  This class is only used after
141  // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
142  // to the full GR8 register class in 64-bit mode, so we cannot allow the
143  // reigster class inflation.
144  //
145  // The GR8_NOREX class is always used in a way that won't be constrained to a
146  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
147  // full GR8 class.
148  if (RC == &X86::GR8_NOREXRegClass)
149    return RC;
150
151  const TargetRegisterClass *Super = RC;
152  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
153  do {
154    switch (Super->getID()) {
155    case X86::GR8RegClassID:
156    case X86::GR16RegClassID:
157    case X86::GR32RegClassID:
158    case X86::GR64RegClassID:
159    case X86::FR32RegClassID:
160    case X86::FR64RegClassID:
161    case X86::RFP32RegClassID:
162    case X86::RFP64RegClassID:
163    case X86::RFP80RegClassID:
164    case X86::VR128RegClassID:
165    case X86::VR256RegClassID:
166      // Don't return a super-class that would shrink the spill size.
167      // That can happen with the vector and float classes.
168      if (Super->getSize() == RC->getSize())
169        return Super;
170    }
171    Super = *I++;
172  } while (Super);
173  return RC;
174}
175
176const TargetRegisterClass *
177X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
178                                                                         const {
179  const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
180  switch (Kind) {
181  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
182  case 0: // Normal GPRs.
183    if (Subtarget.isTarget64BitLP64())
184      return &X86::GR64RegClass;
185    return &X86::GR32RegClass;
186  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
187    if (Subtarget.isTarget64BitLP64())
188      return &X86::GR64_NOSPRegClass;
189    return &X86::GR32_NOSPRegClass;
190  case 2: // Available for tailcall (not callee-saved GPRs).
191    if (Subtarget.isTargetWin64())
192      return &X86::GR64_TCW64RegClass;
193    else if (Subtarget.is64Bit())
194      return &X86::GR64_TCRegClass;
195
196    const Function *F = MF.getFunction();
197    bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
198    if (hasHipeCC)
199      return &X86::GR32RegClass;
200    return &X86::GR32_TCRegClass;
201  }
202}
203
204const TargetRegisterClass *
205X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
206  if (RC == &X86::CCRRegClass) {
207    if (Is64Bit)
208      return &X86::GR64RegClass;
209    else
210      return &X86::GR32RegClass;
211  }
212  return RC;
213}
214
215unsigned
216X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
217                                     MachineFunction &MF) const {
218  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
219
220  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
221  switch (RC->getID()) {
222  default:
223    return 0;
224  case X86::GR32RegClassID:
225    return 4 - FPDiff;
226  case X86::GR64RegClassID:
227    return 12 - FPDiff;
228  case X86::VR128RegClassID:
229    return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
230  case X86::VR64RegClassID:
231    return 4;
232  }
233}
234
235const uint16_t *
236X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
237  switch (MF->getFunction()->getCallingConv()) {
238  case CallingConv::GHC:
239  case CallingConv::HiPE:
240    return CSR_NoRegs_SaveList;
241
242  case CallingConv::Intel_OCL_BI: {
243    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
244    bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
245    if (HasAVX512 && IsWin64)
246      return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
247    if (HasAVX512 && Is64Bit)
248      return CSR_64_Intel_OCL_BI_AVX512_SaveList;
249    if (HasAVX && IsWin64)
250      return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
251    if (HasAVX && Is64Bit)
252      return CSR_64_Intel_OCL_BI_AVX_SaveList;
253    if (!HasAVX && !IsWin64 && Is64Bit)
254      return CSR_64_Intel_OCL_BI_SaveList;
255    break;
256  }
257
258  case CallingConv::Cold:
259    if (Is64Bit)
260      return CSR_MostRegs_64_SaveList;
261    break;
262
263  default:
264    break;
265  }
266
267  bool CallsEHReturn = MF->getMMI().callsEHReturn();
268  if (Is64Bit) {
269    if (IsWin64)
270      return CSR_Win64_SaveList;
271    if (CallsEHReturn)
272      return CSR_64EHRet_SaveList;
273    return CSR_64_SaveList;
274  }
275  if (CallsEHReturn)
276    return CSR_32EHRet_SaveList;
277  return CSR_32_SaveList;
278}
279
280const uint32_t*
281X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
282  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
283  bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
284
285  if (CC == CallingConv::Intel_OCL_BI) {
286    if (IsWin64 && HasAVX512)
287      return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
288    if (Is64Bit && HasAVX512)
289      return CSR_64_Intel_OCL_BI_AVX512_RegMask;
290    if (IsWin64 && HasAVX)
291      return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
292    if (Is64Bit && HasAVX)
293      return CSR_64_Intel_OCL_BI_AVX_RegMask;
294    if (!HasAVX && !IsWin64 && Is64Bit)
295      return CSR_64_Intel_OCL_BI_RegMask;
296  }
297  if (CC == CallingConv::GHC || CC == CallingConv::HiPE)
298    return CSR_NoRegs_RegMask;
299  if (!Is64Bit)
300    return CSR_32_RegMask;
301  if (CC == CallingConv::Cold)
302    return CSR_MostRegs_64_RegMask;
303  if (IsWin64)
304    return CSR_Win64_RegMask;
305  return CSR_64_RegMask;
306}
307
308const uint32_t*
309X86RegisterInfo::getNoPreservedMask() const {
310  return CSR_NoRegs_RegMask;
311}
312
313BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
314  BitVector Reserved(getNumRegs());
315  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
316
317  // Set the stack-pointer register and its aliases as reserved.
318  for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
319       ++I)
320    Reserved.set(*I);
321
322  // Set the instruction pointer register and its aliases as reserved.
323  for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
324       ++I)
325    Reserved.set(*I);
326
327  // Set the frame-pointer register and its aliases as reserved if needed.
328  if (TFI->hasFP(MF)) {
329    for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
330         ++I)
331      Reserved.set(*I);
332  }
333
334  // Set the base-pointer register and its aliases as reserved if needed.
335  if (hasBasePointer(MF)) {
336    CallingConv::ID CC = MF.getFunction()->getCallingConv();
337    const uint32_t* RegMask = getCallPreservedMask(CC);
338    if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
339      report_fatal_error(
340        "Stack realignment in presence of dynamic allocas is not supported with"
341        "this calling convention.");
342
343    for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
344         I.isValid(); ++I)
345      Reserved.set(*I);
346  }
347
348  // Mark the segment registers as reserved.
349  Reserved.set(X86::CS);
350  Reserved.set(X86::SS);
351  Reserved.set(X86::DS);
352  Reserved.set(X86::ES);
353  Reserved.set(X86::FS);
354  Reserved.set(X86::GS);
355
356  // Mark the floating point stack registers as reserved.
357  for (unsigned n = 0; n != 8; ++n)
358    Reserved.set(X86::ST0 + n);
359
360  // Reserve the registers that only exist in 64-bit mode.
361  if (!Is64Bit) {
362    // These 8-bit registers are part of the x86-64 extension even though their
363    // super-registers are old 32-bits.
364    Reserved.set(X86::SIL);
365    Reserved.set(X86::DIL);
366    Reserved.set(X86::BPL);
367    Reserved.set(X86::SPL);
368
369    for (unsigned n = 0; n != 8; ++n) {
370      // R8, R9, ...
371      for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
372        Reserved.set(*AI);
373
374      // XMM8, XMM9, ...
375      for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
376        Reserved.set(*AI);
377    }
378  }
379  if (!Is64Bit || !TM.getSubtarget<X86Subtarget>().hasAVX512()) {
380    for (unsigned n = 16; n != 32; ++n) {
381      for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
382        Reserved.set(*AI);
383    }
384  }
385
386  return Reserved;
387}
388
389//===----------------------------------------------------------------------===//
390// Stack Frame Processing methods
391//===----------------------------------------------------------------------===//
392
393bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
394   const MachineFrameInfo *MFI = MF.getFrameInfo();
395
396   if (!EnableBasePointer)
397     return false;
398
399   // When we need stack realignment and there are dynamic allocas, we can't
400   // reference off of the stack pointer, so we reserve a base pointer.
401   //
402   // This is also true if the function contain MS-style inline assembly.  We
403   // do this because if any stack changes occur in the inline assembly, e.g.,
404   // "pusha", then any C local variable or C argument references in the
405   // inline assembly will be wrong because the SP is not properly tracked.
406   if ((needsStackRealignment(MF) && MFI->hasVarSizedObjects()) ||
407       MF.hasMSInlineAsm())
408     return true;
409
410   return false;
411}
412
413bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
414  const MachineFrameInfo *MFI = MF.getFrameInfo();
415  const MachineRegisterInfo *MRI = &MF.getRegInfo();
416  if (!MF.getTarget().Options.RealignStack)
417    return false;
418
419  // Stack realignment requires a frame pointer.  If we already started
420  // register allocation with frame pointer elimination, it is too late now.
421  if (!MRI->canReserveReg(FramePtr))
422    return false;
423
424  // If a base pointer is necessary.  Check that it isn't too late to reserve
425  // it.
426  if (MFI->hasVarSizedObjects())
427    return MRI->canReserveReg(BasePtr);
428  return true;
429}
430
431bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
432  const MachineFrameInfo *MFI = MF.getFrameInfo();
433  const Function *F = MF.getFunction();
434  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
435  bool requiresRealignment =
436    ((MFI->getMaxAlignment() > StackAlign) ||
437     F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
438                                     Attribute::StackAlignment));
439
440  // If we've requested that we force align the stack do so now.
441  if (ForceStackAlign)
442    return canRealignStack(MF);
443
444  return requiresRealignment && canRealignStack(MF);
445}
446
447bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
448                                           unsigned Reg, int &FrameIdx) const {
449  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
450
451  if (Reg == FramePtr && TFI->hasFP(MF)) {
452    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
453    return true;
454  }
455  return false;
456}
457
458void
459X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
460                                     int SPAdj, unsigned FIOperandNum,
461                                     RegScavenger *RS) const {
462  assert(SPAdj == 0 && "Unexpected");
463
464  MachineInstr &MI = *II;
465  MachineFunction &MF = *MI.getParent()->getParent();
466  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
467  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
468  unsigned BasePtr;
469
470  unsigned Opc = MI.getOpcode();
471  bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
472  if (hasBasePointer(MF))
473    BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
474  else if (needsStackRealignment(MF))
475    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
476  else if (AfterFPPop)
477    BasePtr = StackPtr;
478  else
479    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
480
481  // This must be part of a four operand memory reference.  Replace the
482  // FrameIndex with base register with EBP.  Add an offset to the offset.
483  MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
484
485  // Now add the frame object offset to the offset from EBP.
486  int FIOffset;
487  if (AfterFPPop) {
488    // Tail call jmp happens after FP is popped.
489    const MachineFrameInfo *MFI = MF.getFrameInfo();
490    FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
491  } else
492    FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
493
494  if (MI.getOperand(FIOperandNum+3).isImm()) {
495    // Offset is a 32-bit integer.
496    int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
497    int Offset = FIOffset + Imm;
498    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
499           "Requesting 64-bit offset in 32-bit immediate!");
500    MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
501  } else {
502    // Offset is symbolic. This is extremely rare.
503    uint64_t Offset = FIOffset +
504      (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
505    MI.getOperand(FIOperandNum + 3).setOffset(Offset);
506  }
507}
508
509unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
510  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
511  return TFI->hasFP(MF) ? FramePtr : StackPtr;
512}
513
514unsigned X86RegisterInfo::getEHExceptionRegister() const {
515  llvm_unreachable("What is the exception register");
516}
517
518unsigned X86RegisterInfo::getEHHandlerRegister() const {
519  llvm_unreachable("What is the exception handler register");
520}
521
522namespace llvm {
523unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
524                                bool High) {
525  switch (VT) {
526  default: llvm_unreachable("Unexpected VT");
527  case MVT::i8:
528    if (High) {
529      switch (Reg) {
530      default: return getX86SubSuperRegister(Reg, MVT::i64);
531      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
532        return X86::SI;
533      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
534        return X86::DI;
535      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
536        return X86::BP;
537      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
538        return X86::SP;
539      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
540        return X86::AH;
541      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
542        return X86::DH;
543      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
544        return X86::CH;
545      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
546        return X86::BH;
547      }
548    } else {
549      switch (Reg) {
550      default: llvm_unreachable("Unexpected register");
551      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
552        return X86::AL;
553      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
554        return X86::DL;
555      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
556        return X86::CL;
557      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
558        return X86::BL;
559      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
560        return X86::SIL;
561      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
562        return X86::DIL;
563      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
564        return X86::BPL;
565      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
566        return X86::SPL;
567      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
568        return X86::R8B;
569      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
570        return X86::R9B;
571      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
572        return X86::R10B;
573      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
574        return X86::R11B;
575      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
576        return X86::R12B;
577      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
578        return X86::R13B;
579      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
580        return X86::R14B;
581      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
582        return X86::R15B;
583      }
584    }
585  case MVT::i16:
586    switch (Reg) {
587    default: llvm_unreachable("Unexpected register");
588    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
589      return X86::AX;
590    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
591      return X86::DX;
592    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
593      return X86::CX;
594    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
595      return X86::BX;
596    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
597      return X86::SI;
598    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
599      return X86::DI;
600    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
601      return X86::BP;
602    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
603      return X86::SP;
604    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
605      return X86::R8W;
606    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
607      return X86::R9W;
608    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
609      return X86::R10W;
610    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
611      return X86::R11W;
612    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
613      return X86::R12W;
614    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
615      return X86::R13W;
616    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
617      return X86::R14W;
618    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
619      return X86::R15W;
620    }
621  case MVT::i32:
622    switch (Reg) {
623    default: llvm_unreachable("Unexpected register");
624    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
625      return X86::EAX;
626    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
627      return X86::EDX;
628    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
629      return X86::ECX;
630    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
631      return X86::EBX;
632    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
633      return X86::ESI;
634    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
635      return X86::EDI;
636    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
637      return X86::EBP;
638    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
639      return X86::ESP;
640    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
641      return X86::R8D;
642    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
643      return X86::R9D;
644    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
645      return X86::R10D;
646    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
647      return X86::R11D;
648    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
649      return X86::R12D;
650    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
651      return X86::R13D;
652    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
653      return X86::R14D;
654    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
655      return X86::R15D;
656    }
657  case MVT::i64:
658    switch (Reg) {
659    default: llvm_unreachable("Unexpected register");
660    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
661      return X86::RAX;
662    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
663      return X86::RDX;
664    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
665      return X86::RCX;
666    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
667      return X86::RBX;
668    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
669      return X86::RSI;
670    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
671      return X86::RDI;
672    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
673      return X86::RBP;
674    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
675      return X86::RSP;
676    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
677      return X86::R8;
678    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
679      return X86::R9;
680    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
681      return X86::R10;
682    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
683      return X86::R11;
684    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
685      return X86::R12;
686    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
687      return X86::R13;
688    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
689      return X86::R14;
690    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
691      return X86::R15;
692    }
693  }
694}
695
696unsigned get512BitSuperRegister(unsigned Reg) {
697  if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
698    return X86::ZMM0 + (Reg - X86::XMM0);
699  if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
700    return X86::ZMM0 + (Reg - X86::YMM0);
701  if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
702    return Reg;
703  llvm_unreachable("Unexpected SIMD register");
704}
705
706}
707