X86RegisterInfo.cpp revision d93d3b047cad68de985d413d2cad953ac758d2a7
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the MRegisterInfo class.  This
11// file is responsible for the frame pointer elimination optimization on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86RegisterInfo.h"
17#include "X86InstrBuilder.h"
18#include "llvm/Constants.h"
19#include "llvm/Type.h"
20#include "llvm/CodeGen/ValueTypes.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/Target/TargetFrameInfo.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/Target/TargetOptions.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/ADT/STLExtras.h"
29#include <iostream>
30
31using namespace llvm;
32
33namespace {
34  cl::opt<bool>
35  NoFusing("disable-spill-fusing",
36           cl::desc("Disable fusing of spill code into instructions"));
37  cl::opt<bool>
38  PrintFailedFusing("print-failed-fuse-candidates",
39                    cl::desc("Print instructions that the allocator wants to"
40                             " fuse, but the X86 backend currently can't"),
41                    cl::Hidden);
42}
43
44X86RegisterInfo::X86RegisterInfo()
45  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
46
47static unsigned getIdx(unsigned SpillSize) {
48  switch (SpillSize) {
49  default: assert(0 && "Invalid data size!");
50  case 8:  return 0;
51  case 16: return 1;
52  case 32: return 2;
53  case 80: return 3;
54  }
55}
56
57void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
58                                          MachineBasicBlock::iterator MI,
59                                          unsigned SrcReg, int FrameIdx) const {
60  static const unsigned Opcode[] =
61    { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FSTP80m };
62  unsigned Idx = getIdx(getSpillSize(SrcReg));
63  addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 5), FrameIdx).addReg(SrcReg);
64}
65
66void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
67                                           MachineBasicBlock::iterator MI,
68                                           unsigned DestReg, int FrameIdx)const{
69  static const unsigned Opcode[] =
70    { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD80m };
71  unsigned Idx = getIdx(getSpillSize(DestReg));
72  addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 4, DestReg), FrameIdx);
73}
74
75void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
76                                   MachineBasicBlock::iterator MI,
77                                   unsigned DestReg, unsigned SrcReg,
78                                   const TargetRegisterClass *RC) const {
79  static const unsigned Opcode[] =
80    { X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV };
81  BuildMI(MBB, MI, Opcode[getIdx(RC->getSize()*8)], 1, DestReg).addReg(SrcReg);
82}
83
84static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
85                               MachineInstr *MI) {
86  return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
87}
88
89static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
90                                MachineInstr *MI) {
91  return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
92                 .addReg(MI->getOperand(1).getReg());
93}
94
95static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
96                                 MachineInstr *MI) {
97  return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
98      .addReg(MI->getOperand(1).getReg())
99      .addZImm(MI->getOperand(2).getImmedValue());
100}
101
102static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
103                                MachineInstr *MI) {
104  if (MI->getOperand(1).isImmediate())
105    return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
106      .addZImm(MI->getOperand(1).getImmedValue());
107  else if (MI->getOperand(1).isGlobalAddress())
108    return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
109      .addGlobalAddress(MI->getOperand(1).getGlobal());
110  assert(0 && "Unknown operand for MakeMI!");
111  return 0;
112}
113
114static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
115                                MachineInstr *MI) {
116  const MachineOperand& op = MI->getOperand(0);
117  return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
118                           FrameIndex);
119}
120
121static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
122                                 MachineInstr *MI) {
123  const MachineOperand& op = MI->getOperand(0);
124  return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
125                        FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
126}
127
128
129MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
130                                                 unsigned i,
131                                                 int FrameIndex) const {
132  if (NoFusing) return NULL;
133
134  /// FIXME: This should obviously be autogenerated by tablegen when patterns
135  /// are available!
136  MachineBasicBlock& MBB = *MI->getParent();
137  if (i == 0) {
138    switch(MI->getOpcode()) {
139    case X86::XCHG8rr:   return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI);
140    case X86::XCHG16rr:  return MakeMRInst(X86::XCHG16mr,FrameIndex, MI);
141    case X86::XCHG32rr:  return MakeMRInst(X86::XCHG32mr,FrameIndex, MI);
142    case X86::MOV8rr:    return MakeMRInst(X86::MOV8mr , FrameIndex, MI);
143    case X86::MOV16rr:   return MakeMRInst(X86::MOV16mr, FrameIndex, MI);
144    case X86::MOV32rr:   return MakeMRInst(X86::MOV32mr, FrameIndex, MI);
145    case X86::MOV8ri:    return MakeMIInst(X86::MOV8mi , FrameIndex, MI);
146    case X86::MOV16ri:   return MakeMIInst(X86::MOV16mi, FrameIndex, MI);
147    case X86::MOV32ri:   return MakeMIInst(X86::MOV32mi, FrameIndex, MI);
148    case X86::MUL8r:     return MakeMInst( X86::MUL8m ,  FrameIndex, MI);
149    case X86::MUL16r:    return MakeMInst( X86::MUL16m,  FrameIndex, MI);
150    case X86::MUL32r:    return MakeMInst( X86::MUL32m,  FrameIndex, MI);
151    case X86::DIV8r:     return MakeMInst( X86::DIV8m ,  FrameIndex, MI);
152    case X86::DIV16r:    return MakeMInst( X86::DIV16m,  FrameIndex, MI);
153    case X86::DIV32r:    return MakeMInst( X86::DIV32m,  FrameIndex, MI);
154    case X86::IDIV8r:    return MakeMInst( X86::IDIV8m , FrameIndex, MI);
155    case X86::IDIV16r:   return MakeMInst( X86::IDIV16m, FrameIndex, MI);
156    case X86::IDIV32r:   return MakeMInst( X86::IDIV32m, FrameIndex, MI);
157    case X86::NEG8r:     return MakeMInst( X86::NEG8m ,  FrameIndex, MI);
158    case X86::NEG16r:    return MakeMInst( X86::NEG16m,  FrameIndex, MI);
159    case X86::NEG32r:    return MakeMInst( X86::NEG32m,  FrameIndex, MI);
160    case X86::NOT8r:     return MakeMInst( X86::NOT8m ,  FrameIndex, MI);
161    case X86::NOT16r:    return MakeMInst( X86::NOT16m,  FrameIndex, MI);
162    case X86::NOT32r:    return MakeMInst( X86::NOT32m,  FrameIndex, MI);
163    case X86::INC8r:     return MakeMInst( X86::INC8m ,  FrameIndex, MI);
164    case X86::INC16r:    return MakeMInst( X86::INC16m,  FrameIndex, MI);
165    case X86::INC32r:    return MakeMInst( X86::INC32m,  FrameIndex, MI);
166    case X86::DEC8r:     return MakeMInst( X86::DEC8m ,  FrameIndex, MI);
167    case X86::DEC16r:    return MakeMInst( X86::DEC16m,  FrameIndex, MI);
168    case X86::DEC32r:    return MakeMInst( X86::DEC32m,  FrameIndex, MI);
169    case X86::ADD8rr:    return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
170    case X86::ADD16rr:   return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
171    case X86::ADD32rr:   return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
172    case X86::ADC32rr:   return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
173    case X86::ADC32ri:   return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
174    case X86::ADD8ri:    return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
175    case X86::ADD16ri:   return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
176    case X86::ADD32ri:   return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
177    case X86::SUB8rr:    return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
178    case X86::SUB16rr:   return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
179    case X86::SUB32rr:   return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
180    case X86::SBB32rr:   return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
181    case X86::SBB8ri:    return MakeMIInst(X86::SBB8mi,  FrameIndex, MI);
182    case X86::SBB16ri:   return MakeMIInst(X86::SBB16mi, FrameIndex, MI);
183    case X86::SBB32ri:   return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
184    case X86::SUB8ri:    return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
185    case X86::SUB16ri:   return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
186    case X86::SUB32ri:   return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
187    case X86::AND8rr:    return MakeMRInst(X86::AND8mr , FrameIndex, MI);
188    case X86::AND16rr:   return MakeMRInst(X86::AND16mr, FrameIndex, MI);
189    case X86::AND32rr:   return MakeMRInst(X86::AND32mr, FrameIndex, MI);
190    case X86::AND8ri:    return MakeMIInst(X86::AND8mi , FrameIndex, MI);
191    case X86::AND16ri:   return MakeMIInst(X86::AND16mi, FrameIndex, MI);
192    case X86::AND32ri:   return MakeMIInst(X86::AND32mi, FrameIndex, MI);
193    case X86::OR8rr:     return MakeMRInst(X86::OR8mr ,  FrameIndex, MI);
194    case X86::OR16rr:    return MakeMRInst(X86::OR16mr,  FrameIndex, MI);
195    case X86::OR32rr:    return MakeMRInst(X86::OR32mr,  FrameIndex, MI);
196    case X86::OR8ri:     return MakeMIInst(X86::OR8mi ,  FrameIndex, MI);
197    case X86::OR16ri:    return MakeMIInst(X86::OR16mi,  FrameIndex, MI);
198    case X86::OR32ri:    return MakeMIInst(X86::OR32mi,  FrameIndex, MI);
199    case X86::XOR8rr:    return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
200    case X86::XOR16rr:   return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
201    case X86::XOR32rr:   return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
202    case X86::XOR8ri:    return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
203    case X86::XOR16ri:   return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
204    case X86::XOR32ri:   return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
205    case X86::SHL8rCL:   return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
206    case X86::SHL16rCL:  return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
207    case X86::SHL32rCL:  return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
208    case X86::SHL8ri:    return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
209    case X86::SHL16ri:   return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
210    case X86::SHL32ri:   return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
211    case X86::SHR8rCL:   return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
212    case X86::SHR16rCL:  return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
213    case X86::SHR32rCL:  return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
214    case X86::SHR8ri:    return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
215    case X86::SHR16ri:   return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
216    case X86::SHR32ri:   return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
217    case X86::SAR8rCL:   return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
218    case X86::SAR16rCL:  return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
219    case X86::SAR32rCL:  return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
220    case X86::SAR8ri:    return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
221    case X86::SAR16ri:   return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
222    case X86::SAR32ri:   return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
223    case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
224    case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
225    case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
226    case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);
227    case X86::SETBr:     return MakeMInst( X86::SETBm,   FrameIndex, MI);
228    case X86::SETAEr:    return MakeMInst( X86::SETAEm,  FrameIndex, MI);
229    case X86::SETEr:     return MakeMInst( X86::SETEm,   FrameIndex, MI);
230    case X86::SETNEr:    return MakeMInst( X86::SETNEm,  FrameIndex, MI);
231    case X86::SETBEr:    return MakeMInst( X86::SETBEm,  FrameIndex, MI);
232    case X86::SETAr:     return MakeMInst( X86::SETAm,   FrameIndex, MI);
233    case X86::SETSr:     return MakeMInst( X86::SETSm,   FrameIndex, MI);
234    case X86::SETNSr:    return MakeMInst( X86::SETNSm,  FrameIndex, MI);
235    case X86::SETPr:     return MakeMInst( X86::SETPm,   FrameIndex, MI);
236    case X86::SETLr:     return MakeMInst( X86::SETLm,   FrameIndex, MI);
237    case X86::SETGEr:    return MakeMInst( X86::SETGEm,  FrameIndex, MI);
238    case X86::SETLEr:    return MakeMInst( X86::SETLEm,  FrameIndex, MI);
239    case X86::SETGr:     return MakeMInst( X86::SETGm,   FrameIndex, MI);
240    case X86::TEST8rr:   return MakeMRInst(X86::TEST8mr ,FrameIndex, MI);
241    case X86::TEST16rr:  return MakeMRInst(X86::TEST16mr,FrameIndex, MI);
242    case X86::TEST32rr:  return MakeMRInst(X86::TEST32mr,FrameIndex, MI);
243    case X86::TEST8ri:   return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
244    case X86::TEST16ri:  return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
245    case X86::TEST32ri:  return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
246    case X86::CMP8rr:    return MakeMRInst(X86::CMP8mr , FrameIndex, MI);
247    case X86::CMP16rr:   return MakeMRInst(X86::CMP16mr, FrameIndex, MI);
248    case X86::CMP32rr:   return MakeMRInst(X86::CMP32mr, FrameIndex, MI);
249    case X86::CMP8ri:    return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
250    case X86::CMP16ri:   return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
251    case X86::CMP32ri:   return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
252    }
253  } else if (i == 1) {
254    switch(MI->getOpcode()) {
255    case X86::XCHG8rr:   return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI);
256    case X86::XCHG16rr:  return MakeRMInst(X86::XCHG16rm,FrameIndex, MI);
257    case X86::XCHG32rr:  return MakeRMInst(X86::XCHG32rm,FrameIndex, MI);
258    case X86::MOV8rr:    return MakeRMInst(X86::MOV8rm , FrameIndex, MI);
259    case X86::MOV16rr:   return MakeRMInst(X86::MOV16rm, FrameIndex, MI);
260    case X86::MOV32rr:   return MakeRMInst(X86::MOV32rm, FrameIndex, MI);
261    case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI);
262    case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI);
263    case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI);
264    case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI);
265    case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI);
266    case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI);
267    case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI);
268    case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI);
269    case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI);
270    case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI);
271    case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI);
272    case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI);
273    case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI);
274    case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI);
275    case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI);
276    case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI);
277    case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI);
278    case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI);
279    case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI);
280    case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI);
281    case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI);
282    case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI);
283    case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI);
284    case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI);
285    case X86::ADD8rr:    return MakeRMInst(X86::ADD8rm , FrameIndex, MI);
286    case X86::ADD16rr:   return MakeRMInst(X86::ADD16rm, FrameIndex, MI);
287    case X86::ADD32rr:   return MakeRMInst(X86::ADD32rm, FrameIndex, MI);
288    case X86::ADC32rr:   return MakeRMInst(X86::ADC32rm, FrameIndex, MI);
289    case X86::SUB8rr:    return MakeRMInst(X86::SUB8rm , FrameIndex, MI);
290    case X86::SUB16rr:   return MakeRMInst(X86::SUB16rm, FrameIndex, MI);
291    case X86::SUB32rr:   return MakeRMInst(X86::SUB32rm, FrameIndex, MI);
292    case X86::SBB32rr:   return MakeRMInst(X86::SBB32rm, FrameIndex, MI);
293    case X86::AND8rr:    return MakeRMInst(X86::AND8rm , FrameIndex, MI);
294    case X86::AND16rr:   return MakeRMInst(X86::AND16rm, FrameIndex, MI);
295    case X86::AND32rr:   return MakeRMInst(X86::AND32rm, FrameIndex, MI);
296    case X86::OR8rr:     return MakeRMInst(X86::OR8rm ,  FrameIndex, MI);
297    case X86::OR16rr:    return MakeRMInst(X86::OR16rm,  FrameIndex, MI);
298    case X86::OR32rr:    return MakeRMInst(X86::OR32rm,  FrameIndex, MI);
299    case X86::XOR8rr:    return MakeRMInst(X86::XOR8rm , FrameIndex, MI);
300    case X86::XOR16rr:   return MakeRMInst(X86::XOR16rm, FrameIndex, MI);
301    case X86::XOR32rr:   return MakeRMInst(X86::XOR32rm, FrameIndex, MI);
302    case X86::TEST8rr:   return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
303    case X86::TEST16rr:  return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
304    case X86::TEST32rr:  return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
305    case X86::IMUL16rr:  return MakeRMInst(X86::IMUL16rm,FrameIndex, MI);
306    case X86::IMUL32rr:  return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
307    case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
308    case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
309    case X86::CMP8rr:    return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
310    case X86::CMP16rr:   return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
311    case X86::CMP32rr:   return MakeRMInst(X86::CMP32rm, FrameIndex, MI);
312    case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI);
313    case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI);
314    case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI);
315    case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
316    case X86::MOVZX32rr8:  return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
317    case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
318    }
319  }
320  if (PrintFailedFusing)
321    std::cerr << "We failed to fuse: " << *MI;
322  return NULL;
323}
324
325//===----------------------------------------------------------------------===//
326// Stack Frame Processing methods
327//===----------------------------------------------------------------------===//
328
329// hasFP - Return true if the specified function should have a dedicated frame
330// pointer register.  This is true if the function has variable sized allocas or
331// if frame pointer elimination is disabled.
332//
333static bool hasFP(MachineFunction &MF) {
334  return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
335}
336
337void X86RegisterInfo::
338eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
339                              MachineBasicBlock::iterator I) const {
340  if (hasFP(MF)) {
341    // If we have a frame pointer, turn the adjcallstackup instruction into a
342    // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
343    // <amt>'
344    MachineInstr *Old = I;
345    unsigned Amount = Old->getOperand(0).getImmedValue();
346    if (Amount != 0) {
347      // We need to keep the stack aligned properly.  To do this, we round the
348      // amount of space needed for the outgoing arguments up to the next
349      // alignment boundary.
350      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
351      Amount = (Amount+Align-1)/Align*Align;
352
353      MachineInstr *New;
354      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
355	New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
356              .addZImm(Amount);
357      } else {
358	assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
359	New=BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
360              .addZImm(Amount);
361      }
362
363      // Replace the pseudo instruction with a new instruction...
364      MBB.insert(I, New);
365    }
366  }
367
368  MBB.erase(I);
369}
370
371void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
372  unsigned i = 0;
373  MachineInstr &MI = *II;
374  MachineFunction &MF = *MI.getParent()->getParent();
375  while (!MI.getOperand(i).isFrameIndex()) {
376    ++i;
377    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
378  }
379
380  int FrameIndex = MI.getOperand(i).getFrameIndex();
381
382  // This must be part of a four operand memory reference.  Replace the
383  // FrameIndex with base register with EBP.  Add add an offset to the offset.
384  MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
385
386  // Now add the frame object offset to the offset from EBP.
387  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
388               MI.getOperand(i+3).getImmedValue()+4;
389
390  if (!hasFP(MF))
391    Offset += MF.getFrameInfo()->getStackSize();
392  else
393    Offset += 4;  // Skip the saved EBP
394
395  MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
396}
397
398void
399X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
400  if (hasFP(MF)) {
401    // Create a frame entry for the EBP register that must be saved.
402    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
403    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
404           "Slot for EBP register must be last in order to be found!");
405  }
406}
407
408void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
409  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
410  MachineBasicBlock::iterator MBBI = MBB.begin();
411  MachineFrameInfo *MFI = MF.getFrameInfo();
412  MachineInstr *MI;
413
414  // Get the number of bytes to allocate from the FrameInfo
415  unsigned NumBytes = MFI->getStackSize();
416  if (hasFP(MF)) {
417    // Get the offset of the stack slot for the EBP register... which is
418    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
419    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
420
421    if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
422      MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
423            .addZImm(NumBytes);
424      MBB.insert(MBBI, MI);
425    }
426
427    // Save EBP into the appropriate stack slot...
428    MI = addRegOffset(BuildMI(X86::MOV32mr, 5),    // mov [ESP-<offset>], EBP
429		      X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
430    MBB.insert(MBBI, MI);
431
432    // Update EBP with the new base value...
433    if (NumBytes == 4)    // mov EBP, ESP
434      MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
435    else                  // lea EBP, [ESP+StackSize]
436      MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
437
438    MBB.insert(MBBI, MI);
439
440  } else {
441    if (MFI->hasCalls()) {
442      // When we have no frame pointer, we reserve argument space for call sites
443      // in the function immediately on entry to the current function.  This
444      // eliminates the need for add/sub ESP brackets around call sites.
445      //
446      NumBytes += MFI->getMaxCallFrameSize();
447
448      // Round the size to a multiple of the alignment (don't forget the 4 byte
449      // offset though).
450      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
451      NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
452    }
453
454    // Update frame info to pretend that this is part of the stack...
455    MFI->setStackSize(NumBytes);
456
457    if (NumBytes) {
458      // adjust stack pointer: ESP -= numbytes
459      MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
460            .addZImm(NumBytes);
461      MBB.insert(MBBI, MI);
462    }
463  }
464}
465
466void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
467                                   MachineBasicBlock &MBB) const {
468  const MachineFrameInfo *MFI = MF.getFrameInfo();
469  MachineBasicBlock::iterator MBBI = prior(MBB.end());
470  MachineInstr *MI;
471  assert(MBBI->getOpcode() == X86::RET &&
472         "Can only insert epilog into returning blocks");
473
474  if (hasFP(MF)) {
475    // Get the offset of the stack slot for the EBP register... which is
476    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
477    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
478
479    // mov ESP, EBP
480    MI = BuildMI(X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
481    MBB.insert(MBBI, MI);
482
483    // pop EBP
484    MI = BuildMI(X86::POP32r, 0, X86::EBP);
485    MBB.insert(MBBI, MI);
486  } else {
487    // Get the number of bytes allocated from the FrameInfo...
488    unsigned NumBytes = MFI->getStackSize();
489
490    if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
491      MI =BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
492            .addZImm(NumBytes);
493      MBB.insert(MBBI, MI);
494    }
495  }
496}
497
498#include "X86GenRegisterInfo.inc"
499
500const TargetRegisterClass*
501X86RegisterInfo::getRegClassForType(const Type* Ty) const {
502  switch (Ty->getTypeID()) {
503  case Type::LongTyID:
504  case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
505  default:              assert(0 && "Invalid type to getClass!");
506  case Type::BoolTyID:
507  case Type::SByteTyID:
508  case Type::UByteTyID:   return &R8Instance;
509  case Type::ShortTyID:
510  case Type::UShortTyID:  return &R16Instance;
511  case Type::IntTyID:
512  case Type::UIntTyID:
513  case Type::PointerTyID: return &R32Instance;
514
515  case Type::FloatTyID:
516  case Type::DoubleTyID: return &RFPInstance;
517  }
518}
519