1//===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the XCore implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "XCoreInstrInfo.h"
15#include "XCore.h"
16#include "XCoreMachineFunctionInfo.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/CodeGen/MachineConstantPool.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/IR/Constants.h"
23#include "llvm/IR/Function.h"
24#include "llvm/MC/MCContext.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/TargetRegistry.h"
28
29using namespace llvm;
30
31#define GET_INSTRINFO_CTOR_DTOR
32#include "XCoreGenInstrInfo.inc"
33
34namespace llvm {
35namespace XCore {
36
37  // XCore Condition Codes
38  enum CondCode {
39    COND_TRUE,
40    COND_FALSE,
41    COND_INVALID
42  };
43}
44}
45
46// Pin the vtable to this file.
47void XCoreInstrInfo::anchor() {}
48
49XCoreInstrInfo::XCoreInstrInfo()
50  : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
51    RI() {
52}
53
54static bool isZeroImm(const MachineOperand &op) {
55  return op.isImm() && op.getImm() == 0;
56}
57
58/// isLoadFromStackSlot - If the specified machine instruction is a direct
59/// load from a stack slot, return the virtual or physical register number of
60/// the destination along with the FrameIndex of the loaded stack slot.  If
61/// not, return 0.  This predicate must return 0 if the instruction has
62/// any side effects other than loading from the stack slot.
63unsigned
64XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
65  int Opcode = MI->getOpcode();
66  if (Opcode == XCore::LDWFI)
67  {
68    if ((MI->getOperand(1).isFI()) && // is a stack slot
69        (MI->getOperand(2).isImm()) &&  // the imm is zero
70        (isZeroImm(MI->getOperand(2))))
71    {
72      FrameIndex = MI->getOperand(1).getIndex();
73      return MI->getOperand(0).getReg();
74    }
75  }
76  return 0;
77}
78
79  /// isStoreToStackSlot - If the specified machine instruction is a direct
80  /// store to a stack slot, return the virtual or physical register number of
81  /// the source reg along with the FrameIndex of the loaded stack slot.  If
82  /// not, return 0.  This predicate must return 0 if the instruction has
83  /// any side effects other than storing to the stack slot.
84unsigned
85XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
86                                   int &FrameIndex) const {
87  int Opcode = MI->getOpcode();
88  if (Opcode == XCore::STWFI)
89  {
90    if ((MI->getOperand(1).isFI()) && // is a stack slot
91        (MI->getOperand(2).isImm()) &&  // the imm is zero
92        (isZeroImm(MI->getOperand(2))))
93    {
94      FrameIndex = MI->getOperand(1).getIndex();
95      return MI->getOperand(0).getReg();
96    }
97  }
98  return 0;
99}
100
101//===----------------------------------------------------------------------===//
102// Branch Analysis
103//===----------------------------------------------------------------------===//
104
105static inline bool IsBRU(unsigned BrOpc) {
106  return BrOpc == XCore::BRFU_u6
107      || BrOpc == XCore::BRFU_lu6
108      || BrOpc == XCore::BRBU_u6
109      || BrOpc == XCore::BRBU_lu6;
110}
111
112static inline bool IsBRT(unsigned BrOpc) {
113  return BrOpc == XCore::BRFT_ru6
114      || BrOpc == XCore::BRFT_lru6
115      || BrOpc == XCore::BRBT_ru6
116      || BrOpc == XCore::BRBT_lru6;
117}
118
119static inline bool IsBRF(unsigned BrOpc) {
120  return BrOpc == XCore::BRFF_ru6
121      || BrOpc == XCore::BRFF_lru6
122      || BrOpc == XCore::BRBF_ru6
123      || BrOpc == XCore::BRBF_lru6;
124}
125
126static inline bool IsCondBranch(unsigned BrOpc) {
127  return IsBRF(BrOpc) || IsBRT(BrOpc);
128}
129
130static inline bool IsBR_JT(unsigned BrOpc) {
131  return BrOpc == XCore::BR_JT
132      || BrOpc == XCore::BR_JT32;
133}
134
135/// GetCondFromBranchOpc - Return the XCore CC that matches
136/// the correspondent Branch instruction opcode.
137static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
138{
139  if (IsBRT(BrOpc)) {
140    return XCore::COND_TRUE;
141  } else if (IsBRF(BrOpc)) {
142    return XCore::COND_FALSE;
143  } else {
144    return XCore::COND_INVALID;
145  }
146}
147
148/// GetCondBranchFromCond - Return the Branch instruction
149/// opcode that matches the cc.
150static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
151{
152  switch (CC) {
153  default: llvm_unreachable("Illegal condition code!");
154  case XCore::COND_TRUE   : return XCore::BRFT_lru6;
155  case XCore::COND_FALSE  : return XCore::BRFF_lru6;
156  }
157}
158
159/// GetOppositeBranchCondition - Return the inverse of the specified
160/// condition, e.g. turning COND_E to COND_NE.
161static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
162{
163  switch (CC) {
164  default: llvm_unreachable("Illegal condition code!");
165  case XCore::COND_TRUE   : return XCore::COND_FALSE;
166  case XCore::COND_FALSE  : return XCore::COND_TRUE;
167  }
168}
169
170/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
171/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
172/// implemented for a target).  Upon success, this returns false and returns
173/// with the following information in various cases:
174///
175/// 1. If this block ends with no branches (it just falls through to its succ)
176///    just return false, leaving TBB/FBB null.
177/// 2. If this block ends with only an unconditional branch, it sets TBB to be
178///    the destination block.
179/// 3. If this block ends with an conditional branch and it falls through to
180///    an successor block, it sets TBB to be the branch destination block and a
181///    list of operands that evaluate the condition. These
182///    operands can be passed to other TargetInstrInfo methods to create new
183///    branches.
184/// 4. If this block ends with an conditional branch and an unconditional
185///    block, it returns the 'true' destination in TBB, the 'false' destination
186///    in FBB, and a list of operands that evaluate the condition. These
187///    operands can be passed to other TargetInstrInfo methods to create new
188///    branches.
189///
190/// Note that RemoveBranch and InsertBranch must be implemented to support
191/// cases where this method returns success.
192///
193bool
194XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
195                              MachineBasicBlock *&FBB,
196                              SmallVectorImpl<MachineOperand> &Cond,
197                              bool AllowModify) const {
198  // If the block has no terminators, it just falls into the block after it.
199  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
200  if (I == MBB.end())
201    return false;
202
203  if (!isUnpredicatedTerminator(I))
204    return false;
205
206  // Get the last instruction in the block.
207  MachineInstr *LastInst = I;
208
209  // If there is only one terminator instruction, process it.
210  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
211    if (IsBRU(LastInst->getOpcode())) {
212      TBB = LastInst->getOperand(0).getMBB();
213      return false;
214    }
215
216    XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
217    if (BranchCode == XCore::COND_INVALID)
218      return true;  // Can't handle indirect branch.
219
220    // Conditional branch
221    // Block ends with fall-through condbranch.
222
223    TBB = LastInst->getOperand(1).getMBB();
224    Cond.push_back(MachineOperand::CreateImm(BranchCode));
225    Cond.push_back(LastInst->getOperand(0));
226    return false;
227  }
228
229  // Get the instruction before it if it's a terminator.
230  MachineInstr *SecondLastInst = I;
231
232  // If there are three terminators, we don't know what sort of block this is.
233  if (SecondLastInst && I != MBB.begin() &&
234      isUnpredicatedTerminator(--I))
235    return true;
236
237  unsigned SecondLastOpc    = SecondLastInst->getOpcode();
238  XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
239
240  // If the block ends with conditional branch followed by unconditional,
241  // handle it.
242  if (BranchCode != XCore::COND_INVALID
243    && IsBRU(LastInst->getOpcode())) {
244
245    TBB = SecondLastInst->getOperand(1).getMBB();
246    Cond.push_back(MachineOperand::CreateImm(BranchCode));
247    Cond.push_back(SecondLastInst->getOperand(0));
248
249    FBB = LastInst->getOperand(0).getMBB();
250    return false;
251  }
252
253  // If the block ends with two unconditional branches, handle it.  The second
254  // one is not executed, so remove it.
255  if (IsBRU(SecondLastInst->getOpcode()) &&
256      IsBRU(LastInst->getOpcode())) {
257    TBB = SecondLastInst->getOperand(0).getMBB();
258    I = LastInst;
259    if (AllowModify)
260      I->eraseFromParent();
261    return false;
262  }
263
264  // Likewise if it ends with a branch table followed by an unconditional branch.
265  if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
266    I = LastInst;
267    if (AllowModify)
268      I->eraseFromParent();
269    return true;
270  }
271
272  // Otherwise, can't handle this.
273  return true;
274}
275
276unsigned
277XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
278                             MachineBasicBlock *FBB,
279                             ArrayRef<MachineOperand> Cond,
280                             DebugLoc DL)const{
281  // Shouldn't be a fall through.
282  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
283  assert((Cond.size() == 2 || Cond.size() == 0) &&
284         "Unexpected number of components!");
285
286  if (!FBB) { // One way branch.
287    if (Cond.empty()) {
288      // Unconditional branch
289      BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
290    } else {
291      // Conditional branch.
292      unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
293      BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
294                             .addMBB(TBB);
295    }
296    return 1;
297  }
298
299  // Two-way Conditional branch.
300  assert(Cond.size() == 2 && "Unexpected number of components!");
301  unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
302  BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
303                         .addMBB(TBB);
304  BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
305  return 2;
306}
307
308unsigned
309XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
310  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
311  if (I == MBB.end())
312    return 0;
313
314  if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
315    return 0;
316
317  // Remove the branch.
318  I->eraseFromParent();
319
320  I = MBB.end();
321
322  if (I == MBB.begin()) return 1;
323  --I;
324  if (!IsCondBranch(I->getOpcode()))
325    return 1;
326
327  // Remove the branch.
328  I->eraseFromParent();
329  return 2;
330}
331
332void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
333                                 MachineBasicBlock::iterator I, DebugLoc DL,
334                                 unsigned DestReg, unsigned SrcReg,
335                                 bool KillSrc) const {
336  bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
337  bool GRSrc  = XCore::GRRegsRegClass.contains(SrcReg);
338
339  if (GRDest && GRSrc) {
340    BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
341      .addReg(SrcReg, getKillRegState(KillSrc))
342      .addImm(0);
343    return;
344  }
345
346  if (GRDest && SrcReg == XCore::SP) {
347    BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
348    return;
349  }
350
351  if (DestReg == XCore::SP && GRSrc) {
352    BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
353      .addReg(SrcReg, getKillRegState(KillSrc));
354    return;
355  }
356  llvm_unreachable("Impossible reg-to-reg copy");
357}
358
359void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
360                                         MachineBasicBlock::iterator I,
361                                         unsigned SrcReg, bool isKill,
362                                         int FrameIndex,
363                                         const TargetRegisterClass *RC,
364                                         const TargetRegisterInfo *TRI) const
365{
366  DebugLoc DL;
367  if (I != MBB.end() && !I->isDebugValue())
368    DL = I->getDebugLoc();
369  MachineFunction *MF = MBB.getParent();
370  const MachineFrameInfo &MFI = *MF->getFrameInfo();
371  MachineMemOperand *MMO = MF->getMachineMemOperand(
372      MachinePointerInfo::getFixedStack(*MF, FrameIndex),
373      MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
374      MFI.getObjectAlignment(FrameIndex));
375  BuildMI(MBB, I, DL, get(XCore::STWFI))
376    .addReg(SrcReg, getKillRegState(isKill))
377    .addFrameIndex(FrameIndex)
378    .addImm(0)
379    .addMemOperand(MMO);
380}
381
382void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
383                                          MachineBasicBlock::iterator I,
384                                          unsigned DestReg, int FrameIndex,
385                                          const TargetRegisterClass *RC,
386                                          const TargetRegisterInfo *TRI) const
387{
388  DebugLoc DL;
389  if (I != MBB.end() && !I->isDebugValue())
390    DL = I->getDebugLoc();
391  MachineFunction *MF = MBB.getParent();
392  const MachineFrameInfo &MFI = *MF->getFrameInfo();
393  MachineMemOperand *MMO = MF->getMachineMemOperand(
394      MachinePointerInfo::getFixedStack(*MF, FrameIndex),
395      MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
396      MFI.getObjectAlignment(FrameIndex));
397  BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
398    .addFrameIndex(FrameIndex)
399    .addImm(0)
400    .addMemOperand(MMO);
401}
402
403/// ReverseBranchCondition - Return the inverse opcode of the
404/// specified Branch instruction.
405bool XCoreInstrInfo::
406ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
407  assert((Cond.size() == 2) &&
408          "Invalid XCore branch condition!");
409  Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
410  return false;
411}
412
413static inline bool isImmU6(unsigned val) {
414  return val < (1 << 6);
415}
416
417static inline bool isImmU16(unsigned val) {
418  return val < (1 << 16);
419}
420
421static bool isImmMskBitp(unsigned val) {
422  if (!isMask_32(val)) {
423    return false;
424  }
425  int N = Log2_32(val) + 1;
426  return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
427}
428
429MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
430                                              MachineBasicBlock &MBB,
431                                              MachineBasicBlock::iterator MI,
432                                              unsigned Reg, uint64_t Value) const {
433  DebugLoc dl;
434  if (MI != MBB.end() && !MI->isDebugValue())
435    dl = MI->getDebugLoc();
436  if (isImmMskBitp(Value)) {
437    int N = Log2_32(Value) + 1;
438    return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)
439        .addImm(N)
440        .getInstr();
441  }
442  if (isImmU16(Value)) {
443    int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
444    return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
445  }
446  MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
447  const Constant *C = ConstantInt::get(
448        Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
449  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
450  return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
451      .addConstantPoolIndex(Idx)
452      .getInstr();
453}
454