1// Copyright 2013 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// CPU specific code for arm independent of OS goes here.
6
7#if V8_TARGET_ARCH_ARM64
8
9#include "src/arm64/utils-arm64.h"
10#include "src/assembler.h"
11
12namespace v8 {
13namespace internal {
14
15class CacheLineSizes {
16 public:
17  CacheLineSizes() {
18#ifdef USE_SIMULATOR
19    cache_type_register_ = 0;
20#else
21    // Copy the content of the cache type register to a core register.
22    __asm__ __volatile__("mrs %x[ctr], ctr_el0"  // NOLINT
23                         : [ctr] "=r"(cache_type_register_));
24#endif
25  }
26
27  uint32_t icache_line_size() const { return ExtractCacheLineSize(0); }
28  uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); }
29
30 private:
31  uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
32    // The cache type register holds the size of cache lines in words as a
33    // power of two.
34    return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
35  }
36
37  uint32_t cache_type_register_;
38};
39
40void CpuFeatures::FlushICache(void* address, size_t length) {
41#ifdef V8_HOST_ARCH_ARM64
42  // The code below assumes user space cache operations are allowed. The goal
43  // of this routine is to make sure the code generated is visible to the I
44  // side of the CPU.
45
46  uintptr_t start = reinterpret_cast<uintptr_t>(address);
47  // Sizes will be used to generate a mask big enough to cover a pointer.
48  CacheLineSizes sizes;
49  uintptr_t dsize = sizes.dcache_line_size();
50  uintptr_t isize = sizes.icache_line_size();
51  // Cache line sizes are always a power of 2.
52  DCHECK(CountSetBits(dsize, 64) == 1);
53  DCHECK(CountSetBits(isize, 64) == 1);
54  uintptr_t dstart = start & ~(dsize - 1);
55  uintptr_t istart = start & ~(isize - 1);
56  uintptr_t end = start + length;
57
58  __asm__ __volatile__ (  // NOLINT
59    // Clean every line of the D cache containing the target data.
60    "0:                                \n\t"
61    // dc       : Data Cache maintenance
62    //    c     : Clean
63    //     i    : Invalidate
64    //      va  : by (Virtual) Address
65    //        c : to the point of Coherency
66    // See ARM DDI 0406B page B2-12 for more information.
67    // We would prefer to use "cvau" (clean to the point of unification) here
68    // but we use "civac" to work around Cortex-A53 errata 819472, 826319,
69    // 827319 and 824069.
70    "dc   civac, %[dline]               \n\t"
71    "add  %[dline], %[dline], %[dsize]  \n\t"
72    "cmp  %[dline], %[end]              \n\t"
73    "b.lt 0b                            \n\t"
74    // Barrier to make sure the effect of the code above is visible to the rest
75    // of the world.
76    // dsb    : Data Synchronisation Barrier
77    //    ish : Inner SHareable domain
78    // The point of unification for an Inner Shareable shareability domain is
79    // the point by which the instruction and data caches of all the processors
80    // in that Inner Shareable shareability domain are guaranteed to see the
81    // same copy of a memory location.  See ARM DDI 0406B page B2-12 for more
82    // information.
83    "dsb  ish                           \n\t"
84    // Invalidate every line of the I cache containing the target data.
85    "1:                                 \n\t"
86    // ic      : instruction cache maintenance
87    //    i    : invalidate
88    //     va  : by address
89    //       u : to the point of unification
90    "ic   ivau, %[iline]                \n\t"
91    "add  %[iline], %[iline], %[isize]  \n\t"
92    "cmp  %[iline], %[end]              \n\t"
93    "b.lt 1b                            \n\t"
94    // Barrier to make sure the effect of the code above is visible to the rest
95    // of the world.
96    "dsb  ish                           \n\t"
97    // Barrier to ensure any prefetching which happened before this code is
98    // discarded.
99    // isb : Instruction Synchronisation Barrier
100    "isb                                \n\t"
101    : [dline] "+r" (dstart),
102      [iline] "+r" (istart)
103    : [dsize] "r"  (dsize),
104      [isize] "r"  (isize),
105      [end]   "r"  (end)
106    // This code does not write to memory but without the dependency gcc might
107    // move this code before the code is generated.
108    : "cc", "memory"
109  );  // NOLINT
110#endif  // V8_HOST_ARCH_ARM64
111}
112
113}  // namespace internal
114}  // namespace v8
115
116#endif  // V8_TARGET_ARCH_ARM64
117