1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_PPC_CONSTANTS_PPC_H_
6#define V8_PPC_CONSTANTS_PPC_H_
7
8#include <stdint.h>
9
10#include "src/base/logging.h"
11#include "src/base/macros.h"
12#include "src/globals.h"
13
14namespace v8 {
15namespace internal {
16
17// Number of registers
18const int kNumRegisters = 32;
19
20// FP support.
21const int kNumDoubleRegisters = 32;
22
23const int kNoRegister = -1;
24
25// Used in embedded constant pool builder - max reach in bits for
26// various load instructions (one less due to unsigned)
27const int kLoadPtrMaxReachBits = 15;
28const int kLoadDoubleMaxReachBits = 15;
29
30// sign-extend the least significant 16-bits of value <imm>
31#define SIGN_EXT_IMM16(imm) ((static_cast<int>(imm) << 16) >> 16)
32
33// sign-extend the least significant 26-bits of value <imm>
34#define SIGN_EXT_IMM26(imm) ((static_cast<int>(imm) << 6) >> 6)
35
36// -----------------------------------------------------------------------------
37// Conditions.
38
39// Defines constants and accessor classes to assemble, disassemble and
40// simulate PPC instructions.
41//
42// Section references in the code refer to the "PowerPC Microprocessor
43// Family: The Programmer.s Reference Guide" from 10/95
44// https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF778525699600741775/$file/prg.pdf
45//
46
47// Constants for specific fields are defined in their respective named enums.
48// General constants are in an anonymous enum in class Instr.
49enum Condition {
50  kNoCondition = -1,
51  eq = 0,         // Equal.
52  ne = 1,         // Not equal.
53  ge = 2,         // Greater or equal.
54  lt = 3,         // Less than.
55  gt = 4,         // Greater than.
56  le = 5,         // Less then or equal
57  unordered = 6,  // Floating-point unordered
58  ordered = 7,
59  overflow = 8,  // Summary overflow
60  nooverflow = 9,
61  al = 10  // Always.
62};
63
64
65inline Condition NegateCondition(Condition cond) {
66  DCHECK(cond != al);
67  return static_cast<Condition>(cond ^ ne);
68}
69
70
71// Commute a condition such that {a cond b == b cond' a}.
72inline Condition CommuteCondition(Condition cond) {
73  switch (cond) {
74    case lt:
75      return gt;
76    case gt:
77      return lt;
78    case ge:
79      return le;
80    case le:
81      return ge;
82    default:
83      return cond;
84  }
85}
86
87// -----------------------------------------------------------------------------
88// Instructions encoding.
89
90// Instr is merely used by the Assembler to distinguish 32bit integers
91// representing instructions from usual 32 bit values.
92// Instruction objects are pointers to 32bit values, and provide methods to
93// access the various ISA fields.
94typedef int32_t Instr;
95
96// Opcodes as defined in section 4.2 table 34 (32bit PowerPC)
97enum Opcode {
98  TWI = 3 << 26,       // Trap Word Immediate
99  MULLI = 7 << 26,     // Multiply Low Immediate
100  SUBFIC = 8 << 26,    // Subtract from Immediate Carrying
101  CMPLI = 10 << 26,    // Compare Logical Immediate
102  CMPI = 11 << 26,     // Compare Immediate
103  ADDIC = 12 << 26,    // Add Immediate Carrying
104  ADDICx = 13 << 26,   // Add Immediate Carrying and Record
105  ADDI = 14 << 26,     // Add Immediate
106  ADDIS = 15 << 26,    // Add Immediate Shifted
107  BCX = 16 << 26,      // Branch Conditional
108  SC = 17 << 26,       // System Call
109  BX = 18 << 26,       // Branch
110  EXT1 = 19 << 26,     // Extended code set 1
111  RLWIMIX = 20 << 26,  // Rotate Left Word Immediate then Mask Insert
112  RLWINMX = 21 << 26,  // Rotate Left Word Immediate then AND with Mask
113  RLWNMX = 23 << 26,   // Rotate Left Word then AND with Mask
114  ORI = 24 << 26,      // OR Immediate
115  ORIS = 25 << 26,     // OR Immediate Shifted
116  XORI = 26 << 26,     // XOR Immediate
117  XORIS = 27 << 26,    // XOR Immediate Shifted
118  ANDIx = 28 << 26,    // AND Immediate
119  ANDISx = 29 << 26,   // AND Immediate Shifted
120  EXT5 = 30 << 26,     // Extended code set 5 - 64bit only
121  EXT2 = 31 << 26,     // Extended code set 2
122  LWZ = 32 << 26,      // Load Word and Zero
123  LWZU = 33 << 26,     // Load Word with Zero Update
124  LBZ = 34 << 26,      // Load Byte and Zero
125  LBZU = 35 << 26,     // Load Byte and Zero with Update
126  STW = 36 << 26,      // Store
127  STWU = 37 << 26,     // Store Word with Update
128  STB = 38 << 26,      // Store Byte
129  STBU = 39 << 26,     // Store Byte with Update
130  LHZ = 40 << 26,      // Load Half and Zero
131  LHZU = 41 << 26,     // Load Half and Zero with Update
132  LHA = 42 << 26,      // Load Half Algebraic
133  LHAU = 43 << 26,     // Load Half Algebraic with Update
134  STH = 44 << 26,      // Store Half
135  STHU = 45 << 26,     // Store Half with Update
136  LMW = 46 << 26,      // Load Multiple Word
137  STMW = 47 << 26,     // Store Multiple Word
138  LFS = 48 << 26,      // Load Floating-Point Single
139  LFSU = 49 << 26,     // Load Floating-Point Single with Update
140  LFD = 50 << 26,      // Load Floating-Point Double
141  LFDU = 51 << 26,     // Load Floating-Point Double with Update
142  STFS = 52 << 26,     // Store Floating-Point Single
143  STFSU = 53 << 26,    // Store Floating-Point Single with Update
144  STFD = 54 << 26,     // Store Floating-Point Double
145  STFDU = 55 << 26,    // Store Floating-Point Double with Update
146  LD = 58 << 26,       // Load Double Word
147  EXT3 = 59 << 26,     // Extended code set 3
148  STD = 62 << 26,      // Store Double Word (optionally with Update)
149  EXT4 = 63 << 26      // Extended code set 4
150};
151
152// Bits 10-1
153enum OpcodeExt1 {
154  MCRF = 0 << 1,      // Move Condition Register Field
155  BCLRX = 16 << 1,    // Branch Conditional Link Register
156  CRNOR = 33 << 1,    // Condition Register NOR)
157  RFI = 50 << 1,      // Return from Interrupt
158  CRANDC = 129 << 1,  // Condition Register AND with Complement
159  ISYNC = 150 << 1,   // Instruction Synchronize
160  CRXOR = 193 << 1,   // Condition Register XOR
161  CRNAND = 225 << 1,  // Condition Register NAND
162  CRAND = 257 << 1,   // Condition Register AND
163  CREQV = 289 << 1,   // Condition Register Equivalent
164  CRORC = 417 << 1,   // Condition Register OR with Complement
165  CROR = 449 << 1,    // Condition Register OR
166  BCCTRX = 528 << 1   // Branch Conditional to Count Register
167};
168
169// Bits 9-1 or 10-1
170enum OpcodeExt2 {
171  CMP = 0 << 1,
172  TW = 4 << 1,
173  SUBFCX = 8 << 1,
174  ADDCX = 10 << 1,
175  MULHWUX = 11 << 1,
176  ISEL = 15 << 1,
177  MFCR = 19 << 1,
178  LWARX = 20 << 1,
179  LDX = 21 << 1,
180  LWZX = 23 << 1,  // load word zero w/ x-form
181  SLWX = 24 << 1,
182  CNTLZWX = 26 << 1,
183  SLDX = 27 << 1,
184  ANDX = 28 << 1,
185  CMPL = 32 << 1,
186  SUBFX = 40 << 1,
187  MFVSRD = 51 << 1,  // Move From VSR Doubleword
188  LDUX = 53 << 1,
189  DCBST = 54 << 1,
190  LWZUX = 55 << 1,  // load word zero w/ update x-form
191  CNTLZDX = 58 << 1,
192  ANDCX = 60 << 1,
193  MULHWX = 75 << 1,
194  DCBF = 86 << 1,
195  LBZX = 87 << 1,  // load byte zero w/ x-form
196  NEGX = 104 << 1,
197  MFVSRWZ = 115 << 1,  // Move From VSR Word And Zero
198  LBZUX = 119 << 1,    // load byte zero w/ update x-form
199  NORX = 124 << 1,
200  SUBFEX = 136 << 1,
201  ADDEX = 138 << 1,
202  STDX = 149 << 1,
203  STWX = 151 << 1,    // store word w/ x-form
204  MTVSRD = 179 << 1,  // Move To VSR Doubleword
205  STDUX = 181 << 1,
206  STWUX = 183 << 1,    // store word w/ update x-form
207                       /*
208      MTCRF
209      MTMSR
210      STWCXx
211      SUBFZEX
212    */
213  ADDZEX = 202 << 1,   // Add to Zero Extended
214                       /*
215     MTSR
216   */
217  MTVSRWA = 211 << 1,  // Move To VSR Word Algebraic
218  STBX = 215 << 1,     // store byte w/ x-form
219  MULLD = 233 << 1,    // Multiply Low Double Word
220  MULLW = 235 << 1,    // Multiply Low Word
221  MTVSRWZ = 243 << 1,  // Move To VSR Word And Zero
222  STBUX = 247 << 1,    // store byte w/ update x-form
223  ADDX = 266 << 1,     // Add
224  LHZX = 279 << 1,     // load half-word zero w/ x-form
225  LHZUX = 311 << 1,    // load half-word zero w/ update x-form
226  LWAX = 341 << 1,     // load word algebraic w/ x-form
227  LHAX = 343 << 1,     // load half-word algebraic w/ x-form
228  LHAUX = 375 << 1,    // load half-word algebraic w/ update x-form
229  XORX = 316 << 1,     // Exclusive OR
230  MFSPR = 339 << 1,    // Move from Special-Purpose-Register
231  POPCNTW = 378 << 1,  // Population Count Words
232  STHX = 407 << 1,     // store half-word w/ x-form
233  ORC = 412 << 1,      // Or with Complement
234  STHUX = 439 << 1,    // store half-word w/ update x-form
235  ORX = 444 << 1,      // Or
236  DIVDU = 457 << 1,    // Divide Double Word Unsigned
237  DIVWU = 459 << 1,    // Divide Word Unsigned
238  MTSPR = 467 << 1,    // Move to Special-Purpose-Register
239  DIVD = 489 << 1,     // Divide Double Word
240  DIVW = 491 << 1,     // Divide Word
241  POPCNTD = 506 << 1,  // Population Count Doubleword
242
243  // Below represent bits 10-1  (any value >= 512)
244  LFSX = 535 << 1,    // load float-single w/ x-form
245  SRWX = 536 << 1,    // Shift Right Word
246  SRDX = 539 << 1,    // Shift Right Double Word
247  LFSUX = 567 << 1,   // load float-single w/ update x-form
248  SYNC = 598 << 1,    // Synchronize
249  LFDX = 599 << 1,    // load float-double w/ x-form
250  LFDUX = 631 << 1,   // load float-double w/ update X-form
251  STFSX = 663 << 1,   // store float-single w/ x-form
252  STFSUX = 695 << 1,  // store float-single w/ update x-form
253  STFDX = 727 << 1,   // store float-double w/ x-form
254  STFDUX = 759 << 1,  // store float-double w/ update x-form
255  SRAW = 792 << 1,    // Shift Right Algebraic Word
256  SRAD = 794 << 1,    // Shift Right Algebraic Double Word
257  SRAWIX = 824 << 1,  // Shift Right Algebraic Word Immediate
258  SRADIX = 413 << 2,  // Shift Right Algebraic Double Word Immediate
259  EXTSH = 922 << 1,   // Extend Sign Halfword
260  EXTSB = 954 << 1,   // Extend Sign Byte
261  ICBI = 982 << 1,    // Instruction Cache Block Invalidate
262  EXTSW = 986 << 1    // Extend Sign Word
263};
264
265// Some use Bits 10-1 and other only 5-1 for the opcode
266enum OpcodeExt4 {
267  // Bits 5-1
268  FDIV = 18 << 1,   // Floating Divide
269  FSUB = 20 << 1,   // Floating Subtract
270  FADD = 21 << 1,   // Floating Add
271  FSQRT = 22 << 1,  // Floating Square Root
272  FSEL = 23 << 1,   // Floating Select
273  FMUL = 25 << 1,   // Floating Multiply
274  FMSUB = 28 << 1,  // Floating Multiply-Subtract
275  FMADD = 29 << 1,  // Floating Multiply-Add
276
277  // Bits 10-1
278  FCMPU = 0 << 1,      // Floating Compare Unordered
279  FRSP = 12 << 1,      // Floating-Point Rounding
280  FCTIW = 14 << 1,     // Floating Convert to Integer Word X-form
281  FCTIWZ = 15 << 1,    // Floating Convert to Integer Word with Round to Zero
282  MTFSB1 = 38 << 1,    // Move to FPSCR Bit 1
283  FNEG = 40 << 1,      // Floating Negate
284  MCRFS = 64 << 1,     // Move to Condition Register from FPSCR
285  MTFSB0 = 70 << 1,    // Move to FPSCR Bit 0
286  FMR = 72 << 1,       // Floating Move Register
287  MTFSFI = 134 << 1,   // Move to FPSCR Field Immediate
288  FABS = 264 << 1,     // Floating Absolute Value
289  FRIN = 392 << 1,     // Floating Round to Integer Nearest
290  FRIZ = 424 << 1,     // Floating Round to Integer Toward Zero
291  FRIP = 456 << 1,     // Floating Round to Integer Plus
292  FRIM = 488 << 1,     // Floating Round to Integer Minus
293  MFFS = 583 << 1,     // move from FPSCR x-form
294  MTFSF = 711 << 1,    // move to FPSCR fields XFL-form
295  FCTID = 814 << 1,    // Floating convert to integer doubleword
296  FCTIDZ = 815 << 1,   // ^^^ with round toward zero
297  FCFID = 846 << 1,    // Floating convert from integer doubleword
298  FCTIDU = 942 << 1,   // Floating convert to integer doubleword unsigned
299  FCTIDUZ = 943 << 1,  // ^^^ with round toward zero
300  FCFIDU = 974 << 1    // Floating convert from integer doubleword unsigned
301};
302
303enum OpcodeExt5 {
304  // Bits 4-2
305  RLDICL = 0 << 1,  // Rotate Left Double Word Immediate then Clear Left
306  RLDICR = 2 << 1,  // Rotate Left Double Word Immediate then Clear Right
307  RLDIC = 4 << 1,   // Rotate Left Double Word Immediate then Clear
308  RLDIMI = 6 << 1,  // Rotate Left Double Word Immediate then Mask Insert
309  // Bits 4-1
310  RLDCL = 8 << 1,  // Rotate Left Double Word then Clear Left
311  RLDCR = 9 << 1   // Rotate Left Double Word then Clear Right
312};
313
314// Instruction encoding bits and masks.
315enum {
316  // Instruction encoding bit
317  B1 = 1 << 1,
318  B4 = 1 << 4,
319  B5 = 1 << 5,
320  B7 = 1 << 7,
321  B8 = 1 << 8,
322  B9 = 1 << 9,
323  B12 = 1 << 12,
324  B18 = 1 << 18,
325  B19 = 1 << 19,
326  B20 = 1 << 20,
327  B22 = 1 << 22,
328  B23 = 1 << 23,
329  B24 = 1 << 24,
330  B25 = 1 << 25,
331  B26 = 1 << 26,
332  B27 = 1 << 27,
333  B28 = 1 << 28,
334  B6 = 1 << 6,
335  B10 = 1 << 10,
336  B11 = 1 << 11,
337  B16 = 1 << 16,
338  B17 = 1 << 17,
339  B21 = 1 << 21,
340
341  // Instruction bit masks
342  kCondMask = 0x1F << 21,
343  kOff12Mask = (1 << 12) - 1,
344  kImm24Mask = (1 << 24) - 1,
345  kOff16Mask = (1 << 16) - 1,
346  kImm16Mask = (1 << 16) - 1,
347  kImm26Mask = (1 << 26) - 1,
348  kBOfieldMask = 0x1f << 21,
349  kOpcodeMask = 0x3f << 26,
350  kExt1OpcodeMask = 0x3ff << 1,
351  kExt2OpcodeMask = 0x3ff << 1,
352  kExt2OpcodeVariant2Mask = 0x1ff << 2,
353  kExt5OpcodeMask = 0x3 << 2,
354  kBOMask = 0x1f << 21,
355  kBIMask = 0x1F << 16,
356  kBDMask = 0x14 << 2,
357  kAAMask = 0x01 << 1,
358  kLKMask = 0x01,
359  kRCMask = 0x01,
360  kTOMask = 0x1f << 21
361};
362
363// -----------------------------------------------------------------------------
364// Addressing modes and instruction variants.
365
366// Overflow Exception
367enum OEBit {
368  SetOE = 1 << 10,   // Set overflow exception
369  LeaveOE = 0 << 10  // No overflow exception
370};
371
372// Record bit
373enum RCBit {   // Bit 0
374  SetRC = 1,   // LT,GT,EQ,SO
375  LeaveRC = 0  // None
376};
377
378// Link bit
379enum LKBit {   // Bit 0
380  SetLK = 1,   // Load effective address of next instruction
381  LeaveLK = 0  // No action
382};
383
384enum BOfield {        // Bits 25-21
385  DCBNZF = 0 << 21,   // Decrement CTR; branch if CTR != 0 and condition false
386  DCBEZF = 2 << 21,   // Decrement CTR; branch if CTR == 0 and condition false
387  BF = 4 << 21,       // Branch if condition false
388  DCBNZT = 8 << 21,   // Decrement CTR; branch if CTR != 0 and condition true
389  DCBEZT = 10 << 21,  // Decrement CTR; branch if CTR == 0 and condition true
390  BT = 12 << 21,      // Branch if condition true
391  DCBNZ = 16 << 21,   // Decrement CTR; branch if CTR != 0
392  DCBEZ = 18 << 21,   // Decrement CTR; branch if CTR == 0
393  BA = 20 << 21       // Branch always
394};
395
396#if V8_OS_AIX
397#undef CR_LT
398#undef CR_GT
399#undef CR_EQ
400#undef CR_SO
401#endif
402
403enum CRBit { CR_LT = 0, CR_GT = 1, CR_EQ = 2, CR_SO = 3, CR_FU = 3 };
404
405#define CRWIDTH 4
406
407// These are the documented bit positions biased down by 32
408enum FPSCRBit {
409  VXSOFT = 21,  // 53: Software-Defined Condition
410  VXSQRT = 22,  // 54: Invalid Square Root
411  VXCVI = 23    // 55: Invalid Integer Convert
412};
413
414// -----------------------------------------------------------------------------
415// Supervisor Call (svc) specific support.
416
417// Special Software Interrupt codes when used in the presence of the PPC
418// simulator.
419// svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
420// standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
421enum SoftwareInterruptCodes {
422  // transition to C code
423  kCallRtRedirected = 0x10,
424  // break point
425  kBreakpoint = 0x821008,  // bits23-0 of 0x7d821008 = twge r2, r2
426  // stop
427  kStopCode = 1 << 23
428};
429const uint32_t kStopCodeMask = kStopCode - 1;
430const uint32_t kMaxStopCode = kStopCode - 1;
431const int32_t kDefaultStopCode = -1;
432
433// FP rounding modes.
434enum FPRoundingMode {
435  RN = 0,  // Round to Nearest.
436  RZ = 1,  // Round towards zero.
437  RP = 2,  // Round towards Plus Infinity.
438  RM = 3,  // Round towards Minus Infinity.
439
440  // Aliases.
441  kRoundToNearest = RN,
442  kRoundToZero = RZ,
443  kRoundToPlusInf = RP,
444  kRoundToMinusInf = RM
445};
446
447const uint32_t kFPRoundingModeMask = 3;
448
449enum CheckForInexactConversion {
450  kCheckForInexactConversion,
451  kDontCheckForInexactConversion
452};
453
454// -----------------------------------------------------------------------------
455// Specific instructions, constants, and masks.
456// These constants are declared in assembler-arm.cc, as they use named registers
457// and other constants.
458
459
460// add(sp, sp, 4) instruction (aka Pop())
461extern const Instr kPopInstruction;
462
463// str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))
464// register r is not encoded.
465extern const Instr kPushRegPattern;
466
467// ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))
468// register r is not encoded.
469extern const Instr kPopRegPattern;
470
471// use TWI to indicate redirection call for simulation mode
472const Instr rtCallRedirInstr = TWI;
473
474// -----------------------------------------------------------------------------
475// Instruction abstraction.
476
477// The class Instruction enables access to individual fields defined in the PPC
478// architecture instruction set encoding.
479// Note that the Assembler uses typedef int32_t Instr.
480//
481// Example: Test whether the instruction at ptr does set the condition code
482// bits.
483//
484// bool InstructionSetsConditionCodes(byte* ptr) {
485//   Instruction* instr = Instruction::At(ptr);
486//   int type = instr->TypeValue();
487//   return ((type == 0) || (type == 1)) && instr->HasS();
488// }
489//
490class Instruction {
491 public:
492  enum { kInstrSize = 4, kInstrSizeLog2 = 2, kPCReadOffset = 8 };
493
494// Helper macro to define static accessors.
495// We use the cast to char* trick to bypass the strict anti-aliasing rules.
496#define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \
497  static inline return_type Name(Instr instr) {          \
498    char* temp = reinterpret_cast<char*>(&instr);        \
499    return reinterpret_cast<Instruction*>(temp)->Name(); \
500  }
501
502#define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name)
503
504  // Get the raw instruction bits.
505  inline Instr InstructionBits() const {
506    return *reinterpret_cast<const Instr*>(this);
507  }
508
509  // Set the raw instruction bits to value.
510  inline void SetInstructionBits(Instr value) {
511    *reinterpret_cast<Instr*>(this) = value;
512  }
513
514  // Read one particular bit out of the instruction bits.
515  inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
516
517  // Read a bit field's value out of the instruction bits.
518  inline int Bits(int hi, int lo) const {
519    return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
520  }
521
522  // Read a bit field out of the instruction bits.
523  inline int BitField(int hi, int lo) const {
524    return InstructionBits() & (((2 << (hi - lo)) - 1) << lo);
525  }
526
527  // Static support.
528
529  // Read one particular bit out of the instruction bits.
530  static inline int Bit(Instr instr, int nr) { return (instr >> nr) & 1; }
531
532  // Read the value of a bit field out of the instruction bits.
533  static inline int Bits(Instr instr, int hi, int lo) {
534    return (instr >> lo) & ((2 << (hi - lo)) - 1);
535  }
536
537
538  // Read a bit field out of the instruction bits.
539  static inline int BitField(Instr instr, int hi, int lo) {
540    return instr & (((2 << (hi - lo)) - 1) << lo);
541  }
542
543  inline int RSValue() const { return Bits(25, 21); }
544  inline int RTValue() const { return Bits(25, 21); }
545  inline int RAValue() const { return Bits(20, 16); }
546  DECLARE_STATIC_ACCESSOR(RAValue);
547  inline int RBValue() const { return Bits(15, 11); }
548  DECLARE_STATIC_ACCESSOR(RBValue);
549  inline int RCValue() const { return Bits(10, 6); }
550  DECLARE_STATIC_ACCESSOR(RCValue);
551
552  inline int OpcodeValue() const { return static_cast<Opcode>(Bits(31, 26)); }
553  inline Opcode OpcodeField() const {
554    return static_cast<Opcode>(BitField(24, 21));
555  }
556
557  // Fields used in Software interrupt instructions
558  inline SoftwareInterruptCodes SvcValue() const {
559    return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
560  }
561
562  // Instructions are read of out a code stream. The only way to get a
563  // reference to an instruction is to convert a pointer. There is no way
564  // to allocate or create instances of class Instruction.
565  // Use the At(pc) function to create references to Instruction.
566  static Instruction* At(byte* pc) {
567    return reinterpret_cast<Instruction*>(pc);
568  }
569
570
571 private:
572  // We need to prevent the creation of instances of class Instruction.
573  DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
574};
575
576
577// Helper functions for converting between register numbers and names.
578class Registers {
579 public:
580  // Lookup the register number for the name provided.
581  static int Number(const char* name);
582
583 private:
584  static const char* names_[kNumRegisters];
585};
586
587// Helper functions for converting between FP register numbers and names.
588class DoubleRegisters {
589 public:
590  // Lookup the register number for the name provided.
591  static int Number(const char* name);
592
593 private:
594  static const char* names_[kNumDoubleRegisters];
595};
596}  // namespace internal
597}  // namespace v8
598
599#endif  // V8_PPC_CONSTANTS_PPC_H_
600