1#ifndef __UAPI_MSMB_ISP__
2#define __UAPI_MSMB_ISP__
3
4#include <linux/videodev2.h>
5
6#define MAX_PLANES_PER_STREAM 3
7#define MAX_NUM_STREAM 7
8
9#define ISP_VERSION_47        47
10#define ISP_VERSION_46        46
11#define ISP_VERSION_44        44
12#define ISP_VERSION_40        40
13#define ISP_VERSION_32        32
14#define ISP_NATIVE_BUF_BIT    (0x10000 << 0)
15#define ISP0_BIT              (0x10000 << 1)
16#define ISP1_BIT              (0x10000 << 2)
17#define ISP_META_CHANNEL_BIT  (0x10000 << 3)
18#define ISP_SCRATCH_BUF_BIT   (0x10000 << 4)
19#define ISP_OFFLINE_STATS_BIT (0x10000 << 5)
20#define ISP_STATS_STREAM_BIT  0x80000000
21
22struct msm_vfe_cfg_cmd_list;
23
24enum ISP_START_PIXEL_PATTERN {
25	ISP_BAYER_RGRGRG,
26	ISP_BAYER_GRGRGR,
27	ISP_BAYER_BGBGBG,
28	ISP_BAYER_GBGBGB,
29	ISP_YUV_YCbYCr,
30	ISP_YUV_YCrYCb,
31	ISP_YUV_CbYCrY,
32	ISP_YUV_CrYCbY,
33	ISP_PIX_PATTERN_MAX
34};
35
36enum msm_vfe_plane_fmt {
37	Y_PLANE,
38	CB_PLANE,
39	CR_PLANE,
40	CRCB_PLANE,
41	CBCR_PLANE,
42	VFE_PLANE_FMT_MAX
43};
44
45enum msm_vfe_input_src {
46	VFE_PIX_0,
47	VFE_RAW_0,
48	VFE_RAW_1,
49	VFE_RAW_2,
50	VFE_SRC_MAX,
51};
52
53enum msm_vfe_axi_stream_src {
54	PIX_ENCODER,
55	PIX_VIEWFINDER,
56	PIX_VIDEO,
57	CAMIF_RAW,
58	IDEAL_RAW,
59	RDI_INTF_0,
60	RDI_INTF_1,
61	RDI_INTF_2,
62	VFE_AXI_SRC_MAX
63};
64
65enum msm_vfe_frame_skip_pattern {
66	NO_SKIP,
67	EVERY_2FRAME,
68	EVERY_3FRAME,
69	EVERY_4FRAME,
70	EVERY_5FRAME,
71	EVERY_6FRAME,
72	EVERY_7FRAME,
73	EVERY_8FRAME,
74	EVERY_16FRAME,
75	EVERY_32FRAME,
76	SKIP_ALL,
77	SKIP_RANGE,
78	MAX_SKIP,
79};
80
81/*
82 * Define an unused period. When this period is set it means that the stream is
83 * stopped(i.e the pattern is 0). We don't track the current pattern, just the
84 * period defines what the pattern is, if period is this then pattern is 0 else
85 * pattern is 1
86 */
87#define MSM_VFE_STREAM_STOP_PERIOD 15
88
89enum msm_isp_stats_type {
90	MSM_ISP_STATS_AEC,   /* legacy based AEC */
91	MSM_ISP_STATS_AF,    /* legacy based AF */
92	MSM_ISP_STATS_AWB,   /* legacy based AWB */
93	MSM_ISP_STATS_RS,    /* legacy based RS */
94	MSM_ISP_STATS_CS,    /* legacy based CS */
95	MSM_ISP_STATS_IHIST, /* legacy based HIST */
96	MSM_ISP_STATS_SKIN,  /* legacy based SKIN */
97	MSM_ISP_STATS_BG,    /* Bayer Grids */
98	MSM_ISP_STATS_BF,    /* Bayer Focus */
99	MSM_ISP_STATS_BE,    /* Bayer Exposure*/
100	MSM_ISP_STATS_BHIST, /* Bayer Hist */
101	MSM_ISP_STATS_BF_SCALE,  /* Bayer Focus scale */
102	MSM_ISP_STATS_HDR_BE,    /* HDR Bayer Exposure */
103	MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */
104	MSM_ISP_STATS_AEC_BG,   /* AEC BG */
105	MSM_ISP_STATS_MAX    /* MAX */
106};
107
108/*
109 * @stats_type_mask: Stats type mask (enum msm_isp_stats_type).
110 * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src)
111 * @skip_mode: skip pattern, if skip mode is range only then min/max is used
112 * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE)
113 * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE)
114*/
115struct msm_isp_sw_framskip {
116	uint32_t stats_type_mask;
117	uint32_t stream_src_mask;
118	enum msm_vfe_frame_skip_pattern skip_mode;
119	uint32_t min_frame_id;
120	uint32_t max_frame_id;
121};
122
123enum msm_vfe_testgen_color_pattern {
124	COLOR_BAR_8_COLOR,
125	UNICOLOR_WHITE,
126	UNICOLOR_YELLOW,
127	UNICOLOR_CYAN,
128	UNICOLOR_GREEN,
129	UNICOLOR_MAGENTA,
130	UNICOLOR_RED,
131	UNICOLOR_BLUE,
132	UNICOLOR_BLACK,
133	MAX_COLOR,
134};
135
136enum msm_vfe_camif_input {
137	CAMIF_DISABLED,
138	CAMIF_PAD_REG_INPUT,
139	CAMIF_MIDDI_INPUT,
140	CAMIF_MIPI_INPUT,
141};
142
143struct msm_vfe_fetch_engine_cfg {
144	uint32_t input_format;
145	uint32_t buf_width;
146	uint32_t buf_height;
147	uint32_t fetch_width;
148	uint32_t fetch_height;
149	uint32_t x_offset;
150	uint32_t y_offset;
151	uint32_t buf_stride;
152};
153
154enum msm_vfe_camif_output_format {
155	CAMIF_QCOM_RAW,
156	CAMIF_MIPI_RAW,
157	CAMIF_PLAIN_8,
158	CAMIF_PLAIN_16,
159	CAMIF_MAX_FORMAT,
160};
161
162/*
163 * Camif output general configuration
164 */
165struct msm_vfe_camif_subsample_cfg {
166	uint32_t irq_subsample_period;
167	uint32_t irq_subsample_pattern;
168	uint32_t sof_counter_step;
169	uint32_t pixel_skip;
170	uint32_t line_skip;
171	uint32_t first_line;
172	uint32_t last_line;
173	uint32_t first_pixel;
174	uint32_t last_pixel;
175	enum msm_vfe_camif_output_format output_format;
176};
177
178/*
179 * Camif frame and window configuration
180 */
181struct msm_vfe_camif_cfg {
182	uint32_t lines_per_frame;
183	uint32_t pixels_per_line;
184	uint32_t first_pixel;
185	uint32_t last_pixel;
186	uint32_t first_line;
187	uint32_t last_line;
188	uint32_t epoch_line0;
189	uint32_t epoch_line1;
190	uint32_t is_split;
191	enum msm_vfe_camif_input camif_input;
192	struct msm_vfe_camif_subsample_cfg subsample_cfg;
193};
194
195struct msm_vfe_testgen_cfg {
196	uint32_t lines_per_frame;
197	uint32_t pixels_per_line;
198	uint32_t v_blank;
199	uint32_t h_blank;
200	enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
201	uint32_t rotate_period;
202	enum msm_vfe_testgen_color_pattern color_bar_pattern;
203	uint32_t burst_num_frame;
204};
205
206enum msm_vfe_inputmux {
207	CAMIF,
208	TESTGEN,
209	EXTERNAL_READ,
210};
211
212enum msm_vfe_stats_composite_group {
213	STATS_COMPOSITE_GRP_NONE,
214	STATS_COMPOSITE_GRP_1,
215	STATS_COMPOSITE_GRP_2,
216	STATS_COMPOSITE_GRP_MAX,
217};
218
219enum msm_vfe_hvx_streaming_cmd {
220	HVX_DISABLE,
221	HVX_ONE_WAY,
222	HVX_ROUND_TRIP
223};
224
225struct msm_vfe_pix_cfg {
226	struct msm_vfe_camif_cfg camif_cfg;
227	struct msm_vfe_testgen_cfg testgen_cfg;
228	struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
229	enum msm_vfe_inputmux input_mux;
230	enum ISP_START_PIXEL_PATTERN pixel_pattern;
231	uint32_t input_format;
232	enum msm_vfe_hvx_streaming_cmd hvx_cmd;
233	uint32_t is_split;
234};
235
236struct msm_vfe_rdi_cfg {
237	uint8_t cid;
238	uint8_t frame_based;
239};
240
241struct msm_vfe_input_cfg {
242	union {
243		struct msm_vfe_pix_cfg pix_cfg;
244		struct msm_vfe_rdi_cfg rdi_cfg;
245	} d;
246	enum msm_vfe_input_src input_src;
247	uint32_t input_pix_clk;
248};
249
250struct msm_vfe_fetch_eng_start {
251	uint32_t session_id;
252	uint32_t stream_id;
253	uint32_t buf_idx;
254	uint8_t  offline_mode;
255	uint32_t fd;
256	uint32_t buf_addr;
257	uint32_t frame_id;
258};
259
260struct msm_vfe_axi_plane_cfg {
261	uint32_t output_width; /*Include padding*/
262	uint32_t output_height;
263	uint32_t output_stride;
264	uint32_t output_scan_lines;
265	uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
266	uint32_t plane_addr_offset;
267	uint8_t csid_src; /*RDI 0-2*/
268	uint8_t rdi_cid;/*CID 1-16*/
269};
270
271enum msm_stream_memory_input_t {
272	MEMORY_INPUT_DISABLED,
273	MEMORY_INPUT_ENABLED
274};
275
276struct msm_vfe_axi_stream_request_cmd {
277	uint32_t session_id;
278	uint32_t stream_id;
279	uint32_t vt_enable;
280	uint32_t output_format;/*Planar/RAW/Misc*/
281	enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
282	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
283
284	uint32_t burst_count;
285	uint32_t hfr_mode;
286	uint8_t frame_base;
287
288	uint32_t init_frame_drop; /*MAX 31 Frames*/
289	enum msm_vfe_frame_skip_pattern frame_skip_pattern;
290	uint8_t buf_divert; /* if TRUE no vb2 buf done. */
291	/*Return values*/
292	uint32_t axi_stream_handle;
293	uint32_t controllable_output;
294	uint32_t burst_len;
295	/* Flag indicating memory input stream */
296	enum msm_stream_memory_input_t memory_input;
297};
298
299struct msm_vfe_axi_stream_release_cmd {
300	uint32_t stream_handle;
301};
302
303enum msm_vfe_axi_stream_cmd {
304	STOP_STREAM,
305	START_STREAM,
306	STOP_IMMEDIATELY,
307};
308
309struct msm_vfe_axi_stream_cfg_cmd {
310	uint8_t num_streams;
311	uint32_t stream_handle[VFE_AXI_SRC_MAX];
312	enum msm_vfe_axi_stream_cmd cmd;
313	uint8_t sync_frame_id_src;
314};
315
316enum msm_vfe_axi_stream_update_type {
317	ENABLE_STREAM_BUF_DIVERT,
318	DISABLE_STREAM_BUF_DIVERT,
319	UPDATE_STREAM_FRAMEDROP_PATTERN,
320	UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
321	UPDATE_STREAM_AXI_CONFIG,
322	UPDATE_STREAM_REQUEST_FRAMES,
323	UPDATE_STREAM_ADD_BUFQ,
324	UPDATE_STREAM_REMOVE_BUFQ,
325	UPDATE_STREAM_SW_FRAME_DROP,
326	UPDATE_STREAM_REQUEST_FRAMES_VER2,
327};
328#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2
329
330enum msm_vfe_iommu_type {
331	IOMMU_ATTACH,
332	IOMMU_DETACH,
333};
334
335enum msm_vfe_buff_queue_id {
336	VFE_BUF_QUEUE_DEFAULT,
337	VFE_BUF_QUEUE_SHARED,
338	VFE_BUF_QUEUE_MAX,
339};
340
341struct msm_vfe_axi_stream_cfg_update_info {
342	uint32_t stream_handle;
343	uint32_t output_format;
344	uint32_t user_stream_id;
345	uint32_t frame_id;
346	enum msm_vfe_frame_skip_pattern skip_pattern;
347	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
348	struct msm_isp_sw_framskip sw_skip_info;
349};
350
351struct msm_vfe_axi_stream_cfg_update_info_req_frm {
352	uint32_t stream_handle;
353	uint32_t user_stream_id;
354	uint32_t frame_id;
355	uint32_t buf_index;
356};
357
358struct msm_vfe_axi_halt_cmd {
359	uint32_t stop_camif;
360	uint32_t overflow_detected;
361	uint32_t blocking_halt;
362};
363
364struct msm_vfe_axi_reset_cmd {
365	uint32_t blocking;
366	uint32_t frame_id;
367};
368
369struct msm_vfe_axi_restart_cmd {
370	uint32_t enable_camif;
371};
372
373struct msm_vfe_axi_stream_update_cmd {
374	uint32_t num_streams;
375	enum msm_vfe_axi_stream_update_type update_type;
376	/*
377	 * For backward compatibility, ensure 1st member of any struct
378	 * in union below is uint32_t stream_handle.
379	 */
380	union {
381		struct msm_vfe_axi_stream_cfg_update_info
382					update_info[MSM_ISP_STATS_MAX];
383		struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2;
384	};
385};
386
387struct msm_vfe_smmu_attach_cmd {
388	uint32_t security_mode;
389	uint32_t iommu_attach_mode;
390};
391
392struct msm_vfe_stats_stream_request_cmd {
393	uint32_t session_id;
394	uint32_t stream_id;
395	enum msm_isp_stats_type stats_type;
396	uint32_t composite_flag;
397	uint32_t framedrop_pattern;
398	uint32_t init_frame_drop; /*MAX 31 Frames*/
399	uint32_t irq_subsample_pattern;
400	uint32_t buffer_offset;
401	uint32_t stream_handle;
402};
403
404struct msm_vfe_stats_stream_release_cmd {
405	uint32_t stream_handle;
406};
407struct msm_vfe_stats_stream_cfg_cmd {
408	uint8_t num_streams;
409	uint32_t stream_handle[MSM_ISP_STATS_MAX];
410	uint8_t enable;
411	uint32_t stats_burst_len;
412};
413
414enum msm_vfe_reg_cfg_type {
415	VFE_WRITE,
416	VFE_WRITE_MB,
417	VFE_READ,
418	VFE_CFG_MASK,
419	VFE_WRITE_DMI_16BIT,
420	VFE_WRITE_DMI_32BIT,
421	VFE_WRITE_DMI_64BIT,
422	VFE_READ_DMI_16BIT,
423	VFE_READ_DMI_32BIT,
424	VFE_READ_DMI_64BIT,
425	GET_MAX_CLK_RATE,
426	GET_CLK_RATES,
427	GET_ISP_ID,
428	VFE_HW_UPDATE_LOCK,
429	VFE_HW_UPDATE_UNLOCK,
430	SET_WM_UB_SIZE,
431	SET_UB_POLICY,
432};
433
434struct msm_vfe_cfg_cmd2 {
435	uint16_t num_cfg;
436	uint16_t cmd_len;
437	void __user *cfg_data;
438	void __user *cfg_cmd;
439};
440
441struct msm_vfe_cfg_cmd_list {
442	struct msm_vfe_cfg_cmd2      cfg_cmd;
443	struct msm_vfe_cfg_cmd_list *next;
444	uint32_t                     next_size;
445};
446
447struct msm_vfe_reg_rw_info {
448	uint32_t reg_offset;
449	uint32_t cmd_data_offset;
450	uint32_t len;
451};
452
453struct msm_vfe_reg_mask_info {
454	uint32_t reg_offset;
455	uint32_t mask;
456	uint32_t val;
457};
458
459struct msm_vfe_reg_dmi_info {
460	uint32_t hi_tbl_offset; /*Optional*/
461	uint32_t lo_tbl_offset; /*Required*/
462	uint32_t len;
463};
464
465struct msm_vfe_reg_cfg_cmd {
466	union {
467		struct msm_vfe_reg_rw_info rw_info;
468		struct msm_vfe_reg_mask_info mask_info;
469		struct msm_vfe_reg_dmi_info dmi_info;
470	} u;
471
472	enum msm_vfe_reg_cfg_type cmd_type;
473};
474
475enum vfe_sd_type {
476	VFE_SD_0 = 0,
477	VFE_SD_1,
478	VFE_SD_COMMON,
479	VFE_SD_MAX,
480};
481
482/* When you change the value below, check for the sof event_data size.
483 * V4l2 limits payload to 64 bytes */
484#define MS_NUM_SLAVE_MAX 1
485
486/* Usecases when 2 HW need to be related or synced */
487enum msm_vfe_dual_hw_type {
488	DUAL_NONE = 0,
489	DUAL_HW_VFE_SPLIT = 1,
490	DUAL_HW_MASTER_SLAVE = 2,
491};
492
493/* Type for 2 INTF when used in Master-Slave mode */
494enum msm_vfe_dual_hw_ms_type {
495	MS_TYPE_NONE,
496	MS_TYPE_MASTER,
497	MS_TYPE_SLAVE,
498};
499
500struct msm_isp_set_dual_hw_ms_cmd {
501	uint8_t num_src;
502	/* Each session can be only one type but multiple intf if YUV cam */
503	enum msm_vfe_dual_hw_ms_type dual_hw_ms_type;
504	/* Primary intf is mostly associated with preview.
505	 * This primary intf SOF frame_id and timestamp is tracked
506	 * and used to calculate delta */
507	enum msm_vfe_input_src primary_intf;
508	/* input_src array indicates other input INTF that may be Master/Slave.
509	 * For these additional intf, frame_id and timestamp are not saved.
510	 * However, if these are slaves then they will still get their
511	 * frame_id from Master */
512	enum msm_vfe_input_src input_src[VFE_SRC_MAX];
513	uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */
514};
515
516enum msm_isp_buf_type {
517	ISP_PRIVATE_BUF,
518	ISP_SHARE_BUF,
519	MAX_ISP_BUF_TYPE,
520};
521
522struct msm_isp_unmap_buf_req {
523	uint32_t fd;
524};
525
526struct msm_isp_buf_request {
527	uint32_t session_id;
528	uint32_t stream_id;
529	uint8_t num_buf;
530	uint32_t handle;
531	enum msm_isp_buf_type buf_type;
532};
533
534struct msm_isp_qbuf_plane {
535	uint32_t addr;
536	uint32_t offset;
537	uint32_t length;
538};
539
540struct msm_isp_qbuf_buffer {
541	struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
542	uint32_t num_planes;
543};
544
545struct msm_isp_qbuf_info {
546	uint32_t handle;
547	int32_t buf_idx;
548	/*Only used for prepare buffer*/
549	struct msm_isp_qbuf_buffer buffer;
550	/*Only used for diverted buffer*/
551	uint32_t dirty_buf;
552};
553
554struct msm_isp_clk_rates {
555	uint32_t svs_rate;
556	uint32_t nominal_rate;
557	uint32_t high_rate;
558};
559
560struct msm_vfe_axi_src_state {
561	enum msm_vfe_input_src input_src;
562	uint32_t src_active;
563	uint32_t src_frame_id;
564};
565
566enum msm_isp_event_mask_index {
567	ISP_EVENT_MASK_INDEX_STATS_NOTIFY		= 0,
568	ISP_EVENT_MASK_INDEX_ERROR			= 1,
569	ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT		= 2,
570	ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE		= 3,
571	ISP_EVENT_MASK_INDEX_REG_UPDATE			= 4,
572	ISP_EVENT_MASK_INDEX_SOF			= 5,
573	ISP_EVENT_MASK_INDEX_BUF_DIVERT			= 6,
574	ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY		= 7,
575	ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE		= 8,
576	ISP_EVENT_MASK_INDEX_BUF_DONE			= 9,
577	ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING		= 10,
578	ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH		= 11,
579	ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR		= 12,
580};
581
582
583#define ISP_EVENT_SUBS_MASK_NONE			0
584
585#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \
586			(1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
587
588#define ISP_EVENT_SUBS_MASK_ERROR \
589			(1 << ISP_EVENT_MASK_INDEX_ERROR)
590
591#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \
592			(1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
593
594#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \
595			(1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
596
597#define ISP_EVENT_SUBS_MASK_REG_UPDATE \
598			(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
599
600#define ISP_EVENT_SUBS_MASK_SOF \
601			(1 << ISP_EVENT_MASK_INDEX_SOF)
602
603#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \
604			(1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
605
606#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \
607			(1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
608
609#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \
610			(1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
611
612#define ISP_EVENT_SUBS_MASK_BUF_DONE \
613			(1 << ISP_EVENT_MASK_INDEX_BUF_DONE)
614
615#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \
616			(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING)
617
618#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \
619			(1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH)
620
621#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \
622			(1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR)
623
624enum msm_isp_event_idx {
625	ISP_REG_UPDATE        = 0,
626	ISP_EPOCH_0           = 1,
627	ISP_EPOCH_1           = 2,
628	ISP_START_ACK         = 3,
629	ISP_STOP_ACK          = 4,
630	ISP_IRQ_VIOLATION     = 5,
631	ISP_STATS_OVERFLOW    = 6,
632	ISP_BUF_DONE          = 7,
633	ISP_FE_RD_DONE        = 8,
634	ISP_IOMMU_P_FAULT     = 9,
635	ISP_ERROR             = 10,
636	ISP_HW_FATAL_ERROR      = 11,
637	ISP_PING_PONG_MISMATCH = 12,
638	ISP_REG_UPDATE_MISSING = 13,
639	ISP_BUF_FATAL_ERROR = 14,
640	ISP_EVENT_MAX         = 15
641};
642
643#define ISP_EVENT_OFFSET          8
644#define ISP_EVENT_BASE            (V4L2_EVENT_PRIVATE_START)
645#define ISP_BUF_EVENT_BASE        (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
646#define ISP_STATS_EVENT_BASE      (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
647#define ISP_CAMIF_EVENT_BASE      (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
648#define ISP_STREAM_EVENT_BASE     (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
649#define ISP_EVENT_REG_UPDATE      (ISP_EVENT_BASE + ISP_REG_UPDATE)
650#define ISP_EVENT_EPOCH_0         (ISP_EVENT_BASE + ISP_EPOCH_0)
651#define ISP_EVENT_EPOCH_1         (ISP_EVENT_BASE + ISP_EPOCH_1)
652#define ISP_EVENT_START_ACK       (ISP_EVENT_BASE + ISP_START_ACK)
653#define ISP_EVENT_STOP_ACK        (ISP_EVENT_BASE + ISP_STOP_ACK)
654#define ISP_EVENT_IRQ_VIOLATION   (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
655#define ISP_EVENT_STATS_OVERFLOW  (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
656#define ISP_EVENT_ERROR           (ISP_EVENT_BASE + ISP_ERROR)
657#define ISP_EVENT_SOF             (ISP_CAMIF_EVENT_BASE)
658#define ISP_EVENT_EOF             (ISP_CAMIF_EVENT_BASE + 1)
659#define ISP_EVENT_BUF_DONE        (ISP_EVENT_BASE + ISP_BUF_DONE)
660#define ISP_EVENT_BUF_DIVERT      (ISP_BUF_EVENT_BASE)
661#define ISP_EVENT_STATS_NOTIFY    (ISP_STATS_EVENT_BASE)
662#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
663#define ISP_EVENT_FE_READ_DONE    (ISP_EVENT_BASE + ISP_FE_RD_DONE)
664#define ISP_EVENT_IOMMU_P_FAULT   (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
665#define ISP_EVENT_HW_FATAL_ERROR  (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR)
666#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
667#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
668#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR)
669#define ISP_EVENT_STREAM_UPDATE_DONE   (ISP_STREAM_EVENT_BASE)
670
671/* The msm_v4l2_event_data structure should match the
672 * v4l2_event.u.data field.
673 * should not exceed 64 bytes */
674
675struct msm_isp_buf_event {
676	uint32_t session_id;
677	uint32_t stream_id;
678	uint32_t handle;
679	uint32_t output_format;
680	int8_t buf_idx;
681};
682struct msm_isp_fetch_eng_event {
683	uint32_t session_id;
684	uint32_t stream_id;
685	uint32_t handle;
686	uint32_t fd;
687	int8_t buf_idx;
688	int8_t offline_mode;
689};
690struct msm_isp_stats_event {
691	uint32_t stats_mask;                        /* 4 bytes */
692	uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX];  /* 11 bytes */
693};
694
695struct msm_isp_stream_ack {
696	uint32_t session_id;
697	uint32_t stream_id;
698	uint32_t handle;
699};
700
701enum msm_vfe_error_type {
702	ISP_ERROR_NONE,
703	ISP_ERROR_CAMIF,
704	ISP_ERROR_BUS_OVERFLOW,
705	ISP_ERROR_RETURN_EMPTY_BUFFER,
706	ISP_ERROR_FRAME_ID_MISMATCH,
707	ISP_ERROR_MAX,
708};
709
710struct msm_isp_error_info {
711	enum msm_vfe_error_type err_type;
712	uint32_t session_id;
713	uint32_t stream_id;
714	uint32_t stream_id_mask;
715};
716
717/* This structure reports delta between master and slave */
718struct msm_isp_ms_delta_info {
719	uint8_t num_delta_info;
720	uint32_t delta[MS_NUM_SLAVE_MAX];
721};
722
723/* This is sent in EPOCH irq */
724struct msm_isp_output_info {
725	uint8_t regs_not_updated;
726	/* mask with bufq_handle for regs not updated or return empty */
727	uint16_t output_err_mask;
728	/* mask with stream_idx for get_buf failed */
729	uint8_t stream_framedrop_mask;
730	/* mask with stats stream_idx for get_buf failed */
731	uint16_t stats_framedrop_mask;
732	/* delta between master and slave */
733};
734
735/* This structure is piggybacked with SOF event */
736struct msm_isp_sof_info {
737	uint8_t regs_not_updated;
738	/* mask with AXI_SRC for regs not updated */
739	uint16_t reg_update_fail_mask;
740	/* mask with bufq_handle for get_buf failed */
741	uint32_t stream_get_buf_fail_mask;
742	/* mask with stats stream_idx for get_buf failed */
743	uint16_t stats_get_buf_fail_mask;
744	/* delta between master and slave */
745	struct msm_isp_ms_delta_info ms_delta_info;
746};
747
748struct msm_isp_event_data {
749	/*Wall clock except for buffer divert events
750	 *which use monotonic clock
751	 */
752	struct timeval timestamp;
753	/* Monotonic timestamp since bootup */
754	struct timeval mono_timestamp;
755	uint32_t frame_id;
756	union {
757		/* Sent for Stats_Done event */
758		struct msm_isp_stats_event stats;
759		/* Sent for Buf_Divert event */
760		struct msm_isp_buf_event buf_done;
761		/* Sent for offline fetch done event */
762		struct msm_isp_fetch_eng_event fetch_done;
763		/* Sent for Error_Event */
764		struct msm_isp_error_info error_info;
765		/*
766		 * This struct needs to be removed once
767		 * userspace switches to sof_info
768		 */
769		struct msm_isp_output_info output_info;
770		/* Sent for SOF event */
771		struct msm_isp_sof_info sof_info;
772	} u; /* union can have max 52 bytes */
773};
774
775#define V4L2_PIX_FMT_QBGGR8  v4l2_fourcc('Q', 'B', 'G', '8')
776#define V4L2_PIX_FMT_QGBRG8  v4l2_fourcc('Q', 'G', 'B', '8')
777#define V4L2_PIX_FMT_QGRBG8  v4l2_fourcc('Q', 'G', 'R', '8')
778#define V4L2_PIX_FMT_QRGGB8  v4l2_fourcc('Q', 'R', 'G', '8')
779#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
780#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
781#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
782#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
783#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
784#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
785#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
786#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
787#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
788#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
789#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
790#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
791#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
792#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
793#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
794#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
795#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
796#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
797#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
798#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/
799#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/
800#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/
801#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/
802
803enum msm_isp_ioctl_cmd_code {
804	MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE,
805	MSM_ISP_REQUEST_BUF,
806	MSM_ISP_ENQUEUE_BUF,
807	MSM_ISP_RELEASE_BUF,
808	MSM_ISP_REQUEST_STREAM,
809	MSM_ISP_CFG_STREAM,
810	MSM_ISP_RELEASE_STREAM,
811	MSM_ISP_INPUT_CFG,
812	MSM_ISP_SET_SRC_STATE,
813	MSM_ISP_REQUEST_STATS_STREAM,
814	MSM_ISP_CFG_STATS_STREAM,
815	MSM_ISP_RELEASE_STATS_STREAM,
816	MSM_ISP_REG_UPDATE_CMD,
817	MSM_ISP_UPDATE_STREAM,
818	MSM_VFE_REG_LIST_CFG,
819	MSM_ISP_SMMU_ATTACH,
820	MSM_ISP_UPDATE_STATS_STREAM,
821	MSM_ISP_AXI_HALT,
822	MSM_ISP_AXI_RESET,
823	MSM_ISP_AXI_RESTART,
824	MSM_ISP_FETCH_ENG_START,
825	MSM_ISP_DEQUEUE_BUF,
826	MSM_ISP_SET_DUAL_HW_MASTER_SLAVE,
827	MSM_ISP_MAP_BUF_START_FE,
828	MSM_ISP_UNMAP_BUF,
829};
830
831#define VIDIOC_MSM_VFE_REG_CFG \
832	_IOWR('V', MSM_VFE_REG_CFG, \
833		struct msm_vfe_cfg_cmd2)
834
835#define VIDIOC_MSM_ISP_REQUEST_BUF \
836	_IOWR('V', MSM_ISP_REQUEST_BUF, \
837		struct msm_isp_buf_request)
838
839#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
840	_IOWR('V', MSM_ISP_ENQUEUE_BUF, \
841		struct msm_isp_qbuf_info)
842
843#define VIDIOC_MSM_ISP_RELEASE_BUF \
844	_IOWR('V', MSM_ISP_RELEASE_BUF, \
845		struct msm_isp_buf_request)
846
847#define VIDIOC_MSM_ISP_REQUEST_STREAM \
848	_IOWR('V', MSM_ISP_REQUEST_STREAM, \
849		struct msm_vfe_axi_stream_request_cmd)
850
851#define VIDIOC_MSM_ISP_CFG_STREAM \
852	_IOWR('V', MSM_ISP_CFG_STREAM, \
853		struct msm_vfe_axi_stream_cfg_cmd)
854
855#define VIDIOC_MSM_ISP_RELEASE_STREAM \
856	_IOWR('V', MSM_ISP_RELEASE_STREAM, \
857		struct msm_vfe_axi_stream_release_cmd)
858
859#define VIDIOC_MSM_ISP_INPUT_CFG \
860	_IOWR('V', MSM_ISP_INPUT_CFG, \
861		struct msm_vfe_input_cfg)
862
863#define VIDIOC_MSM_ISP_SET_SRC_STATE \
864	_IOWR('V', MSM_ISP_SET_SRC_STATE, \
865		struct msm_vfe_axi_src_state)
866
867#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
868	_IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, \
869		struct msm_vfe_stats_stream_request_cmd)
870
871#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
872	_IOWR('V', MSM_ISP_CFG_STATS_STREAM, \
873		struct msm_vfe_stats_stream_cfg_cmd)
874
875#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
876	_IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, \
877		struct msm_vfe_stats_stream_release_cmd)
878
879#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \
880	_IOWR('V', MSM_ISP_REG_UPDATE_CMD, \
881		enum msm_vfe_input_src)
882
883#define VIDIOC_MSM_ISP_UPDATE_STREAM \
884	_IOWR('V', MSM_ISP_UPDATE_STREAM, \
885		struct msm_vfe_axi_stream_update_cmd)
886
887#define VIDIOC_MSM_VFE_REG_LIST_CFG \
888	_IOWR('V', MSM_VFE_REG_LIST_CFG, \
889		struct msm_vfe_cfg_cmd_list)
890
891#define VIDIOC_MSM_ISP_SMMU_ATTACH \
892	_IOWR('V', MSM_ISP_SMMU_ATTACH, \
893		struct msm_vfe_smmu_attach_cmd)
894
895#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \
896	_IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, \
897		struct msm_vfe_axi_stream_update_cmd)
898
899#define VIDIOC_MSM_ISP_AXI_HALT \
900	_IOWR('V', MSM_ISP_AXI_HALT, \
901		struct msm_vfe_axi_halt_cmd)
902
903#define VIDIOC_MSM_ISP_AXI_RESET \
904	_IOWR('V', MSM_ISP_AXI_RESET, \
905		struct msm_vfe_axi_reset_cmd)
906
907#define VIDIOC_MSM_ISP_AXI_RESTART \
908	_IOWR('V', MSM_ISP_AXI_RESTART, \
909		struct msm_vfe_axi_restart_cmd)
910
911#define VIDIOC_MSM_ISP_FETCH_ENG_START \
912	_IOWR('V', MSM_ISP_FETCH_ENG_START, \
913		struct msm_vfe_fetch_eng_start)
914
915#define VIDIOC_MSM_ISP_DEQUEUE_BUF \
916	_IOWR('V', MSM_ISP_DEQUEUE_BUF, \
917		struct msm_isp_qbuf_info)
918
919#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \
920	_IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, \
921		struct msm_isp_set_dual_hw_ms_cmd)
922
923#define VIDIOC_MSM_ISP_MAP_BUF_START_FE \
924	_IOWR('V', MSM_ISP_MAP_BUF_START_FE, \
925		struct msm_vfe_fetch_eng_start)
926
927#define VIDIOC_MSM_ISP_UNMAP_BUF \
928	_IOWR('V', MSM_ISP_UNMAP_BUF, \
929		struct msm_isp_unmap_buf_req)
930
931#endif /* __MSMB_ISP__ */
932