1#ifndef _UAPI_MSM_MDP_H_ 2#define _UAPI_MSM_MDP_H_ 3 4#include <linux/types.h> 5#include <linux/fb.h> 6 7#define MSMFB_IOCTL_MAGIC 'm' 8#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15/* new ioctls's for set/get ccs matrix */ 16#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70#define MSMFB_REG_READ _IOWR(MSMFB_IOCTL_MAGIC, 64, struct msmfb_reg_access) 71#define MSMFB_REG_WRITE _IOW(MSMFB_IOCTL_MAGIC, 65, struct msmfb_reg_access) 72#define MSMFB_SECURE _IOWR(MSMFB_IOCTL_MAGIC, 170, struct msmfb_secure_config) 73 74#define FB_TYPE_3D_PANEL 0x10101010 75#define MDP_IMGTYPE2_START 0x10000 76#define MSMFB_DRIVER_VERSION 0xF9E8D701 77 78/* HW Revisions for different MDSS targets */ 79#define MDSS_GET_MAJOR(rev) ((rev) >> 28) 80#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 81#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 82#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 83 84#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 85 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 86 87#define MDSS_MDP_REV(major, minor, step) \ 88 ((((major) & 0x000F) << 28) | \ 89 (((minor) & 0x0FFF) << 16) | \ 90 ((step) & 0xFFFF)) 91 92#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 93#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 94#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 95#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 96#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 97#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 98#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 99#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 100#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 101 102enum { 103 NOTIFY_UPDATE_START, 104 NOTIFY_UPDATE_STOP, 105 NOTIFY_UPDATE_POWER_OFF, 106}; 107 108enum { 109 NOTIFY_TYPE_NO_UPDATE, 110 NOTIFY_TYPE_SUSPEND, 111 NOTIFY_TYPE_UPDATE, 112 NOTIFY_TYPE_BL_UPDATE, 113}; 114 115enum { 116 MDP_RGB_565, /* RGB 565 planer */ 117 MDP_XRGB_8888, /* RGB 888 padded */ 118 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 119 MDP_Y_CBCR_H2V2_ADRENO, 120 MDP_ARGB_8888, /* ARGB 888 */ 121 MDP_RGB_888, /* RGB 888 planer */ 122 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 123 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 124 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 125 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 126 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 127 MDP_Y_CRCB_H1V2, 128 MDP_Y_CBCR_H1V2, 129 MDP_RGBA_8888, /* ARGB 888 */ 130 MDP_BGRA_8888, /* ABGR 888 */ 131 MDP_RGBX_8888, /* RGBX 888 */ 132 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 133 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 134 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 135 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 136 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 137 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 138 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 139 MDP_YCRCB_H1V1, /* YCrCb interleave */ 140 MDP_YCBCR_H1V1, /* YCbCr interleave */ 141 MDP_BGR_565, /* BGR 565 planer */ 142 MDP_BGR_888, /* BGR 888 */ 143 MDP_Y_CBCR_H2V2_VENUS, 144 MDP_BGRX_8888, /* BGRX 8888 */ 145 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 146 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 147 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 148 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 149 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 150 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 151 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 152 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 153 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 154 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 155 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 156 MDP_IMGTYPE_LIMIT, 157 MDP_RGB_BORDERFILL, /* border fill pipe */ 158 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 159 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 160}; 161 162enum { 163 PMEM_IMG, 164 FB_IMG, 165}; 166 167enum { 168 HSIC_HUE = 0, 169 HSIC_SAT, 170 HSIC_INT, 171 HSIC_CON, 172 NUM_HSIC_PARAM, 173}; 174 175#define MDSS_MDP_ROT_ONLY 0x80 176#define MDSS_MDP_RIGHT_MIXER 0x100 177#define MDSS_MDP_DUAL_PIPE 0x200 178 179/* mdp_blit_req flag values */ 180#define MDP_ROT_NOP 0 181#define MDP_FLIP_LR 0x1 182#define MDP_FLIP_UD 0x2 183#define MDP_ROT_90 0x4 184#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 185#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 186#define MDP_DITHER 0x8 187#define MDP_BLUR 0x10 188#define MDP_BLEND_FG_PREMULT 0x20000 189#define MDP_IS_FG 0x40000 190#define MDP_SOLID_FILL 0x00000020 191#define MDP_VPU_PIPE 0x00000040 192#define MDP_DEINTERLACE 0x80000000 193#define MDP_SHARPENING 0x40000000 194#define MDP_NO_DMA_BARRIER_START 0x20000000 195#define MDP_NO_DMA_BARRIER_END 0x10000000 196#define MDP_NO_BLIT 0x08000000 197#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 198#define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 199 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 200#define MDP_BLIT_SRC_GEM 0x04000000 201#define MDP_BLIT_DST_GEM 0x02000000 202#define MDP_BLIT_NON_CACHED 0x01000000 203#define MDP_OV_PIPE_SHARE 0x00800000 204#define MDP_DEINTERLACE_ODD 0x00400000 205#define MDP_OV_PLAY_NOWAIT 0x00200000 206#define MDP_SOURCE_ROTATED_90 0x00100000 207#define MDP_OVERLAY_PP_CFG_EN 0x00080000 208#define MDP_BACKEND_COMPOSITION 0x00040000 209#define MDP_BORDERFILL_SUPPORTED 0x00010000 210#define MDP_SECURE_OVERLAY_SESSION 0x00008000 211#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 212#define MDP_OV_PIPE_FORCE_DMA 0x00004000 213#define MDP_MEMORY_ID_TYPE_FB 0x00001000 214#define MDP_BWC_EN 0x00000400 215#define MDP_DECIMATION_EN 0x00000800 216#define MDP_TRANSP_NOP 0xffffffff 217#define MDP_ALPHA_NOP 0xff 218 219#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 220#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 221#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 222#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 223#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 224/* Sentinel: Don't use! */ 225#define MDP_FB_PAGE_PROTECTION_INVALID (5) 226/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 227#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 228 229struct mdp_rect { 230 uint32_t x; 231 uint32_t y; 232 uint32_t w; 233 uint32_t h; 234}; 235 236struct mdp_img { 237 uint32_t width; 238 uint32_t height; 239 uint32_t format; 240 uint32_t offset; 241 int memory_id; /* the file descriptor */ 242 uint32_t priv; 243}; 244 245/* 246 * {3x3} + {3} ccs matrix 247 */ 248 249#define MDP_CCS_RGB2YUV 0 250#define MDP_CCS_YUV2RGB 1 251 252#define MDP_CCS_SIZE 9 253#define MDP_BV_SIZE 3 254 255struct mdp_ccs { 256 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 257 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 258 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 259}; 260 261struct mdp_csc { 262 int id; 263 uint32_t csc_mv[9]; 264 uint32_t csc_pre_bv[3]; 265 uint32_t csc_post_bv[3]; 266 uint32_t csc_pre_lv[6]; 267 uint32_t csc_post_lv[6]; 268}; 269 270/* The version of the mdp_blit_req structure so that 271 * user applications can selectively decide which functionality 272 * to include 273 */ 274 275#define MDP_BLIT_REQ_VERSION 2 276 277struct color { 278 uint32_t r; 279 uint32_t g; 280 uint32_t b; 281 uint32_t alpha; 282}; 283 284struct mdp_blit_req { 285 struct mdp_img src; 286 struct mdp_img dst; 287 struct mdp_rect src_rect; 288 struct mdp_rect dst_rect; 289 struct color const_color; 290 uint32_t alpha; 291 uint32_t transp_mask; 292 uint32_t flags; 293 int sharpening_strength; /* -127 <--> 127, default 64 */ 294}; 295 296struct mdp_blit_req_list { 297 uint32_t count; 298 struct mdp_blit_req req[]; 299}; 300 301#define MSMFB_DATA_VERSION 2 302 303struct msmfb_data { 304 uint32_t offset; 305 int memory_id; 306 int id; 307 uint32_t flags; 308 uint32_t priv; 309 uint32_t iova; 310}; 311 312#define MSMFB_NEW_REQUEST -1 313 314struct msmfb_overlay_data { 315 uint32_t id; 316 struct msmfb_data data; 317 uint32_t version_key; 318 struct msmfb_data plane1_data; 319 struct msmfb_data plane2_data; 320 struct msmfb_data dst_data; 321}; 322 323struct msmfb_img { 324 uint32_t width; 325 uint32_t height; 326 uint32_t format; 327}; 328 329#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 330struct msmfb_writeback_data { 331 struct msmfb_data buf_info; 332 struct msmfb_img img; 333}; 334 335#define MDP_PP_OPS_ENABLE 0x1 336#define MDP_PP_OPS_READ 0x2 337#define MDP_PP_OPS_WRITE 0x4 338#define MDP_PP_OPS_DISABLE 0x8 339#define MDP_PP_IGC_FLAG_ROM0 0x10 340#define MDP_PP_IGC_FLAG_ROM1 0x20 341 342#define MDP_PP_PA_HUE_ENABLE 0x10 343#define MDP_PP_PA_SAT_ENABLE 0x20 344#define MDP_PP_PA_VAL_ENABLE 0x40 345#define MDP_PP_PA_CONT_ENABLE 0x80 346#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 347#define MDP_PP_PA_SKIN_ENABLE 0x200 348#define MDP_PP_PA_SKY_ENABLE 0x400 349#define MDP_PP_PA_FOL_ENABLE 0x800 350#define MDP_PP_PA_HUE_MASK 0x1000 351#define MDP_PP_PA_SAT_MASK 0x2000 352#define MDP_PP_PA_VAL_MASK 0x4000 353#define MDP_PP_PA_CONT_MASK 0x8000 354#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 355#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 356#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 357#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 358#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 359#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 360#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 361#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 362 363#define MDSS_PP_DSPP_CFG 0x000 364#define MDSS_PP_SSPP_CFG 0x100 365#define MDSS_PP_LM_CFG 0x200 366#define MDSS_PP_WB_CFG 0x300 367 368#define MDSS_PP_ARG_MASK 0x3C00 369#define MDSS_PP_ARG_NUM 4 370#define MDSS_PP_ARG_SHIFT 10 371#define MDSS_PP_LOCATION_MASK 0x0300 372#define MDSS_PP_LOGICAL_MASK 0x00FF 373 374#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 375#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 376#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 377#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 378 379 380struct mdp_qseed_cfg { 381 uint32_t table_num; 382 uint32_t ops; 383 uint32_t len; 384 uint32_t *data; 385}; 386 387struct mdp_sharp_cfg { 388 uint32_t flags; 389 uint32_t strength; 390 uint32_t edge_thr; 391 uint32_t smooth_thr; 392 uint32_t noise_thr; 393}; 394 395struct mdp_qseed_cfg_data { 396 uint32_t block; 397 struct mdp_qseed_cfg qseed_data; 398}; 399 400#define MDP_OVERLAY_PP_CSC_CFG 0x1 401#define MDP_OVERLAY_PP_QSEED_CFG 0x2 402#define MDP_OVERLAY_PP_PA_CFG 0x4 403#define MDP_OVERLAY_PP_IGC_CFG 0x8 404#define MDP_OVERLAY_PP_SHARP_CFG 0x10 405#define MDP_OVERLAY_PP_HIST_CFG 0x20 406#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 407#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 408 409#define MDP_CSC_FLAG_ENABLE 0x1 410#define MDP_CSC_FLAG_YUV_IN 0x2 411#define MDP_CSC_FLAG_YUV_OUT 0x4 412 413struct mdp_csc_cfg { 414 /* flags for enable CSC, toggling RGB,YUV input/output */ 415 uint32_t flags; 416 uint32_t csc_mv[9]; 417 uint32_t csc_pre_bv[3]; 418 uint32_t csc_post_bv[3]; 419 uint32_t csc_pre_lv[6]; 420 uint32_t csc_post_lv[6]; 421}; 422 423struct mdp_csc_cfg_data { 424 uint32_t block; 425 struct mdp_csc_cfg csc_data; 426}; 427 428struct mdp_pa_cfg { 429 uint32_t flags; 430 uint32_t hue_adj; 431 uint32_t sat_adj; 432 uint32_t val_adj; 433 uint32_t cont_adj; 434}; 435 436struct mdp_pa_mem_col_cfg { 437 uint32_t color_adjust_p0; 438 uint32_t color_adjust_p1; 439 uint32_t hue_region; 440 uint32_t sat_region; 441 uint32_t val_region; 442}; 443 444#define MDP_SIX_ZONE_LUT_SIZE 384 445 446struct mdp_pa_v2_data { 447 /* Mask bits for PA features */ 448 uint32_t flags; 449 uint32_t global_hue_adj; 450 uint32_t global_sat_adj; 451 uint32_t global_val_adj; 452 uint32_t global_cont_adj; 453 struct mdp_pa_mem_col_cfg skin_cfg; 454 struct mdp_pa_mem_col_cfg sky_cfg; 455 struct mdp_pa_mem_col_cfg fol_cfg; 456 uint32_t six_zone_len; 457 uint32_t six_zone_thresh; 458 uint32_t *six_zone_curve_p0; 459 uint32_t *six_zone_curve_p1; 460}; 461 462struct mdp_igc_lut_data { 463 uint32_t block; 464 uint32_t len, ops; 465 uint32_t *c0_c1_data; 466 uint32_t *c2_data; 467}; 468 469struct mdp_histogram_cfg { 470 uint32_t ops; 471 uint32_t block; 472 uint8_t frame_cnt; 473 uint8_t bit_mask; 474 uint16_t num_bins; 475}; 476 477struct mdp_hist_lut_data { 478 uint32_t block; 479 uint32_t ops; 480 uint32_t len; 481 uint32_t *data; 482}; 483 484struct mdp_overlay_pp_params { 485 uint32_t config_ops; 486 struct mdp_csc_cfg csc_cfg; 487 struct mdp_qseed_cfg qseed_cfg[2]; 488 struct mdp_pa_cfg pa_cfg; 489 struct mdp_pa_v2_data pa_v2_cfg; 490 struct mdp_igc_lut_data igc_cfg; 491 struct mdp_sharp_cfg sharp_cfg; 492 struct mdp_histogram_cfg hist_cfg; 493 struct mdp_hist_lut_data hist_lut_cfg; 494}; 495 496/** 497 * enum mdss_mdp_blend_op - Different blend operations set by userspace 498 * 499 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 500 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 501 * would appear opaque in case fg plane alpha is 502 * 0xff. 503 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 504 * alpha pre-multiplication done. If fg plane alpha 505 * is less than 0xff, apply modulation as well. This 506 * operation is intended on layers having alpha 507 * channel. 508 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 509 * pre-multiplied. Apply pre-multiplication. If fg 510 * plane alpha is less than 0xff, apply modulation as 511 * well. 512 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 513 * mdp. 514 */ 515enum mdss_mdp_blend_op { 516 BLEND_OP_NOT_DEFINED = 0, 517 BLEND_OP_OPAQUE, 518 BLEND_OP_PREMULTIPLIED, 519 BLEND_OP_COVERAGE, 520 BLEND_OP_MAX, 521}; 522 523#define MAX_PLANES 4 524struct mdp_scale_data { 525 uint8_t enable_pxl_ext; 526 527 int init_phase_x[MAX_PLANES]; 528 int phase_step_x[MAX_PLANES]; 529 int init_phase_y[MAX_PLANES]; 530 int phase_step_y[MAX_PLANES]; 531 532 int num_ext_pxls_left[MAX_PLANES]; 533 int num_ext_pxls_right[MAX_PLANES]; 534 int num_ext_pxls_top[MAX_PLANES]; 535 int num_ext_pxls_btm[MAX_PLANES]; 536 537 int left_ftch[MAX_PLANES]; 538 int left_rpt[MAX_PLANES]; 539 int right_ftch[MAX_PLANES]; 540 int right_rpt[MAX_PLANES]; 541 542 int top_rpt[MAX_PLANES]; 543 int btm_rpt[MAX_PLANES]; 544 int top_ftch[MAX_PLANES]; 545 int btm_ftch[MAX_PLANES]; 546 547 uint32_t roi_w[MAX_PLANES]; 548}; 549 550/** 551 * struct mdp_overlay - overlay surface structure 552 * @src: Source image information (width, height, format). 553 * @src_rect: Source crop rectangle, portion of image that will be fetched. 554 * This should always be within boundaries of source image. 555 * @dst_rect: Destination rectangle, the position and size of image on screen. 556 * This should always be within panel boundaries. 557 * @z_order: Blending stage to occupy in display, if multiple layers are 558 * present, highest z_order usually means the top most visible 559 * layer. The range acceptable is from 0-3 to support blending 560 * up to 4 layers. 561 * @is_fg: This flag is used to disable blending of any layers with z_order 562 * less than this overlay. It means that any layers with z_order 563 * less than this layer will not be blended and will be replaced 564 * by the background border color. 565 * @alpha: Used to set plane opacity. The range can be from 0-255, where 566 * 0 means completely transparent and 255 means fully opaque. 567 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 568 * image matching this color will be transparent when blending. 569 * The color should be in same format as the source image format. 570 * @flags: This is used to customize operation of overlay. See MDP flags 571 * for more information. 572 * @user_data: DEPRECATED* Used to store user application specific information. 573 * @bg_color: Solid color used to fill the overlay surface when no source 574 * buffer is provided. 575 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 576 * dropped for each pixel that is fetched from a line. The value 577 * given should be power of two of decimation amount. 578 * 0: no decimation 579 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 580 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 581 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 582 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 583 * @vert_deci: Vertical decimation value, this indicates the amount of lines 584 * dropped for each line that is fetched from overlay. The value 585 * given should be power of two of decimation amount. 586 * 0: no decimation 587 * 1: decimation by 2 (drop 1 line for each line fetched) 588 * 2: decimation by 4 (drop 3 lines for each line fetched) 589 * 3: decimation by 8 (drop 7 lines for each line fetched) 590 * 4: decimation by 16 (drop 15 lines for each line fetched) 591 * @overlay_pp_cfg: Overlay post processing configuration, for more information 592 * see struct mdp_overlay_pp_params. 593 * @priority: Priority is returned by the driver when overlay is set for the 594 * first time. It indicates the priority of the underlying pipe 595 * serving the overlay. This priority can be used by user-space 596 * in source split when pipes are re-used and shuffled around to 597 * reduce fallbacks. 598 */ 599struct mdp_overlay { 600 struct msmfb_img src; 601 struct mdp_rect src_rect; 602 struct mdp_rect dst_rect; 603 uint32_t z_order; /* stage number */ 604 uint32_t is_fg; /* control alpha & transp */ 605 uint32_t alpha; 606 uint32_t blend_op; 607 uint32_t transp_mask; 608 uint32_t flags; 609 uint32_t id; 610 uint8_t priority; 611 uint32_t user_data[6]; 612 uint32_t bg_color; 613 uint8_t horz_deci; 614 uint8_t vert_deci; 615 struct mdp_overlay_pp_params overlay_pp_cfg; 616 struct mdp_scale_data scale; 617}; 618 619struct msmfb_overlay_3d { 620 uint32_t is_3d; 621 uint32_t width; 622 uint32_t height; 623}; 624 625 626struct msmfb_overlay_blt { 627 uint32_t enable; 628 uint32_t offset; 629 uint32_t width; 630 uint32_t height; 631 uint32_t bpp; 632}; 633 634struct mdp_histogram { 635 uint32_t frame_cnt; 636 uint32_t bin_cnt; 637 uint32_t *r; 638 uint32_t *g; 639 uint32_t *b; 640}; 641 642#define MISR_CRC_BATCH_SIZE 32 643enum { 644 DISPLAY_MISR_EDP, 645 DISPLAY_MISR_DSI0, 646 DISPLAY_MISR_DSI1, 647 DISPLAY_MISR_HDMI, 648 DISPLAY_MISR_LCDC, 649 DISPLAY_MISR_MDP, 650 DISPLAY_MISR_ATV, 651 DISPLAY_MISR_DSI_CMD, 652 DISPLAY_MISR_MAX 653}; 654 655enum { 656 MISR_OP_NONE, 657 MISR_OP_SFM, 658 MISR_OP_MFM, 659 MISR_OP_BM, 660 MISR_OP_MAX 661}; 662 663struct mdp_misr { 664 uint32_t block_id; 665 uint32_t frame_count; 666 uint32_t crc_op_mode; 667 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 668}; 669 670/* 671 672 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 673 674 MDP_BLOCK_RESERVED is provided for backward compatibility and is 675 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 676 instead. 677 678 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 679 same for others. 680 681*/ 682 683enum { 684 MDP_BLOCK_RESERVED = 0, 685 MDP_BLOCK_OVERLAY_0, 686 MDP_BLOCK_OVERLAY_1, 687 MDP_BLOCK_VG_1, 688 MDP_BLOCK_VG_2, 689 MDP_BLOCK_RGB_1, 690 MDP_BLOCK_RGB_2, 691 MDP_BLOCK_DMA_P, 692 MDP_BLOCK_DMA_S, 693 MDP_BLOCK_DMA_E, 694 MDP_BLOCK_OVERLAY_2, 695 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 696 MDP_LOGICAL_BLOCK_DISP_1, 697 MDP_LOGICAL_BLOCK_DISP_2, 698 MDP_BLOCK_MAX, 699}; 700 701/* 702 * mdp_histogram_start_req is used to provide the parameters for 703 * histogram start request 704 */ 705 706struct mdp_histogram_start_req { 707 uint32_t block; 708 uint8_t frame_cnt; 709 uint8_t bit_mask; 710 uint16_t num_bins; 711}; 712 713/* 714 * mdp_histogram_data is used to return the histogram data, once 715 * the histogram is done/stopped/cance 716 */ 717 718struct mdp_histogram_data { 719 uint32_t block; 720 uint32_t bin_cnt; 721 uint32_t *c0; 722 uint32_t *c1; 723 uint32_t *c2; 724 uint32_t *extra_info; 725}; 726 727struct mdp_pcc_coeff { 728 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 729}; 730 731struct mdp_pcc_cfg_data { 732 uint32_t block; 733 uint32_t ops; 734 struct mdp_pcc_coeff r, g, b; 735}; 736 737#define MDP_GAMUT_TABLE_NUM 8 738 739enum { 740 mdp_lut_igc, 741 mdp_lut_pgc, 742 mdp_lut_hist, 743 mdp_lut_max, 744}; 745 746struct mdp_ar_gc_lut_data { 747 uint32_t x_start; 748 uint32_t slope; 749 uint32_t offset; 750}; 751 752struct mdp_pgc_lut_data { 753 uint32_t block; 754 uint32_t flags; 755 uint8_t num_r_stages; 756 uint8_t num_g_stages; 757 uint8_t num_b_stages; 758 struct mdp_ar_gc_lut_data *r_data; 759 struct mdp_ar_gc_lut_data *g_data; 760 struct mdp_ar_gc_lut_data *b_data; 761}; 762 763 764struct mdp_lut_cfg_data { 765 uint32_t lut_type; 766 union { 767 struct mdp_igc_lut_data igc_lut_data; 768 struct mdp_pgc_lut_data pgc_lut_data; 769 struct mdp_hist_lut_data hist_lut_data; 770 } data; 771}; 772 773struct mdp_bl_scale_data { 774 uint32_t min_lvl; 775 uint32_t scale; 776}; 777 778struct mdp_pa_cfg_data { 779 uint32_t block; 780 struct mdp_pa_cfg pa_data; 781}; 782 783struct mdp_pa_v2_cfg_data { 784 uint32_t block; 785 struct mdp_pa_v2_data pa_v2_data; 786}; 787 788struct mdp_dither_cfg_data { 789 uint32_t block; 790 uint32_t flags; 791 uint32_t g_y_depth; 792 uint32_t r_cr_depth; 793 uint32_t b_cb_depth; 794}; 795 796struct mdp_gamut_cfg_data { 797 uint32_t block; 798 uint32_t flags; 799 uint32_t gamut_first; 800 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 801 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 802 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 803 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 804}; 805 806struct mdp_calib_config_data { 807 uint32_t ops; 808 uint32_t addr; 809 uint32_t data; 810}; 811 812struct mdp_calib_config_buffer { 813 uint32_t ops; 814 uint32_t size; 815 uint32_t *buffer; 816}; 817 818struct mdp_calib_dcm_state { 819 uint32_t ops; 820 uint32_t dcm_state; 821}; 822 823enum { 824 DCM_UNINIT, 825 DCM_UNBLANK, 826 DCM_ENTER, 827 DCM_EXIT, 828 DCM_BLANK, 829 DTM_ENTER, 830 DTM_EXIT, 831}; 832 833#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 834#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 835#define MDSS_PP_SPLIT_MASK 0x30000000 836 837#define MDSS_MAX_BL_BRIGHTNESS 255 838#define AD_BL_LIN_LEN 256 839#define AD_BL_ATT_LUT_LEN 33 840 841#define MDSS_AD_MODE_AUTO_BL 0x0 842#define MDSS_AD_MODE_AUTO_STR 0x1 843#define MDSS_AD_MODE_TARG_STR 0x3 844#define MDSS_AD_MODE_MAN_STR 0x7 845#define MDSS_AD_MODE_CALIB 0xF 846 847#define MDP_PP_AD_INIT 0x10 848#define MDP_PP_AD_CFG 0x20 849 850struct mdss_ad_init { 851 uint32_t asym_lut[33]; 852 uint32_t color_corr_lut[33]; 853 uint8_t i_control[2]; 854 uint16_t black_lvl; 855 uint16_t white_lvl; 856 uint8_t var; 857 uint8_t limit_ampl; 858 uint8_t i_dither; 859 uint8_t slope_max; 860 uint8_t slope_min; 861 uint8_t dither_ctl; 862 uint8_t format; 863 uint8_t auto_size; 864 uint16_t frame_w; 865 uint16_t frame_h; 866 uint8_t logo_v; 867 uint8_t logo_h; 868 uint32_t alpha; 869 uint32_t alpha_base; 870 uint32_t bl_lin_len; 871 uint32_t bl_att_len; 872 uint32_t *bl_lin; 873 uint32_t *bl_lin_inv; 874 uint32_t *bl_att_lut; 875}; 876 877#define MDSS_AD_BL_CTRL_MODE_EN 1 878#define MDSS_AD_BL_CTRL_MODE_DIS 0 879struct mdss_ad_cfg { 880 uint32_t mode; 881 uint32_t al_calib_lut[33]; 882 uint16_t backlight_min; 883 uint16_t backlight_max; 884 uint16_t backlight_scale; 885 uint16_t amb_light_min; 886 uint16_t filter[2]; 887 uint16_t calib[4]; 888 uint8_t strength_limit; 889 uint8_t t_filter_recursion; 890 uint16_t stab_itr; 891 uint32_t bl_ctrl_mode; 892}; 893 894/* ops uses standard MDP_PP_* flags */ 895struct mdss_ad_init_cfg { 896 uint32_t ops; 897 union { 898 struct mdss_ad_init init; 899 struct mdss_ad_cfg cfg; 900 } params; 901}; 902 903/* mode uses MDSS_AD_MODE_* flags */ 904struct mdss_ad_input { 905 uint32_t mode; 906 union { 907 uint32_t amb_light; 908 uint32_t strength; 909 uint32_t calib_bl; 910 } in; 911 uint32_t output; 912}; 913 914#define MDSS_CALIB_MODE_BL 0x1 915struct mdss_calib_cfg { 916 uint32_t ops; 917 uint32_t calib_mask; 918}; 919 920enum { 921 mdp_op_pcc_cfg, 922 mdp_op_csc_cfg, 923 mdp_op_lut_cfg, 924 mdp_op_qseed_cfg, 925 mdp_bl_scale_cfg, 926 mdp_op_pa_cfg, 927 mdp_op_pa_v2_cfg, 928 mdp_op_dither_cfg, 929 mdp_op_gamut_cfg, 930 mdp_op_calib_cfg, 931 mdp_op_ad_cfg, 932 mdp_op_ad_input, 933 mdp_op_calib_mode, 934 mdp_op_calib_buffer, 935 mdp_op_calib_dcm_state, 936 mdp_op_max, 937}; 938 939enum { 940 WB_FORMAT_NV12, 941 WB_FORMAT_RGB_565, 942 WB_FORMAT_RGB_888, 943 WB_FORMAT_xRGB_8888, 944 WB_FORMAT_ARGB_8888, 945 WB_FORMAT_BGRA_8888, 946 WB_FORMAT_BGRX_8888, 947 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 948}; 949 950struct msmfb_mdp_pp { 951 uint32_t op; 952 union { 953 struct mdp_pcc_cfg_data pcc_cfg_data; 954 struct mdp_csc_cfg_data csc_cfg_data; 955 struct mdp_lut_cfg_data lut_cfg_data; 956 struct mdp_qseed_cfg_data qseed_cfg_data; 957 struct mdp_bl_scale_data bl_scale_data; 958 struct mdp_pa_cfg_data pa_cfg_data; 959 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 960 struct mdp_dither_cfg_data dither_cfg_data; 961 struct mdp_gamut_cfg_data gamut_cfg_data; 962 struct mdp_calib_config_data calib_cfg; 963 struct mdss_ad_init_cfg ad_init_cfg; 964 struct mdss_calib_cfg mdss_calib_cfg; 965 struct mdss_ad_input ad_input; 966 struct mdp_calib_config_buffer calib_buffer; 967 struct mdp_calib_dcm_state calib_dcm; 968 } data; 969}; 970 971#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 972enum { 973 metadata_op_none, 974 metadata_op_base_blend, 975 metadata_op_frame_rate, 976 metadata_op_vic, 977 metadata_op_wb_format, 978 metadata_op_wb_secure, 979 metadata_op_get_caps, 980 metadata_op_crc, 981 metadata_op_max 982}; 983 984struct mdp_blend_cfg { 985 uint32_t is_premultiplied; 986}; 987 988struct mdp_mixer_cfg { 989 uint32_t writeback_format; 990 uint32_t alpha; 991}; 992 993struct mdss_hw_caps { 994 uint32_t mdp_rev; 995 uint8_t rgb_pipes; 996 uint8_t vig_pipes; 997 uint8_t dma_pipes; 998 uint8_t max_smp_cnt; 999 uint8_t smp_per_pipe; 1000 uint32_t features; 1001}; 1002 1003struct msmfb_metadata { 1004 uint32_t op; 1005 uint32_t flags; 1006 union { 1007 struct mdp_misr misr_request; 1008 struct mdp_blend_cfg blend_cfg; 1009 struct mdp_mixer_cfg mixer_cfg; 1010 uint32_t panel_frame_rate; 1011 uint32_t video_info_code; 1012 struct mdss_hw_caps caps; 1013 uint8_t secure_en; 1014 } data; 1015}; 1016 1017#define MDP_MAX_FENCE_FD 32 1018#define MDP_BUF_SYNC_FLAG_WAIT 1 1019#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1020 1021struct mdp_buf_sync { 1022 uint32_t flags; 1023 uint32_t acq_fen_fd_cnt; 1024 uint32_t session_id; 1025 int *acq_fen_fd; 1026 int *rel_fen_fd; 1027 int *retire_fen_fd; 1028}; 1029 1030struct mdp_async_blit_req_list { 1031 struct mdp_buf_sync sync; 1032 uint32_t count; 1033 struct mdp_blit_req req[]; 1034}; 1035 1036#define MDP_DISPLAY_COMMIT_OVERLAY 1 1037 1038struct mdp_display_commit { 1039 uint32_t flags; 1040 uint32_t wait_for_finish; 1041 struct fb_var_screeninfo var; 1042 struct mdp_rect l_roi; 1043 struct mdp_rect r_roi; 1044}; 1045 1046/** 1047 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1048 * @num_overlays: Number of overlay layers as part of the frame. 1049 * @overlay_list: Pointer to a list of overlay structures identifying 1050 * the layers as part of the frame 1051 * @flags: Flags can be used to extend behavior. 1052 * @processed_overlays: Output parameter indicating how many pipes were 1053 * successful. If there are no errors this number should 1054 * match num_overlays. Otherwise it will indicate the last 1055 * successful index for overlay that couldn't be set. 1056 */ 1057struct mdp_overlay_list { 1058 uint32_t num_overlays; 1059 struct mdp_overlay **overlay_list; 1060 uint32_t flags; 1061 uint32_t processed_overlays; 1062}; 1063 1064struct mdp_page_protection { 1065 uint32_t page_protection; 1066}; 1067 1068 1069struct mdp_mixer_info { 1070 int pndx; 1071 int pnum; 1072 int ptype; 1073 int mixer_num; 1074 int z_order; 1075}; 1076 1077#define MAX_PIPE_PER_MIXER 4 1078 1079struct msmfb_mixer_info_req { 1080 int mixer_num; 1081 int cnt; 1082 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1083}; 1084 1085struct msmfb_secure_config { 1086 uint8_t enable; 1087 uint32_t fd; 1088}; 1089 1090struct msmfb_reg_access { 1091 uint8_t address; 1092 uint8_t use_hs_mode; 1093 size_t buffer_size; 1094 void __user *buffer; 1095}; 1096 1097enum { 1098 DISPLAY_SUBSYSTEM_ID, 1099 ROTATOR_SUBSYSTEM_ID, 1100}; 1101 1102enum { 1103 MDP_IOMMU_DOMAIN_CP, 1104 MDP_IOMMU_DOMAIN_NS, 1105}; 1106 1107enum { 1108 MDP_WRITEBACK_MIRROR_OFF, 1109 MDP_WRITEBACK_MIRROR_ON, 1110 MDP_WRITEBACK_MIRROR_PAUSE, 1111 MDP_WRITEBACK_MIRROR_RESUME, 1112}; 1113#endif /*_UAPI_MSM_MDP_H_*/ 1114