1595815c2a914a78df7dfb6f0082f47d4e82bb36 |
|
10-Feb-2017 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Implement read barriers. This is the core functionality. Further improvements will be done separately. This also adds/moves memory barriers where they belong and removes the UnsafeGetLongVolatile and UnsafePutLongVolatile MIPS32 intrinsics as they need to load/store a pair of registers atomically, which is not supported directly by the CPU. Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: "testrunner.py --target --optimizing -j1" Test: same MIPS64 boot/test with ART_READ_BARRIER_TYPE=TABLELOOKUP Test: "testrunner.py --target --optimizing --32 -j2" on CI20 Test: same CI20 test with ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I0ff91525fefba3ec1cc019f50316478a888acced
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ba89c34e94a82f0a6904dcc62caa6aa7bb14c12c |
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10-Mar-2017 |
Tijana Jakovljevic <tijana.jakovljevic@imgtec.com> |
MIPS64: Improve storing of constants in fields and array elements Test: booted MIPS64 in QEMU Test: mma test-art-target-run-test Test: mma test-art-host-gtest-assembler_mips64_test Change-Id: I8e0002166174eebea1309358eb9d96f34eee3225
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c52f3034b06c03632e937aff07d46c2bdcadfef5 |
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02-Mar-2017 |
Richard Uhler <ruhler@google.com> |
Remove --include-patch-information option from dex2oat. Because we no longer support running patchoat on npic oat files, which means the included patch information is unused . Bug: 33192586 Test: m test-art-host Change-Id: I9e100c4e47dc24d91cd74226c84025e961d30f67
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627c1a0e573b4512e68f097771d7fdd4d8c7f7de |
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31-Jan-2017 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Support kJitTableAddress kinds of string/class loads. Also remove a few stale comments. Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: "make -j1 ART_TEST_DEFAULT_COMPILER=false ART_TEST_OPTIMIZING=false ART_TEST_INTERPRETER=false ART_TEST_JIT=true test-art-target-run-test" Test: booted MIPS32R2 in QEMU Change-Id: I8914b8e6594e030f8137e7fface1ae20b6d6b971
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0cb124219e986a27c40001a1b22ea7ebd833a2d8 |
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26-Jan-2017 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Refactor code for unresolved field entrypoint. This is a follow-up to https://android-review.googlesource.com/#/c/325423/. Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test-optimizing in QEMU Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS64R6 and MIPS32R6) in QEMU Change-Id: Ie663ecf0489e7b182434708bef71686df5f37273
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1998cd02603197f2acdc0734397a6d48b2f59b80 |
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13-Jan-2017 |
Vladimir Marko <vmarko@google.com> |
Implement HLoadClass/kBssEntry for boot image. Test: m test-art-host Test: m test-art-host with CC Test: m test-art-target on Nexus 9 Test: Nexus 9 boots. Test: Build aosp_mips64-eng Bug: 30627598 Change-Id: I168f24dedd5fb54a1e4215ecafb947ffb0dc3280
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6bec91c7d4670905cd67440991ec76fd54d0f000 |
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09-Jan-2017 |
Vladimir Marko <vmarko@google.com> |
Store resolved types for AOT code in .bss. Test: m test-art-host Test: m test-art-target on Nexus 9. Test: Nexus 9 boots. Test: Build aosp_mips64-eng. Bug: 30627598 Bug: 34193123 Change-Id: I8ec60a98eb488cb46ae3ea56341f5709dad4f623
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4375819125bce2132cde663ba5024e33d7bd2681 |
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30-Dec-2016 |
Tijana Jakovljevic <tijana.jakovljevic@imgtec.com> |
MIPS64: Implement branchless HCondition for floats Test: mma test-art-target-run-test64 in QEMU Change-Id: I595b5b7ddf9ebb19e872ed85f2e4098a835d9214
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c378980e32f0ec9ab7f1d0b87e1d5b97c1f3972c |
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22-Dec-2016 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Align register spills on 8-byte boundaries in slow paths 64-bit loads/stores would otherwise be split into pairs of 32-bit ones. Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS64R6) in QEMU Change-Id: I4846d11b52b71507dfd5ca2e27b3f2a5befcc58e
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0960ac5a5a255bb3e8418e185914243aeef54a7c |
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21-Dec-2016 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Implement table-based packed switch Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS64R6) in QEMU Test: test-art-host-gtest Change-Id: I333dca43fca57ae7e6021bb84585487c889417c3
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c1a42cf3873be202c8c0ca3c4e67500b470ab075 |
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18-Dec-2016 |
Nicolas Geoffray <ngeoffray@google.com> |
Remove soon to be obsolete call kinds for direct calls. And remove CompilerDriver::GetCodeAndMethodForDirectCall in preparation of removing non-PIC prebuild and non-PIC on-device boot image compilation. Test: test-art-host test-art-target bug:33192586 Change-Id: Ic48e3e8b9d7605dd0e66f31d458a182198ba9578
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f63f569eeefe3907c48a175494a2a0ba351b641a |
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14-Dec-2016 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Improve string and class loads. This adds most kinds of string/class loads. JIT string/class loads are TBD separately. This also fixes Mips64Assembler::LoadLabelAddress() (adding a constant to a 64-bit address must be done using daddiu, not addiu). Test: test-art-host-gtest Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: "make -j1 ART_TEST_DEFAULT_COMPILER=false ART_TEST_OPTIMIZING=true ART_TEST_INTERPRETER=false ART_TEST_JIT=false ART_TEST_PIC_TEST=true test-art-target-run-test64" Change-Id: I1f94ece4cd202382c11167e1ed958e9d08d92822
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19f6c696bbb7a17d8ac521b316c40f9cbef32151 |
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01-Dec-2016 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Improve method invocation. Improvements include: - support for all kinds of method loads and static/direct calls - 32-bit and 64-bit literals for the above and future work - shorter instruction sequences for recursive static/direct calls Also: - include the MIPS64 dinsu instruction (missed earlier) and minor clean-up in the disassembler - properly prefix constant names with 'k' in relative patcher tests Test: test-art-host-gtest Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: "make -j1 ART_TEST_DEFAULT_COMPILER=false ART_TEST_OPTIMIZING=true ART_TEST_INTERPRETER=false ART_TEST_JIT=false ART_TEST_PIC_TEST=true test-art-target-run-test64" Change-Id: I19876fa5316b68531af7dfddfce90d2068433116
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5e4e11e171f90d9a3ea178fc8e72aac909de55d5 |
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22-Sep-2016 |
Nicolas Geoffray <ngeoffray@google.com> |
Clean-up sharpening and compiler driver. Remove dependency on compiler driver for sharpening and dex2dex (the methods called on the compiler driver were doing unnecessary work), and remove the now unused methods in compiler driver. Also remove test that is now invalid, as sharpening always succeeds. test: m test-art-host m test-art-target Change-Id: I54e91c6839bd5b0b86182f2f43ba5d2c112ef908
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f41f956558ceb5402d3b4499a44a15c42f1c0064 |
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14-Sep-2016 |
Roland Levillain <rpl@google.com> |
Add missing OVERRIDE qualifiers in code generators. Test: mmma art Change-Id: I91d0a2dc23dc8d63a9bb3607eb1c1517eabaeb1f
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fc734088e6656a918b6c75094eb942a22bd799e8 |
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19-Jul-2016 |
Serban Constantinescu <serban.constantinescu@linaro.org> |
Extend the InvokeRuntime() changes to mips64. Change-Id: I3f825746053b9288ca31ab5e823d6a1648dfd894
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26de38bb7f2122417388809f4ff88a7cb5c4af5e |
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28-Jul-2016 |
Andreas Gampe <agampe@google.com> |
ART: Delete old compiler_enums.h Holdover from the Quick days. Move the two enums that are still used closer to the actual users (and prune no longer used cases). Test: m test-art-host Change-Id: I88aa49961a54635788cafac570ddc3125aa38262
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dbb7f5bef10138ade0fb202da1d61f562b2df649 |
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30-Mar-2016 |
Vladimir Marko <vmarko@google.com> |
Improve HLoadClass code generation. For classes in the boot image, use either direct pointers or PC-relative addresses. For other classes, use PC-relative access to the dex cache arrays for AOT and direct address of the type's dex cache slot for JIT. For aosp_flounder-userdebug: - 32-bit boot.oat: -252KiB (-0.3%) - 64-bit boot.oat: -412KiB (-0.4%) - 32-bit dalvik cache total: -392KiB (-0.4%) - 64-bit dalvik-cache total: -2312KiB (-1.0%) (contains more files than the 32-bit dalvik cache) For aosp_flounder-userdebug forced to compile PIC: - 32-bit boot.oat: -124KiB (-0.2%) - 64-bit boot.oat: -420KiB (-0.5%) - 32-bit dalvik cache total: -136KiB (-0.1%) - 64-bit dalvik-cache total: -1136KiB (-0.5%) (contains more files than the 32-bit dalvik cache) Bug: 27950288 Change-Id: I4da991a4b7e53c63c92558b97923d18092acf139
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c393d63aa2b8f6984672fdd4de631bbeff14b6a2 |
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15-Apr-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Fix: correctly destruct VIXL labels. (cherry picked from commit c01a66465a398ad15da90ab2bdc35b7f4a609b17) Bug: 27505766 Change-Id: I077465e3d308f4331e7a861902e05865f9d99835
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c01a66465a398ad15da90ab2bdc35b7f4a609b17 |
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15-Apr-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Fix: correctly destruct VIXL labels. Bug: 27505766 Change-Id: I077465e3d308f4331e7a861902e05865f9d99835
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dee58d6bb6d567fcd0c4f39d8d690c3acaf0e432 |
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07-Apr-2016 |
David Brazdil <dbrazdil@google.com> |
Revert "Revert "Refactor HGraphBuilder and SsaBuilder to remove HLocals"" This patch merges the instruction-building phases from HGraphBuilder and SsaBuilder into a single HInstructionBuilder class. As a result, it is not necessary to generate HLocal, HLoadLocal and HStoreLocal instructions any more, as the builder produces SSA form directly. Saves 5-15% of arena-allocated memory (see bug for more data): GMS 20.46MB => 19.26MB (-5.86%) Maps 24.12MB => 21.47MB (-10.98%) YouTube 28.60MB => 26.01MB (-9.05%) This CL fixed an issue with parsing quickened instructions. Bug: 27894376 Bug: 27998571 Bug: 27995065 Change-Id: I20dbe1bf2d0fe296377478db98cb86cba695e694
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60328910cad396589474f8513391ba733d19390b |
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04-Apr-2016 |
David Brazdil <dbrazdil@google.com> |
Revert "Refactor HGraphBuilder and SsaBuilder to remove HLocals" Bug: 27995065 This reverts commit e3ff7b293be2a6791fe9d135d660c0cffe4bd73f. Change-Id: I5363c7ce18f47fd422c15eed5423a345a57249d8
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e3ff7b293be2a6791fe9d135d660c0cffe4bd73f |
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02-Mar-2016 |
David Brazdil <dbrazdil@google.com> |
Refactor HGraphBuilder and SsaBuilder to remove HLocals This patch merges the instruction-building phases from HGraphBuilder and SsaBuilder into a single HInstructionBuilder class. As a result, it is not necessary to generate HLocal, HLoadLocal and HStoreLocal instructions any more, as the builder produces SSA form directly. Saves 5-15% of arena-allocated memory (see bug for more data): GMS 20.46MB => 19.26MB (-5.86%) Maps 24.12MB => 21.47MB (-10.98%) YouTube 28.60MB => 26.01MB (-9.05%) Bug: 27894376 Change-Id: Iefe28d40600c169c5d306fd2c77034ae19476d90
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cac5a7e871f1f346b317894359ad06fa7bd67fba |
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22-Feb-2016 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Improve const-string code generation. For strings in the boot image, use either direct pointers or pc-relative addresses. For other strings, use PC-relative access to the dex cache arrays for AOT and direct address of the string's dex cache slot for JIT. For aosp_flounder-userdebug: - 32-bit boot.oat: -692KiB (-0.9%) - 64-bit boot.oat: -948KiB (-1.1%) - 32-bit dalvik cache total: -900KiB (-0.9%) - 64-bit dalvik cache total: -3672KiB (-1.5%) (contains more files than the 32-bit dalvik cache) For aosp_flounder-userdebug forced to compile PIC: - 32-bit boot.oat: -380KiB (-0.5%) - 64-bit boot.oat: -928KiB (-1.0%) - 32-bit dalvik cache total: -468KiB (-0.4%) - 64-bit dalvik cache total: -1928KiB (-0.8%) (contains more files than the 32-bit dalvik cache) Bug: 26884697 Change-Id: Iec7266ce67e6fedc107be78fab2e742a8dab2696
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2ae48182573da7087bffc2873730bc758ec29696 |
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16-Mar-2016 |
Calin Juravle <calin@google.com> |
Clean up NullCheck generation and record stats about it. This removes redundant code from the generators and allows for easier stat recording. Change-Id: Iccd4368f9e9d87a6fecb863dee4e2145c97851c4
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9cd6d378bd573cdc14d049d32bdd22a97fa4d84a |
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09-Feb-2016 |
David Srbecky <dsrbecky@google.com> |
Associate slow paths with the instruction that they belong to. Almost all slow paths already know the instruction they belong to, this CL just moves the knowledge to the base class as well. This is needed to be be able to get the corresponding dex pc for slow path, which allows us generate better native line numbers, which in turn fixes some native debugging stepping issues. Change-Id: I568dbe78a7cea6a43a4a71a014b3ad135782c270
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c7098ff991bb4e00a800d315d1c36f52a9cb0149 |
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09-Feb-2016 |
David Srbecky <dsrbecky@google.com> |
Remove HNativeDebugInfo from start of basic blocks. We do not require full environment at the start of basic block. The dex pc contained in basic block is sufficient for line mapping. Change-Id: I5ba9e5f5acbc4a783ad544769f9a73bb33e2bafa
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6e332529c33be4d7dae5dad3609a839f4c0d3bfc |
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02-Feb-2016 |
David Brazdil <dbrazdil@google.com> |
ART: Remove HTemporary Change-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03
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3acee732f9475fbfc6b046e0044b764e7ff5ac01 |
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18-Nov-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS32: peek*/poke*, and String.charAt intrinsics. - byte libcore.io.Memory.peekByte(long address) - short libcore.io.Memory.peekShort(long address) - int libcore.io.Memory.peekInt(long address) - long libcore.io.Memory.peekLong(long address) - void libcore.io.Memory.pokeByte(long address, byte value) - void libcore.io.Memory.pokeShort(long address, short value) - void libcore.io.Memory.pokeInt(long address, int value) - void libcore.io.Memory.pokeLong(long address, long value) - char java.lang.String.charAt(int index) Change-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa
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d967266cdfc8011c81ba6e9857a247c4a73bd0fc |
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03-Sep-2015 |
Lazar Trsic <Lazar.Trsic@imgtec.com> |
MIPS64: Remove unaligned memory access from art generated code Unaligned memory access was caused by sd, ld, ldc1 and sdc1 instructions. Check if offset is unaligned and replace it with two 32 bit memory accesses, if so. Added assembler tests for new instructions, as well as assembler tests for LoadFromOffset, LoadFpuFromOffset, StoreToOffset and StoreFpuToOffset. Change-Id: I0228a4a2ce6c801eeb5b46952b8330e14468deb3
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8ed1826a9da054920f2d39d34dfc7ba43337e4c9 |
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22-Jan-2016 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
Fix MIPS64 booting problem Add missing MarkGCCard in compareAndSwapObject intinsic. Additionaly, don't do a null test in MarkGCCard if the value cannot be null for MIPS64. Change-Id: Iad50f9e6be8cd27fedb31abb00d5829498941696
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58282f4510961317b8d5a364a6f740a78926716f |
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14-Jan-2016 |
David Brazdil <dbrazdil@google.com> |
ART: Remove Baseline compiler We don't need Baseline any more and it hasn't been maintained for a while anyway. Let's remove it. Change-Id: I442ed26855527be2df3c79935403a25b1ee55df6
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42249c3602c3d0243396ee3627ffb5906aa77c1e |
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08-Jan-2016 |
Aart Bik <ajcbik@google.com> |
Reduce code size by sharing slow paths. Rationale: Sharing identical slow path code reduces code size. Background: Currently, slow paths with the same dex-pc, same physical register spilling code, and identical stack maps are shared (making this only useful for deopt slow paths). The newly introduced mechanism is sufficiently general to allow future improvements by e.g. allowing different dex-pc (by passing this to runtime) or even the kind of slow paths (by passing runtime addresses to the slowpath). Change-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0
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5f7b58ea1adfc0639dd605b65f59198d3763f801 |
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23-Nov-2015 |
Vladimir Marko <vmarko@google.com> |
Rewrite HInstruction::Is/As<type>(). Make Is<type>() and As<type>() non-virtual for concrete instruction types, relying on GetKind(), and mark GetKind() as PURE to improve optimization opportunities. This reduces the number of relocations in libart-compiler.so's .rel.dyn section by ~4K, or ~44%, and in .data.rel.ro by ~18K, or ~65%. The file is 96KiB smaller for Nexus 5, including 8KiB reduction of the .text section. Unfortunately, the g++/clang++ __attribute__((pure)) is not strong enough to avoid duplicated virtual calls and we would need the C++ [[pure]] attribute proposed in n3744 instead. To work around this deficiency, we introduce an extra non-virtual indirection for GetKind(), so that the compiler can optimize common expressions such as instruction->IsAdd() || instruction->IsSub() or instruction->IsAdd() && instruction->AsAdd()->... which contain two virtual calls to GetKind() after inlining. Change-Id: I83787de0671a5cb9f5b0a5f4a536cef239d5b401
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299a93993fb8f3efbf0465cf674d80c3bcfdc66c |
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09-Dec-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Fuse long and FP compare & condition in Optimizing. Bug: 25559148 Change-Id: I2d14ac75460a76848c71c08cffff6d7a18f5f580
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a0e87b0a97fadd54540ec7e8331b61bebd82d378 |
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25-Sep-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Support short and long branches Change-Id: I618c960bd211048166d9fde78d4106bd3ca42b3a
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0debae7bc89eb05f7a2bf7dccd223318fad7c88d |
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12-Nov-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Refactor GenerateTestAndBranch Each code generator implements a method for generating condition evaluation and branching to arbitrary labels. This patch refactors it for better clarity but also to generate fewer jumps when the true branch is the fallthrough successor. This is preliminary work for implementing HSelect. Change-Id: Iaa545a5ecbacb761c5aa241fa69140cf6eb5952f
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00580bdbbb119a354c94a9c19928c1dcbd14a8f4 |
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11-Nov-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: fix calling conventions in LoadClass and field accesses This fixes failures in test 529-checker-unresolved Change-Id: I6170c22059e9711b2fcc965b00d6e34edd839539
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c857c746707dfd45d74b75cb7fa84484ca68cc2a |
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24-Sep-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Improve integer division by constants This also removes some unused instructions and instructions not available on MIPS64R6. Change-Id: I44bfe12c60344312c88c45e97b6b07dcd5bdc630
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53afca191ace3d7447b09097f9ea82a513075c52 |
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06-Nov-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Implement virtual intrinsic slow path This fixes a crash in dex2oat while compiling boot.oat. Change-Id: I44fc92809902d7fc226c88b3e3f081b72cc19ce5
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dc151b2346bb8a4fdeed0c06e54c2fca21d59b5d |
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15-Oct-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Determine invoke-static/-direct dispatch early. Determine the dispatch type of invoke-static/-direct in a special pass right after the type inference. This allows the inliner to pass the "needs dex cache" check and inline more. It also allows the code generator to avoid requesting a register location for the ArtMethod* for kDexCachePcRelative and direct methods. The supported dispatch check handles also situations that the CompilerDriver currently doesn't allow. The cleanup of the CompilerDriver and required changes to Quick will come in a separate change. Change-Id: I3f8e903a119949e95871d8ab0a995f4731a13a07
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f652cecb984c104d44a0223c3c98400ef8ed8ce2 |
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25-Aug-2015 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS: Initial version of optimizing compiler for MIPS32 Change-Id: I370388e8d5de52c7001552b513877ef5833aa621
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8c34ec1ede2608eb99a7e26253b6253931dcb7ab |
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14-Oct-2015 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
Fix MIPS64 boot Return register in FieldAccessCallingConventionMIPS64 was A0, but it should be V0. With this change, the system server doesn't crash. Change-Id: Id52f684658d235fd001d9784145f4ea5ed2938b6
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e460d1df1f789c7c8bb97024a8efbd713ac175e9 |
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29-Sep-2015 |
Calin Juravle <calin@google.com> |
Revert "Revert "Support unresolved fields in optimizing" The CL also changes the calling convetion for 64bit static field set to use kArg2 instead of kArg1. This allows optimizing to keep the asumptions: - arm pairs are always of form (even_reg, odd_reg) - ecx_edx is not used as a register on x86. This reverts commit e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1. Change-Id: I93159917565824084abc96775f31be1a4249f2f3
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225b6464a58ebe11c156144653f11a1c6607f4eb |
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28-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag arena allocations in code generators. And completely remove the deprecated GrowableArray. Replace GrowableArray with ArenaVector in code generators and related classes and tag arena allocations. Label arrays use direct allocations from ArenaAllocator because Label is non-copyable and non-movable and as such cannot be really held in a container. The GrowableArray never actually constructed them, instead relying on the zero-initialized storage from the arena allocator to be correct. We now actually construct the labels. Also avoid StackMapStream::ComputeDexRegisterMapSize() being passed null references, even though unused. Change-Id: I26a46fdd406b23a3969300a67739d55528df8bf4
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85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d |
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09-Sep-2015 |
Andreas Gampe <agampe@google.com> |
ART: Refactor intrinsics slow-paths Refactor slow paths so that there is a default implementation for common cases (only arm64 with vixl is special). Write a generic intrinsic slow-path that can be reused for the specific architectures. Move helper functions into CodeGenerator so that they are accessible. Change-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550
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e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1 |
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17-Sep-2015 |
Calin Juravle <calin@google.com> |
Revert "Support unresolved fields in optimizing" breaks debuggable tests. This reverts commit 23a8e35481face09183a24b9d11e505597c75ebb. Change-Id: I8e60b5c8f48525975f25d19e5e8066c1c94bd2e5
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23a8e35481face09183a24b9d11e505597c75ebb |
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08-Sep-2015 |
Calin Juravle <calin@google.com> |
Support unresolved fields in optimizing Change-Id: I9941fa5fcb6ef0a7a253c7a0b479a44a0210aad4
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175dc732c80e6f2afd83209348124df349290ba8 |
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25-Aug-2015 |
Calin Juravle <calin@google.com> |
Support unresolved methods in Optimizing Change-Id: If2da02b50d2fa668cd58f134a005f1752e7746b1
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fa6b93c4b69e6d7ddfa2a4ed0aff01b0608c5a3a |
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15-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag arena allocations in HGraph. Replace GrowableArray with ArenaVector in HGraph and related classes HEnvironment, HLoopInformation, HInvoke and HPhi, and tag allocations with new arena allocation types. Change-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d
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ecc4366670e12b4812ef1653f7c8d52234ca1b1f |
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13-Aug-2015 |
Serban Constantinescu <serban.constantinescu@linaro.org> |
Add OptimizingCompilerStats to the CodeGenerator class. Just refactoring, not yet used, but will be used by the incoming patch series and future CodeGen specific stats. Change-Id: I7d20489907b82678120518a77bdab9c4cc58f937 Signed-off-by: Serban Constantinescu <serban.constantinescu@linaro.org>
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a1935c4fa255b5c20f5e9b2abce6be2d0f7cb0a8 |
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26-Jun-2015 |
Roland Levillain <rpl@google.com> |
MIPS: Initial version of optimizing compiler for MIPS64R6. (cherry picked from commit 4dda3376b71209fae07f5c3c8ac3eb4b54207aa8) (amended for mnc-dev) Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
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fc6a86ab2b70781e72b807c1798b83829ca7f931 |
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26-Jun-2015 |
David Brazdil <dbrazdil@google.com> |
Revert "Revert "ART: Implement try/catch blocks in Builder"" This patch enables the GraphBuilder to generate blocks and edges which represent the exceptional control flow when try/catch blocks are present in the code. Actual compilation is still delegated to Quick and Baseline ignores the additional code. To represent the relationship between try and catch blocks, Builder splits the edges which enter/exit a try block and links the newly created blocks to the corresponding exception handlers. This layout will later enable the SsaBuilder to correctly infer the dominators of the catch blocks and to produce the appropriate reverse post ordering. It will not, however, allow for building the complete SSA form of the catch blocks and consequently optimizing such blocks. To this end, a new TryBoundary control-flow instruction is introduced. Codegen treats it the same as a Goto but it allows for additional successors (the handlers). This reverts commit 3e18738bd338e9f8363b26bc895f38c0ec682824. Change-Id: I4f5ea961848a0b83d8db3673763861633e9bfcfb
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3e18738bd338e9f8363b26bc895f38c0ec682824 |
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26-Jun-2015 |
David Brazdil <dbrazdil@google.com> |
Revert "ART: Implement try/catch blocks in Builder" Causes OutOfMemory issues, need to investigate. This reverts commit 0b5c7d1994b76090afcc825e737f2b8c546da2f8. Change-Id: I263e6cc4df5f9a56ad2ce44e18932ca51d7e349f
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0b5c7d1994b76090afcc825e737f2b8c546da2f8 |
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11-Jun-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Implement try/catch blocks in Builder This patch enables the GraphBuilder to generate blocks and edges which represent the exceptional control flow when try/catch blocks are present in the code. Actual compilation is still delegated to Quick and Baseline ignores the additional code. To represent the relationship between try and catch blocks, Builder splits the edges which enter/exit a try block and links the newly created blocks to the corresponding exception handlers. This layout will later enable the SsaBuilder to correctly infer the dominators of the catch blocks and to produce the appropriate reverse post ordering. It will not, however, allow for building the complete SSA form of the catch blocks and consequently optimizing such blocks. To this end, a new TryBoundary control-flow instruction is introduced. Codegen treats it the same as a Goto but it allows for additional successors (the handlers). Change-Id: I415b985596d5bebb7b1bb358a46e08b7b04bb53a
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f39e0641a6d1a6561b20f6a130d1e763788cd70b |
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23-Jun-2015 |
Alexandre Rames <alexandre.rames@linaro.org> |
Minor fixes to mips64 for the arch-specific optimisation framework. Change-Id: I9d49ea61c732e4fc6b3393aa8778951e29ce4efe
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eb7b7399dbdb5e471b8ae00a567bf4f19edd3907 |
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19-Jun-2015 |
Alexandre Rames <alexandre.rames@linaro.org> |
Opt compiler: Add disassembly to the '.cfg' output. This is automatically added to the '.cfg' output when using the usual `--dump-cfg` option. Change-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb
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4dda3376b71209fae07f5c3c8ac3eb4b54207aa8 |
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02-Jun-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Initial version of optimizing compiler for MIPS64R6. Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
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