| 31afbec96e9f9c8e58778694e74aea7ce55e1378 |
|
14-Mar-2017 |
buzbee <buzbee@google.com> |
ART: Bit intrinsics for Mterp interpreter
Another batch of interpreter intrinisics, mostly around bit
manipulation. Also some formatting changes and inclusion of a
comprehensive list of recognized intrinisics (to assist with
telling what's left to do).
Bug: 30933338
Benchmarks:
20% Improvement for Reversi
10% Improvement for Scimark2
3% Improvement for ChessBench
Test: ART_TEST_INTERPRETER=true m test-art-host
Test: art/tools/run-libcore-tests --host (edited for force -Xint)
Note: Added intrinsics have existing test coverage via
082-inline-execute, 123-inline-execute2, 565-checker-rotate,
564-checker-bitcount, 566-checker-signum & 567-checker-compare
Change-Id: I29f0386e28eddba37c44f9ced44e7d5f8206bb47
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| 3c3c4a1da1e8c03e78813d175a9974fb9f1097ea |
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22-Feb-2017 |
Hiroshi Yamauchi <yamauchi@google.com> |
Improve the region space memory mapping.
Add a region space mmap fallback when the initial address isn't
available.
Clean up around the asan-specific base address.
Add MemMap::AlignBy to align the region space base address by the
region size, which is currently required by ReadBarrierTable.
Disable some read barriers in ZygoteCompactingCollector to avoid a
DCHECK failure in LockWord::SetMarkBitState when classes are in the
forward state due to unnecessary read barriers on
SizeOf/VisitReference.
Bug: 12687968
Test: test-art-host with CC and CMS.
Test: marlin-userdebug_asan_coverage boot.
Test: angler boots with CC and CMS.
Change-Id: I70f99779df6acc1b64cab6402f3ef7c73ce5b39b
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| 58246a13ded36d5256c6fcd3cc60bae5705a73bd |
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26-Sep-2016 |
Andreas Gampe <agampe@google.com> |
ART: Revert base/logging conditional hacks
This partially reverts commit bda1d606f2d31086874b68edd9254e3817d8049c.
ART was switched to libbase logging.
Bug: 31338270
Test: m test-art-host
Change-Id: I1a2f90d1ddb67d45ebe28d970b3ee7fd2d16a730
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| bda1d606f2d31086874b68edd9254e3817d8049c |
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30-Aug-2016 |
Andreas Gampe <agampe@google.com> |
ART: Detach libart-disassembler from libart
Some more intrusive changes than I would have liked, as long as
ART logging is different from libbase logging.
Fix up some includes.
Bug: 15436106
Bug: 31338270
Test: m test-art-host
Change-Id: I9fbe4b85b2d74e079a4981f3aec9af63b163a461
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| f04cf5470fd53d93f7ae5b07205284c19fa59f41 |
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31-Aug-2016 |
Vladimir Marko <vmarko@google.com> |
Remove workarounds for [D]CHECK()s in constexpr functions.
We're now using C++14, so we can use [D]CHECK()s directly
in constexpr functions. Remove the C++11 workaround macros
([D]CHECK_CONSTEXPR) and C++ version checks. Also remove the
'static' qualifier from inline functions in affected files.
Test: m test-art-host
Change-Id: I0f962ad75e4efe9b65325d022cd272b229574222
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| 09ed09866da6d8c7448ef297c148bfa577a247c2 |
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12-Feb-2016 |
David Srbecky <dsrbecky@google.com> |
Pack stack map entries on bit level to save space.
Use only the minimum number of bits required to store stack map data.
For example, if native_pc needs 5 bits and dex_pc needs 3 bits, they
will share the first byte of the stack map entry.
The header is changed to store bit offsets of the fields rather than
byte sizes. Offsets also make it easier to access later fields without
calculating sum of all previous sizes.
All of the header fields are byte sized or encoded as ULEB128 instead
of the previous fixed size encoding. This shrinks it by about half.
It saves 3.6 MB from non-debuggable boot.oat (AOSP).
It saves 3.1 MB from debuggable boot.oat (AOSP).
It saves 2.8 MB (of 99.4 MB) from /system/framework/arm/ (GOOG).
It saves 1.0 MB (of 27.8 MB) from /system/framework/oat/arm/ (GOOG).
Field loads from stackmaps seem to get around 10% faster.
(based on the time it takes to load all stackmap entries from boot.oat)
Bug: 27640410
Change-Id: I8bf0996b4eb24300c1b0dfc6e9d99fe85d04a1b7
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| 88b2b80aed15bb1f931cddd40e44ca525ef10018 |
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04-Dec-2015 |
Vladimir Marko <vmarko@google.com> |
Allow initializing runtime with parsed options.
Needed by upcoming refactoring of dex2oat to allow
early writing of dex files to the oat file.
Change-Id: Ia13c26132846801522f181f51f64035d625e8416
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| 0d5a281c671444bfa75d63caf1427a8c0e6e1177 |
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13-Nov-2015 |
Roland Levillain <rpl@google.com> |
x86/x86-64 read barrier support for concurrent GC in Optimizing.
This first implementation uses slow paths to instrument heap
reference loads and GC root loads for the concurrent copying
collector, respectively calling the artReadBarrierSlow and
artReadBarrierForRootSlow (new) runtime entry points.
Notes:
- This implementation does not instrument HInvokeVirtual
nor HInvokeInterface instructions (for class reference
loads), as the corresponding read barriers are not stricly
required with the current concurrent copying collector.
- Intrinsics which may eventually call (on slow path) are
disabled when read barriers are enabled, as the current
slow path infrastructure does not support this case.
- When read barriers are enabled, the code generated for a
HArraySet instruction always go into the array set slow
path for object arrays (delegating the operation to the
runtime), as we are lacking a mechanism to keep a
temporary register live accross a runtime call (needed for
the instrumentation of type checking code, which requires
two successive read barriers).
Bug: 12687968
Change-Id: I14cd6107233c326389120336f93955b28ffbb329
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| dbce0d738e9d7956d2bd73e932a0fdd28f2229b4 |
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17-Sep-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS64r6 Assembler Tests
Assembler tests for:
- SQRT.fmt - ABS.fmt - ROUND.L.fmt - ROUND.W.fmt
- CEIL.L.fmt - CEIL.W.fmt - FLOOR.L.fmt - FLOOR.W.fmt
- SEL.fmt - RINT.fmt - CLASS.fmt - MIN.fmt
- MAX.fmt - cvt.d.l - BITSWAP - DBITSWAP
- DSBH - DSHD - WSBH - ROTR
- SELEQZ - SELNEZ - CLZ - CLO
- DCLZ - DCLO - SC - SCD
- LL - LLD
These are the assembler instructions which were added to support
intrinsic functions on MIPS64. Tests for additional assembler
instructions will follow.
Support added to the testing infrastructure for:
- Assembler instructions which use three registers; previously
instructions were limited to one, or two, registers.
- Immediate values which have their sizes specified by the number of
bits required to store them rather than the number of bytes, in both
signed and unsigned versions.
Change-Id: I38c07dcbf2539825b25bed13aac05a26fa594b0b
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| 151ab8d096be02b04391fd32460a31ee60ae2b0a |
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15-Aug-2015 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: DCHECK zero case for CLZ/CTZ""
This reverts commit 4318d91ea4be673d4deba39d33ac4718d77986a7.
Fix up the lit=-1 case in the arm32 Quick backend; add test case.
Change-Id: I8d0861133db950090ee959f532ede1448683dfa9
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| cf36d493124d8048efa0bd6f67d817ce3cd6b725 |
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12-Aug-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Compress LengthPrefixedArray on 32-bit targets.
Previously, the LengthPrefixedArray<ArtMethod> on 32-bit
targets contained a 64-bit length field followed by the
ArtMethod elements with size only a multiple of 4, not 8.
Consequently, an odd-length array broke the alignment for
the following array which would have the 64-bit length
placed at an unaligned address.
To fix that, we make the length field 32-bit and explicitly
pass the alignment information to the LengthPrefixedArray.
This also makes the 32-bit boot image a bit smaller.
On Nexus 5, AOSP, ToT, the field section is 11528B smaller
and the method section is 21036B smaller. 64-bit targets
should see the same savings for the field section but no
difference for the methods section.
Change-Id: I3e03e7b94129025c8a1c117c27645a34dec516d2
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| 4318d91ea4be673d4deba39d33ac4718d77986a7 |
|
14-Aug-2015 |
Andreas Gampe <agampe@google.com> |
Revert "ART: DCHECK zero case for CLZ/CTZ"
This reverts commit 51db2c217052fd6881b81f3ac5162fe88c36dbf0.
Still breaks for arm32. :(
Change-Id: I5fe6fc0cc410cc1c5b6bd68028ce9bf835cb94d5
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| 51db2c217052fd6881b81f3ac5162fe88c36dbf0 |
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14-Aug-2015 |
Andreas Gampe <agampe@google.com> |
ART: DCHECK zero case for CLZ/CTZ
Add a DCHECK_CONSTEXPR. All current callers have an explicit
zero check before hand and so we should not trip this at the
moment. Remove the TODO.
Add the check for T being unsigned for CLZ (trivial fix for
leb128.h). We use CTZ with signed types.
Change-Id: I7bbf0b1699eed21715c6cc20dbfe22b7da403b1a
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| 7bf2b4f1d08050f80782217febac55c8cfc5e4ef |
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08-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Remove interpreter entrypoint in ArtMethod.""
The start of the interned strings in the image was not aligned
properly, now that ArtMethods just need to be word aligned.
This reverts commit 7070ccd8b6439477eafeea7ed3736645d78e003f.
bug:22242193
Change-Id: I580c23310c33c239fe0e5d15c72f23a936f58ed1
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| 7070ccd8b6439477eafeea7ed3736645d78e003f |
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08-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Remove interpreter entrypoint in ArtMethod."
Build failures on bots. Investigating.
This reverts commit fa2c054b28d4b540c1b3651401a7a091282a015f.
Change-Id: Id65b2009aa66cb291fb8c39758a58e0b0d22616c
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| fa2c054b28d4b540c1b3651401a7a091282a015f |
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01-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Remove interpreter entrypoint in ArtMethod.
Saves 4/8 bytes for each ArtMethod.
Change-Id: I110ecdddf8516b0759a31fa157609643e6d60b15
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| 41b175aba41c9365a1c53b8a1afbd17129c87c14 |
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19-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Clean up arm64 kNumberOfXRegisters usage.
Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
(cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0)
Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
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| 80afd02024d20e60b197d3adfbb43cc303cf29e0 |
|
19-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Clean up arm64 kNumberOfXRegisters usage.
Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
Change-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7
|