| ab8707e6875a9fe447ff04fad9053d7d719f89e6 |
|
08-Jan-2015 |
Soby Mathew <soby.mathew@arm.com> |
Remove coherent memory from the BL memory maps
This patch extends the build option `USE_COHERENT_MEMORY` to
conditionally remove coherent memory from the memory maps of
all boot loader stages. The patch also adds necessary
documentation for coherent memory removal in firmware-design,
porting and user guides.
Fixes ARM-Software/tf-issues#106
Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| d5f130930624ceb95cde40de999a880aa2b00493 |
|
12-Aug-2014 |
Juan Castillo <juan.castillo@arm.com> |
Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs
This patch adds support for SYSTEM_OFF and SYSTEM_RESET PSCI
operations. A platform should export handlers to complete the
requested operation. The FVP port exports fvp_system_off() and
fvp_system_reset() as an example.
If the SPD provides a power management hook for system off and
system reset, then the SPD is notified about the corresponding
operation so it can do some bookkeeping. The TSPD exports
tspd_system_off() and tspd_system_reset() for that purpose.
Versatile Express shutdown and reset methods have been removed
from the FDT as new PSCI sys_poweroff and sys_reset services
have been added. For those kernels that do not support yet these
PSCI services (i.e. GICv3 kernel), the original dtsi files have
been renamed to *-no_psci.dtsi.
Fixes ARM-software/tf-issues#218
Change-Id: Ic8a3bf801db979099ab7029162af041c4e8330c8
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| a1d80440c44ce70e5fec4d8c60b5f6688b6cf8ff |
|
19-Aug-2014 |
Dan Handley <dan.handley@arm.com> |
Merge pull request #189 from achingupta/ag/tf-issues#153
Unmask SError interrupt and clear SCR_EL3.EA bit
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| 5a06bb7e0b3ec6c98857423f52a1f98b54e46303 |
|
04-Aug-2014 |
Dan Handley <dan.handley@arm.com> |
Clarify platform porting interface to TSP
* Move TSP platform porting functions to new file:
include/bl32/tsp/platform_tsp.h.
* Create new TSP_IRQ_SEC_PHY_TIMER definition for use by the generic
TSP interrupt handling code, instead of depending on the FVP
specific definition IRQ_SEC_PHY_TIMER.
* Rename TSP platform porting functions from bl32_* to tsp_*, and
definitions from BL32_* to TSP_*.
* Update generic TSP code to use new platform porting function names
and definitions.
* Update FVP port accordingly and move all TSP source files to:
plat/fvp/tsp/.
* Update porting guide with above changes.
Note: THIS CHANGE REQUIRES ALL PLATFORM PORTS OF THE TSP TO
BE UPDATED
Fixes ARM-software/tf-issues#167
Change-Id: Ic0ff8caf72aebb378d378193d2f017599fc6b78f
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 0c8d4fef28768233f1f46b4d085f904293dffd2c |
|
05-Aug-2014 |
Achin Gupta <achin.gupta@arm.com> |
Unmask SError interrupt and clear SCR_EL3.EA bit
This patch disables routing of external aborts from lower exception levels to
EL3 and ensures that a SError interrupt generated as a result of execution in
EL3 is taken locally instead of a lower exception level.
The SError interrupt is enabled in the TSP code only when the operation has not
been directly initiated by the normal world. This is to prevent the possibility
of an asynchronous external abort which originated in normal world from being
taken when execution is in S-EL1.
Fixes ARM-software/tf-issues#153
Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| da0af78aa230d3a873923e05643071f761f593e2 |
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01-Aug-2014 |
Dan Handley <dan.handley@arm.com> |
Move TSP private declarations into separate header
Move the TSP private declarations out of tsp.h and into a new
header, tsp_private.h. This clarifies the TSP interface to the TSPD.
Change-Id: I39af346eeba3350cadcac56c02d97a5cb978c28b
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 53fdcebd6d330183ce3e46f38bb50e838a6a60de |
|
16-Jul-2014 |
Juan Castillo <juan.castillo@arm.com> |
Call platform_is_primary_cpu() only from reset handler
The purpose of platform_is_primary_cpu() is to determine after reset
(BL1 or BL3-1 with reset handler) if the current CPU must follow the
cold boot path (primary CPU), or wait in a safe state (secondary CPU)
until the primary CPU has finished the system initialization.
This patch removes redundant calls to platform_is_primary_cpu() in
subsequent bootloader entrypoints since the reset handler already
guarantees that code is executed exclusively on the primary CPU.
Additionally, this patch removes the weak definition of
platform_is_primary_cpu(), so the implementation of this function
becomes mandatory. Removing the weak symbol avoids other
bootloaders accidentally picking up an invalid definition in case the
porting layer makes the real function available only to BL1.
The define PRIMARY_CPU is no longer mandatory in the platform porting
because platform_is_primary_cpu() hides the implementation details
(for instance, there may be platforms that report the primary CPU in
a system register). The primary CPU definition in FVP has been moved
to fvp_def.h.
The porting guide has been updated accordingly.
Fixes ARM-software/tf-issues#219
Change-Id: If675a1de8e8d25122b7fef147cb238d939f90b5e
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| ec3c10039bdc2c1468a8ba95fbbe9de78628eea5 |
|
18-Jul-2014 |
Achin Gupta <achin.gupta@arm.com> |
Simplify management of SCTLR_EL3 and SCTLR_EL1
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of
SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset
in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in
S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They
do not have to be saved and restored either. The M, WXN and optionally the C
bit are set in the enable_mmu_elX() function. This is done during both the warm
and cold boot paths.
Fixes ARM-software/tf-issues#226
Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| b51da821821cfda0d44f09a6f92fdc5933f9b23b |
|
26-Jun-2014 |
Achin Gupta <achin.gupta@arm.com> |
Remove coherent stack usage from the warm boot path
This patch uses stacks allocated in normal memory to enable the MMU early in the
warm boot path thus removing the dependency on stacks allocated in coherent
memory. Necessary cache and stack maintenance is performed when a cpu is being
powered down and up. This avoids any coherency issues that can arise from
reading speculatively fetched stale stack memory from another CPUs cache. These
changes affect the warm boot path in both BL3-1 and BL3-2.
The EL3 system registers responsible for preserving the MMU state are not saved
and restored any longer. Static values are used to program these system
registers when a cpu is powered on or resumed from suspend.
Change-Id: I8357e2eb5eb6c5f448492c5094b82b8927603784
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 754a2b7a092d3cf81767f1b5a6ab61531792e45f |
|
25-Jun-2014 |
Achin Gupta <achin.gupta@arm.com> |
Remove coherent stack usage from the cold boot path
This patch reworks the cold boot path across the BL1, BL2, BL3-1 and BL3-2 boot
loader stages to not use stacks allocated in coherent memory for early platform
setup and enabling the MMU. Stacks allocated in normal memory are used instead.
Attributes for stack memory change from nGnRnE when the MMU is disabled to
Normal WBWA Inner-shareable when the MMU and data cache are enabled. It is
possible for the CPU to read stale stack memory after the MMU is enabled from
another CPUs cache. Hence, it is unsafe to turn on the MMU and data cache while
using normal stacks when multiple CPUs are a part of the same coherency
domain. It is safe to do so in the cold boot path as only the primary cpu
executes it. The secondary cpus are in a quiescent state.
This patch does not remove the allocation of coherent stack memory. That is done
in a subsequent patch.
Change-Id: I12c80b7c7ab23506d425c5b3a8a7de693498f830
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| dff8e47a4b6797e862a20559d34a9e2a056ab6e1 |
|
16-May-2014 |
Dan Handley <dan.handley@arm.com> |
Add enable mmu platform porting interfaces
Previously, the enable_mmu_elX() functions were implicitly part of
the platform porting layer since they were included by generic
code. These functions have been placed behind 2 new platform
functions, bl31_plat_enable_mmu() and bl32_plat_enable_mmu().
These are weakly defined so that they can be optionally overridden
by platform ports.
Also, the enable_mmu_elX() functions have been moved to
lib/aarch64/xlat_tables.c for optional re-use by platform ports.
These functions are tightly coupled with the translation table
initialization code.
Fixes ARM-software/tf-issues#152
Change-Id: I0a2251ce76acfa3c27541f832a9efaa49135cc1c
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 399fb08fff2e4a0cad4cd1cf0ece84db6670447f |
|
20-May-2014 |
Andrew Thoelke <andrew.thoelke@arm.com> |
Use a vector table for TSP entrypoints
The TSP has a number of entrypoints used by the TSP on different
occasions. These were provided to the TSPD as a table of function
pointers, and required the TSPD to read the entry in the table,
which is in TSP memory, in order to program the exception return
address.
Ideally, the TSPD has no access to the TSP memory.
This patch changes the table of function pointers into a vector
table of single instruction entrypoints. This allows the TSPD to
calculate the entrypoint address instead of read it.
Fixes ARM-software/tf-issues#160
Change-Id: Iec6e055d537ade78a45799fbc6f43765a4725ad3
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 239b04fa31647100c537852b4a3fc8bd47e33aa6 |
|
09-May-2014 |
Soby Mathew <soby.mathew@arm.com> |
Non-Secure Interrupt support during Standard SMC processing in TSP
Implements support for Non Secure Interrupts preempting the
Standard SMC call in EL1. Whenever an IRQ is trapped in the
Secure world we securely handover to the Normal world
to process the interrupt. The normal world then issues
"resume" smc call to resume the previous interrupted SMC call.
Fixes ARM-software/tf-issues#105
Change-Id: I72b760617dee27438754cdfc9fe9bcf4cc024858
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 57356e9094ac5ecbca29131a3c53c6978457350f |
|
09-May-2014 |
Achin Gupta <achin.gupta@arm.com> |
Add support for asynchronous FIQ handling in TSP
This patch adds support in the TSP to handle FIQ interrupts that are
generated when execution is in the TSP. S-EL1 interrupt are handled
normally and execution resumes at the instruction where the exception
was originally taken. S-EL3 interrupts i.e. any interrupt not
recognized by the TSP are handed to the TSPD. Execution resumes
normally once such an interrupt has been handled at EL3.
Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 6cf89021312a33395f804d80377a6ffdaadbbe21 |
|
09-May-2014 |
Achin Gupta <achin.gupta@arm.com> |
Add support for synchronous FIQ handling in TSP
This patch adds support in the TSP for handling S-EL1 interrupts
handed over by the TSPD. It includes GIC support in its platform port,
updates various statistics related to FIQ handling, exports an entry
point that the TSPD can use to hand over interrupts and defines the
handover protocol w.r.t what context is the TSP expected to preserve
and the state in which the entry point is invoked by the TSPD.
Change-Id: I93b22e5a8133400e4da366f5fc862f871038df39
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 6871c5d3a227cb95008a25e90e358ec0ac615222 |
|
16-May-2014 |
Vikram Kanigiri <vikram.kanigiri@arm.com> |
Rework memory information passing to BL3-x images
The issues addressed in this patch are:
1. Remove meminfo_t from the common interfaces in BL3-x,
expecting that platform code will find a suitable mechanism
to determine the memory extents in these images and provide
it to the BL3-x images.
2. Remove meminfo_t and bl31_plat_params_t from all FVP BL3-x
code as the images use link-time information to determine
memory extents.
meminfo_t is still used by common interface in BL1/BL2 for
loading images
Change-Id: I4e825ebf6f515b59d84dc2bdddf6edbf15e2d60f
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| b793e43166348772af74331df7be46d7a696a7aa |
|
09-May-2014 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
fvp: Provide per-EL MMU setup functions
Instead of having a single version of the MMU setup functions for all
bootloader images that can execute either in EL3 or in EL1, provide
separate functions for EL1 and EL3. Each bootloader image can then
call the appropriate version of these functions. The aim is to reduce
the amount of code compiled in each BL image by embedding only what's
needed (e.g. BL1 to embed only EL3 variants).
Change-Id: Ib86831d5450cf778ae78c9c1f7553fe91274c2fa
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 97043ac98e13a726dbf8b3b41654dca759e3da2c |
|
09-Apr-2014 |
Dan Handley <dan.handley@arm.com> |
Reduce deep nesting of header files
Reduce the number of header files included from other header
files as much as possible without splitting the files. Use forward
declarations where possible. This allows removal of some unnecessary
"#ifndef __ASSEMBLY__" statements.
Also, review the .c and .S files for which header files really need
including and reorder the #include statements alphabetically.
Fixes ARM-software/tf-issues#31
Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 0a30cf54af7bb1f77b405062b1d5b44e809d0290 |
|
18-Mar-2014 |
Andrew Thoelke <andrew.thoelke@arm.com> |
Place assembler functions in separate sections
This extends the --gc-sections behaviour to the many assembler
support functions in the firmware images by placing each function
into its own code section. This is achieved by creating a 'func'
macro used to declare each function label.
Fixes ARM-software/tf-issues#80
Change-Id: I301937b630add292d2dec6d2561a7fcfa6fec690
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|
| 7c88f3f633288856dd691dfda222e60092e4dab9 |
|
18-Feb-2014 |
Achin Gupta <achin.gupta@arm.com> |
Add Test Secure Payload (BL3-2) image
This patch adds a simple TSP as the BL3-2 image. The secure payload
executes in S-EL1. It paves the way for the addition of the TSP
dispatcher runtime service to BL3-1. The TSP and the dispatcher service
will serve as an example of the runtime firmware's ability to toggle
execution between the non-secure and secure states in response to SMC
request from the non-secure state. The TSP will be replaced by a
Trusted OS in a real system.
The TSP also exports a set of handlers which should be called in
response to a PSCI power management event e.g a cpu being suspended or
turned off. For now it runs out of Secure DRAM on the ARM FVP port and
will be moved to Secure SRAM later. The default translation table setup
code assumes that the caller is executing out of secure SRAM. Hence the
TSP exports its own translation table setup function.
The TSP only services Fast SMCs, is non-reentrant and non-interruptible.
It does arithmetic operations on two sets of four operands, one set
supplied by the non-secure client, and the other supplied by the TSP
dispatcher in EL3. It returns the result according to the Secure Monitor
Calling convention standard.
This TSP has two functional entry points:
- An initial, one-time entry point through which the TSP is initialized
and prepares for receiving further requests from secure
monitor/dispatcher
- A fast SMC service entry point through which the TSP dispatcher
requests secure services on behalf of the non-secure client
Change-Id: I24377df53399307e2560a025eb2c82ce98ab3931
Co-authored-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
|