f3ef5332fa3f4d5ec72c178a2b19dac363a19383 |
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04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229 http://b/26987366 Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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ebe69fe11e48d322045d5949c83283927a0d790b |
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23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699. Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494. Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712). Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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4f3b5e8c9232e43d1291aab8db5f5698d7ee0ea4 |
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10-Oct-2013 |
Matthias Braun <matze@braunis.de> |
Represent RegUnit liveness with LiveRange instance Previously LiveInterval has been used, but having a spill weight and register number is unnecessary for a register unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
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03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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1ead68d769f27f6d68d4aaeffe4199fa2cacbc95 |
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28-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make the LiveRegMatrix analysis available to targets. No functional change, just moved header files. Targets can inject custom passes between register allocation and rewriting. This makes it possible to tweak the register allocation before rewriting, using the full global interference checking available from LiveRegMatrix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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45c5c57179e8b4938042431f8e12c9bfad67b3c8 |
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06-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Allow overlaps between virtreg and physreg live ranges. The RegisterCoalescer understands overlapping live ranges where one register is defined as a copy of the other. With this change, register allocators using LiveRegMatrix can do the same, at least for copies between physical and virtual registers. When a physreg is defined by a copy from a virtreg, allow those live ranges to overlap: %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11 %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill> We can assign %vreg11 to %ECX, overlapping the live range of %CL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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eb06b0b6aa627c6698471d4df71570f080fb3c5c |
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16-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Accept null PhysReg arguments to checkRegMaskInterference. Calling checkRegMaskInterference(VirtReg) checks if VirtReg crosses any regmask operands, regardless of the registers they clobber. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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8879480ed708ffa51d23f423ec316763c7cb9577 |
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09-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Sketch a LiveRegMatrix analysis pass. The LiveRegMatrix represents the live range of assigned virtual registers in a Live interval union per register unit. This is not fundamentally different from the interference tracking in RegAllocBase that both RABasic and RAGreedy use. The important differences are: - LiveRegMatrix tracks interference per register unit instead of per physical register. This makes interference checks cheaper and assignments slightly more expensive. For example, the ARM D7 reigster has 24 aliases, so we would check 24 physregs before assigning to one. With unit-based interference, we check 2 units before assigning to 2 units. - LiveRegMatrix caches regmask interference checks. That is currently duplicated functionality in RABasic and RAGreedy. - LiveRegMatrix is a pass which makes it possible to insert target-dependent passes between register allocation and rewriting. Such passes could tweak the register assignments with interference checking support from LiveRegMatrix. Eventually, RABasic and RAGreedy will be switched to LiveRegMatrix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/LiveRegMatrix.cpp
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