History log of /external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
de2d8694e25a814696358e95141f4b1aa4d8847e 20-Sep-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r275480

Bug: http://b/31320715

This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from
aosp/dev.

Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)

Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
f3ef5332fa3f4d5ec72c178a2b19dac363a19383 04-Mar-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r256229

http://b/26987366

Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
6948897e478cbd66626159776a8017b3c18579b9 01-Jul-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r239765

Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.

Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
0c7f116bb6950ef819323d855415b2f2b0aad987 06-May-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r235153

Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
4c5e43da7792f75567b693105cc53e3f1992ad98 08-Apr-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master llvm for rebase to r233350

Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
37ed9c199ca639565f6ce88105f9e39e898d82d0 01-Dec-2014 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r222494.

Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
c6a4f5e819217e1e12c458aed8e7b122e23a3a58 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
23427207ea575f57b571cf5aad1effb1f97e7ee1 18-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code for (ConstantFP 0.0)

Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64
which resulted in an impossible constraint on the register allocation. It now
uses BuildPairF64_64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
2ef99c5dff1ab9612f2d65e38f725d809672d2fd 15-Oct-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Define a pseudo instruction which writes to both the lower and higher
parts of the accumulators and gets expanded post-RA.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
243702b95a471ffb7d2374dfad3d7f8b11bee7e7 07-Oct-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo.

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
e1b1a684dd1459a40b9ee1f46eb865ba9e2133c1 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for MSA registers to copyPhysReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0 07-Sep-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
a6c3a4ee76ef8464d3c83472e15af521ade7eeb4 28-Aug-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added cfcmsa, and ctcmsa

The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
62f61bf9077418801be5e2039333727079819844 27-Aug-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added spill/reload support


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
b1f4f120a50c392c85c6b4388d63e36251fce279 21-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Add support for mfhc1 and mthc1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
3531db14c61957e7ad00ce972e9685864c3887da 21-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
a98a486ad194c38293efcc5359d6ed2493f950dc 20-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
cbaf6d0cc3d3f363f269346817a90d3cbc8d1084 14-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename HIRegs and LORegs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
491d04969d9f29ed891c73238648853954ba4f81 08-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename accumulator register classes and FP register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
1858786285139b87961d9ca08de91dcd59364afb 07-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename register classes CPURegs and CPU64Regs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
0b926427670de6e0ed855ef93f220a3f51ed1eab 22-Jul-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
da218210f7371cd47a43252756e03b6a03a6b06d 19-Jul-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.

No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
4cef3d818183aafc1b3adfad4140483d9ad1ad86 11-Jun-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Use function TargetInstrInfo::getRegClass.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
7462a875d9ca4cf7ab30829152175f7448757943 08-Jun-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Use a helper function which compares the size of the source and
destination operands of an instruction.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
41e632d9e1a55d36cb08b0551ad82a13d9137a5e 07-Jun-2013 Bill Wendling <isanbard@gmail.com> Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
ec4db6ab5f64318b1aa2351f7e710569869193e9 16-May-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
invalid instruction sequence.

Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.

mtc1 $f4, $4 # int-to-fp move instruction.
mov.s $f2, $f4 # move contents of $f4 to $f2.
cvt.s.w $f0, $f2 # int-to-fp conversion.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
42f562a1694d24b41f36bbb4d4a086a2a470c625 13-May-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Add option -mno-ldc1-sdc1.

This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
6daba286836e6fb2351e7ebc248e18a5c80e8a31 13-May-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename functions. No functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
99ad6ac65e8c97a0d3c9d884285dda01f793b7d1 03-May-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Handle reading, writing or copying of ccond field of DSP control
register.

- Define pseudo instructions which store or load ccond field of the DSP
control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
c147c1b994e1187cb471cdb7ee05f5f875eff4e0 01-May-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix handling of instructions which copy to/from accumulator registers.

Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
67fdafe1cd2c25aa1d245b4becf93324c08ec93e 03-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Small update to the implementation of eh.return for Mips.

This patch initializes t9 to the handler address, but only if the relocation
model is pic. This handles the case where handler to which eh.return jumps
points to the start of the function.

Patch by Sasa Stankovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
8f4d3800a7e6f546279bc7b7f418693fc7484d54 30-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStack
to handle accumulator registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
c713e996d305df99cc7fc58c9d8dc1f5fa00518d 29-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
544cc21cf4807116251a699d8b1d3d4bace21597 30-Jan-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Lower EH_RETURN.

Patch by Sasa Stankovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
68fe665b9a878b4a19e005ad9a8c92c402ecd320 20-Dec-2012 Akira Hatanaka <ahatanaka@mips.com> [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy
physical register $r1 to $r0.

GNU disassembler recognizes an "or" instruction as a "move", and this change
makes the disassembled code easier to read.

Original patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
d04a8d4b33ff316ca4cf961e06c9e312eff8e64f 03-Dec-2012 Chandler Carruth <chandlerc@gmail.com> Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
11a45c214c26bdc49ef58c0eb214df5200867cee 03-Nov-2012 Akira Hatanaka <ahatanaka@mips.com> [mips] Stop reserving register AT and use register scavenger when a scratch
register is needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
173192fa71a45ee87479c0eb7753bf116bce36b8 02-Nov-2012 Akira Hatanaka <ahatanaka@mips.com> [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directive
"set .noat" so that the assembler doesn't issue warnings when register $AT is
used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
fc4eafa0f490bd06d8191a2f007514b9e3ce0387 23-Aug-2012 Akira Hatanaka <ahatanaka@mips.com> Make function loadImmediate a member of MipsSEInstrInfo and change it to return
the temporary register that was used to load the immediate. Currently, it always
returns register $at, but this will change if, in the future, we decide to use
another register.

No changes in functionality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
af2662606745bdebaa2cb43096274ce3d33b665f 02-Aug-2012 Akira Hatanaka <ahatanaka@mips.com> Move the code that creates instances of MipsInstrInfo and MipsFrameLowering out
of MipsTargetMachine.cpp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
71746220d3d1c3e8efba35038ac2ff14b4a4d3ae 01-Aug-2012 Akira Hatanaka <ahatanaka@mips.com> Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emits
instructions that decrement and increment the stack pointer before and after a
call when the function does not have a reserved call frame.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
8589010e3d1d5a902992a5039cffa9d4116982c5 01-Aug-2012 Akira Hatanaka <ahatanaka@mips.com> Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and
MipsSERegisterInfo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
0bc1adbbc4fdc6d85a671ed70a1bbd345dba445d 31-Jul-2012 Akira Hatanaka <ahatanaka@mips.com> Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),
and MipsSEInstrInfo (for mips32/64).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp