History log of /external/llvm/test/MC/PowerPC/ppc64-encoding.s
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de2d8694e25a814696358e95141f4b1aa4d8847e 20-Sep-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r275480

Bug: http://b/31320715

This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from
aosp/dev.

Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)

Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
f3ef5332fa3f4d5ec72c178a2b19dac363a19383 04-Mar-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r256229

http://b/26987366

Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
6948897e478cbd66626159776a8017b3c18579b9 01-Jul-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r239765

Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.

Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
0c7f116bb6950ef819323d855415b2f2b0aad987 06-May-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r235153

Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
37ed9c199ca639565f6ce88105f9e39e898d82d0 01-Dec-2014 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r222494.

Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
9e5bbeab1f6f79375c24bfab87c28f5f4c5afea1 08-Jul-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Support basic compare mnemonics

This adds support for the basic mnemoics (with the L operand) for the
fixed-point compare instructions. These are defined as aliases for the
already existing CMPW/CMPD patterns, depending on the value of L.

This requires use of InstAlias patterns with immediate literal operands.
To make this work, we need two further changes:

- define a RegisterPrefix, because otherwise literals 0 and 1 would
be parsed as literal register names

- provide a PPCAsmParser::validateTargetOperandClass routine to
recognize immediate literals (like ARM does)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
3c99602ca87f604080e367838180c3d63f6931f3 04-Jul-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Add all trap mnemonics

This adds support for all basic and extended variants
of the trap instructions to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
51f558c9aed3bf74c2e8f3ff3bf365c94637ecdf 03-Jul-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Support lmw/stmw in the asm parser

This adds support for the load/store multiple instructions,
currently used by the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
33efedc0481c4b0d9866ff526eb1161372b5919f 03-Jul-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Use mtocrf when available

Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.

Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.

To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.

As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
44175d9715268bfb7c2cb10ebf14474f4a411464 03-Jul-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Support mtspr/mfspr in the asm parser

This adds support for the generic forms of mtspr/mfspr
for the asm parser. The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
1307d8300f6fe97059998480c42b44faefbc9b99 01-Jul-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Support all condition register logical instructions

This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
816c06f7fa73e8150e260a11d897be2f52d4f2b8 25-Jun-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Add rldcr/rldic instructions

This adds pattern for the rldcr and rldic instructions (the last instruction
from the rotate/shift family that were missing). They are currently used
only by the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
e5a30f0ca22cc1ba97478e9fadcdef02d341004e 24-Jun-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Support generic conditional branches in asm parser

This adds instruction patterns to cover the generic forms of
the conditional branch instructions. This allows the assembler
to support the generic mnemonics.

The compiler will still generate the various specific forms
of the instruction that were already supported.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
9679c47a07386cbf3547a0927609c7ee080b2aab 24-Jun-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Support absolute branches

There is currently only limited support for the "absolute" variants
of branch instructions. This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
278916500a2d7c735e3ed6b0f57cd757815b9867 10-Jun-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Support extended sc mnemonic

A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler. This patch adds a corresponding alias.

Problem reported by Joerg Sonnenberger.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
5bbdb190412a55436b808cfa59820b1e6cf08db0 14-May-2013 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Implement the PowerPC system call (sc) instruction.

Instruction added at request of Roman Divacky. Tested via asm-parser.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s
5e220753ff81ac5cbee874e7c00c76c7fbe0d20a 03-May-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> [PowerPC] Add assembler parser

This adds assembler parser support to the PowerPC back end.

The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux. The supported syntax is
intended to be compatible with the GNU assembler.

The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.

Instruction operands will be checked for validity and errors
generated. (Error handling in general could still be improved.)

The patch adds a number of test cases to verify instruction
and operand encodings. The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector.
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.

A number of follow-on check-ins will add extra features. When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/PowerPC/ppc64-encoding.s