| d02343e5016a5795451af3e0315b658b39463a30 |
|
04-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use Haswell's sample_d_c for textureGrad with shadow samplers.
The new hardware actually just supports this now.
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 899017fc54c40c969b5239b33f3a17b311878b0d)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| e592f7df0361eb8b5c75944f0151c4e6b3f839dd |
|
02-Aug-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/msaa: Add sample-alpha-to-coverage support for multiple render targets
Render Target Write message should include source zero alpha value when
sample-alpha-to-coverage is enabled for an FBO with multiple render targets.
Source zero alpha value is used as fragment coverage for all the render
targets.
This patch makes piglit tests draw-buffers-alpha-to-coverage and
alpha-to-coverage-no-draw-buffer-zero to pass on Sandybridge. No
regressions are observed with piglit all.tests.
V2: Revert all the changes made in emit_color_write() function to
include src0 alpha for targets > 0. Now handling this case in a if
block.
V3: Correctly calculate the instruction length for buffer zero.
Properly handle the case of dual_src_blend when alpha-to-coverage
is enabled.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 9b4053cabd8bda180b352d2d2047209f6ca5f6e8 |
|
06-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop the confusing saturate argument to math instruction setup.
This was ridiculous. We were ignoring the inst->header.saturate flag in the
case of math and only math. On gen4, we would leave inst->header.saturate in
place if it happened to be set, which would end up being applied to the
implicit mov and thus trash the first argument. On gen6, we would overwrite
inst->header.saturate with the saturate flag from the argument, which was not
set appropriately in brw_vec4_emit.cpp, and was only not a bug due to our
incompetence at coalescing saturate moves.
By ripping the argument out and making saturate work just like all the other
brw_eu_emit.c code generation, we can avoid both these classes of bugs.
Fixes piglit fog-modes, and the new specific fs-saturate-exp2 case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 454dc83f66643e66ea7ee9117368211f0cfe84d7 |
|
21-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Communicate the pull constant block read parameters through fs_regs.
I wanted to add the surface index as a variable value for UBO support,
and a reg seemed like the obvious way to go. This exposes more of the
information to CSE, which we'll probably want to apply to pull
constant loads for UBOs eventually (you might access 4 floats in a
row, each of which would produce an oword block read of the same
block).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 82bfb4b41af7d61aa45e41d62c1842b6a09e9585 |
|
05-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Move message header and texture offset setup to generate_tex().
Setting the texture offset bits in the message header involves very
specific hardware register descriptions. As such, I feel it's better
suited for the lower level "generate" layer that has direct access to
the weird register layouts, rather than at the fs_inst abstraction layer.
This also parallels the approach I took in the VS backend.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| d08fdacd58dfa6b1926e9df4707dd9e8dd5370c5 |
|
20-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Avoid unnecessary recompiles for shaders that don't use dFdy().
The i965 back-end needs to compile dFdy() differently for FBOs and
window system framebuffers, because Y coordinates are flipped between
the two (see commit 82d2596: i965: Compute dFdy() correctly for FBOs).
This patch avoids unnecessarily recompiling shaders that don't use
dFdy(), by only setting render_to_fbo in the wm program key if the
shader actually uses dFdy().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 3f929efa2872aa5a4402520ec9fd551392e2413a |
|
18-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend.
In order to compute centroid varyings correctly, the fragment shader
needs to be able to load the current pixel/sample mask into a flag
register. This patch adds an opcode to the fragment shader back-end
to do this; the opcode gets translated into the instruction
mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all }
Since this instruction clobbers f0, instruction scheduling has to
treat it the same as instructions that have a conditional modifier.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 82d25963a838cfebdeb9b080169979329ee850ea |
|
20-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Compute dFdy() correctly for FBOs.
On i965, dFdx() and dFdy() are computed by taking advantage of the
fact that each consecutive set of 4 pixels dispatched to the fragment
shader always constitutes a contiguous 2x2 block of pixels in a fixed
arrangement known as a "sub-span". So we calculate dFdx() by taking
the difference between the values computed for the left and right
halves of the sub-span, and we calculate dFdy() by taking the
difference between the values computed for the top and bottom halves
of the sub-span.
However, there's a subtlety when FBOs are in use: since FBOs use a
coordinate system where the origin is at the upper left, and window
system framebuffers use a coordinate system where the origin is at the
lower left, the computation of dFdy() needs to be negated for FBOs.
This patch modifies the fragment shader back-ends to negate the value
of dFdy() when an FBO is in use. It also modifies the code that
populates the program key (brw_wm_populate_key() and
brw_fs_precompile()) so that they always record in the program key
whether we are rendering to an FBO or to a window system framebuffer;
this ensures that the fragment shader will get recompiled when
switching between FBO and non-FBO use.
This will result in unnecessary recompiles of fragment shaders that
don't use dFdy(). To fix that, we will need to adapt the GLSL and
NV_fragment_program front-ends to record whether or not a given shader
uses dFdy(). I plan to implement this in a future patch series; I've
left FIXME comments in the code as a reminder.
Fixes Piglit test "fbo-deriv".
NOTE: This is a candidate for stable release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 29362875f2613ad87abe7725ce3c56c36d16cf9b |
|
25-Apr-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for GL_ARB_blend_func_extended.
v2: Add support for gen6, and don't turn it on if blending is
disabled. (fixes GPU hang), and note it in docs/GL3.txt
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 9e9ae280e215988287b0f875c81bc2e146b9f5dd |
|
04-May-2012 |
Eric Anholt <eric@anholt.net> |
Revert "i965/fs: Jump from discard statements to the end of the program when done."
This reverts commit 31866308fcf989df992ace28b5b986c3d3770e90.
Fixes piglit glsl-fs-discard-exit-3 and unigine tropics rendering.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 080b125c64b48447a515b1a169f779e62b3de13d |
|
10-Apr-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add basic block generator.
This takes the fs_inst list generated by the visitor, and generates a
list of basic blocks with edges between them. This is a building
block for data-flow analysis.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 31866308fcf989df992ace28b5b986c3d3770e90 |
|
19-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Jump from discard statements to the end of the program when done.
From the GLSL 1.30 spec:
The discard keyword is only allowed within fragment shaders. It
can be used within a fragment shader to abandon the operation on
the current fragment. This keyword causes the fragment to be
discarded and no updates to any buffers will occur. Control flow
exits the shader, and subsequent implicit or explicit derivatives
are undefined when this control flow is non-uniform (meaning
different fragments within the primitive take different control
paths).
v2: Don't emit the final HALT if no other HALTs were emitted.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 7d55f37b0e87db9b3806088797075161a1c9a8bb |
|
07-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for generating MADs.
Improves nexuiz performance 0.65% +/- .10% (n=5) on my gen6, and .39%
+/- .11% (n=10) on gen7. No statistically significant performance
difference on warsow (n=5, but only one shader has MADs).
v2: Add support for MADs in 16-wide by using compression control.
v3: Don't generate MADs when it will force an immediate to be moved to a temp.
(it's not clear whether this is a win or not, but it should result in less
questionable change to codegen compared to v2).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| f1d89638c02afafbf82ef657cd6ba9965dad6738 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop.
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| ce6be334bbf7f44c71ad5d190f9fb075d2f9a38c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching.
The EU code itself can just do this work, since all the consumers were
duplicating it.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 32118cfe37495738ed5931c6b1a71b8ee2ad189c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 9f8814752f306cb9a26d283f0b7cf876639e10f7 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop unused do_insn argument from gen6_CONT().
The branch distances get patched up later at the WHILE instruction.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| febad1779ae5cb5c85d66c2635baea62da52d2fa |
|
26-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB.
We'll be reusing most of these for the VS shortly. The one exception is
TXB (texturing with LOD bias), which is explicitly forbidden in the VS.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| a3b8c5ed5bd591d4ae7d215f71f039d3b19200bb |
|
23-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Make register file enum 0 be the undefined register file.
In 6d874d0ee18b3694c49e0206fa519bd8b746ec24, I checked whether a
register that had been stored was BAD_FILE (as opposed to a legitimate
GRF), but actually the unset register was ARF NULL because it had been
memset to 0. Finding BAD_FILE for unset values in debugging was my
intention with that file, so make it the case more often by
rearranging the enum. There was only one place we relied on the magic
enum register_file to hardware register file correspondance anyway.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 7e84a64dd02794a59586ba58ef0864118534d3c6 |
|
10-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Fix sampling from integer textures.
On original gen4, the surface format didn't determine the return data
type from sampling like it does on g45 and later.
Fixes GL_EXT_texture_integer/texture_integer_glsl130
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| dceb202297b39220fbbcb41267077fb3ff8d137a |
|
07-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix Sandybridge regression introduced by workaround-free math.
Commit a73c65c5342bf41fa0dfefe7daa9197ce6a11db4 had a typo which
accidentally enabled the workaround-free Gen7 code on Gen6.
Fixes GPU hangs in anything using pow() or integer division/modulus.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| a73c65c5342bf41fa0dfefe7daa9197ce6a11db4 |
|
18-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable faster workaround-free math on Ivybridge.
According to the documentation, Ivybridge's math instruction works in
SIMD16 mode for the fragment shader, and no longer forbids align16 mode
for the vertex shader.
The documentation claims that SIMD16 mode isn't supported for INT DIV,
but empirical evidence shows that it works fine. Presumably the note
is trying to warn us that the variant that returns both quotient and
remainder in (dst, dst + 1) doesn't work in SIMD16 mode since dst + 1
would be sechalf(dst), trashing half your results. Since we don't use
that variant, we don't care and can just enable SIMD16 everywhere.
The documentation also still claims that source modifiers and
conditional modifiers aren't supported, but empirical evidence and
study of the simulator both show that they work just fine.
Goodbye workarounds. Math just works now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 73b0a28ba8b3e2ab917d4c729f34ddbde52c9e88 |
|
04-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix comparisions with uint negation.
The condmod instruction ends up generating garbage condition codes,
because apparently the comparison happens on the accumulator value (33
bits for UD), not the truncated value that would be written.
Fixes fs-op-neg-*
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 43ccd3200c394dd4d89ed96f039ca7d6cfff972f |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove EOT parameter from brw_SAMPLE and brw_set_sampler_message.
The existing code asserted that eot == 0, as it doesn't make sense for
a thread to sample a texture as the last thing it does.
It doesn't make much sense to pass around a dead parameter either.
Especially for a function which already has a long parameter list.
So, remove the parameter and just set EOT to 0.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| ff8f272b0d02b41a0ce34ab6af7119b9e06f4961 |
|
29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement integer quotient and remainder math operations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 74e927bcafad0a994be5f88fbda4058bef08bc51 |
|
18-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants.
This mirrors the structure Eric used in the new VS backend, and seems
simpler. In particular, the math1/math2 split will avoid having to
figure out how many operands there are, as this is already known by the
caller.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 47b556fbcaea4660b21481e40d89167d883d47f5 |
|
07-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement texelFetch() on Gen4.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 30be2cc6c7c3378ee17885b5bf41d7ae53bf6fe0 |
|
26-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement texelFetch() on Ironlake and Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 4eeb4c150598605d1be3ce6674fa63076a720ae9 |
|
17-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement textureSize (TXS) on Gen4.
Also, remove the BRW_SAMPLER_MESSAGE_SIMD8_RESINFO #define because
there totally isn't a SIMD8 variant.
Unfortunately, resinfo returns FLOAT32 on Broadwater/Crestline, unlike
G45 which returns a proper UINT32. This turns out to be simple,
however: when we emit MOVs to select the desired half of the SIMD16
result, we can simply override the register type to be float so it's
converted to an integer.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| ecf8963754489abfb5097c130a9bcd4cdb76b6bd |
|
19-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement textureSize (TXS) on Gen5+.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 3f78f719732b87e6707f94c187ad6e263c6c2ef0 |
|
16-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix 32-bit integer multiplication.
The MUL opcode does a 16bit * 32bit multiply, and we need to do the
MACH to get the top 16bit * 32bit added in.
Fixes fs-op-mult-int-*, fs-op-mult-ivec*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| af3c9803d818fd33139f1247a387d64b967b8992 |
|
02-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Start adding the VS visitor and codegen.
The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's
currently controlled by the INTEL_NEW_VS=1 environment variable, and
only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 65b5cbbcf783f6c668ab5b31a0734680dd396794 |
|
05-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*.
I want to just use the same enums in the VS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| 6034b9a5124475d300d0678bd2fb6160865fa972 |
|
03-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Create a shared enum for hardware and compiler-internal opcodes.
This should make gdbing more pleasant, and it might be used in sharing
part of the codegen between the VS and FS backends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
|
| c9e81fe14f36933617c862efb15ae09194485eab |
|
15-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop the reg/hw_reg distinction.
"reg" was set in only one case, virtual GRFs pre register allocation,
and would be unset and have hw_reg set after allocation. Since we
never bothered with looking at virtual GRF number after allocation
anyway, just use the same storage and avoid confusion.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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| 44ffb4ae207e48f78fae55925601b8708ed09c1d |
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29-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Stop using the exec_list iterator.
The old style has gone out of favor in the project, but I kept copy
and pasting from existing iterator code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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| 3daa2d97eb13f41de4cbab9301a167be85d48642 |
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26-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix MRT drawing since the m0->m2 move for shader debug.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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| 6430df37736d71dd2bd6f1fe447d39f0b68cb567 |
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10-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Add support for TXD with shadow comparisons.
Our hardware doesn't have a sample_d_c message, so we have to do a
regular sample_d and emit instructions to manually perform the
comparison.
This requires a state dependent recompile whenever the sampler's compare
mode or function change. This adds the per-sampler comparison functions
to brw_wm_prog_key, but only sets them when the sampler's compare mode
is GL_COMPARE_R_TO_TEXTURE (i.e. only for shadow sampling).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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| 6c947cfd1973c3791d54f1406c973357b4a9621a |
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09-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Add support for non-shadow textureGrad (TXD) on gen4.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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| 3fa910fff9f72d1adf33f0f4dea3d790a9ce04ab |
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09-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Add support for non-shadow textureGrad (TXD) on Ivybridge.
This is somewhat ugly, but I couldn't think of a nicer way to handle the
interleaved coordinate/derivative parameter loading.
Ironlake and Sandybridge will still hit an assertion in visit().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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| 0653c450cc8da1212e1123a1cd6635c02f7d6919 |
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27-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix up for 8752764076e5b3f052a57e0134424a37bf2e9164.
I failed to commit and squash before pushing.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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| 11dd9e9c0fcf9985b90ff4b63b2833345fece027 |
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25-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp
This is all separate from the visitor and the optimization passes
which feed into it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
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