| e8357cb03d354756d238e99101998b028db63f0f |
|
27-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Make use of gl_transform_feedback_info::ComponentOffset.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 15f4bca2df47fed8af322217d62b35189f5ca4ab |
|
26-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix transform feedback of gl_PointSize.
On i965 Gen6 and above, gl_PointSize is stored in component W of the
first VUE slot (which corresponds to VERT_RESULT_PSIZ in the VUE map).
Normally we store varying floats in component X of a VUE slot, so we
need special case logic for gl_PointSize.
For Gen6, we do this with a ".wwww" swizzle in the GS. For Gen7, we
shift the component mask by 3 to select the W component.
Fixes Piglit test "EXT_transform_feedback/builtin-varyings
gl_PointSize".
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| b31f62c9074cb88fbb2e0b327e053778dea5b83f |
|
23-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Fix transform feedback of triangle strips.
When rendering triangle strips, vertices come down the pipeline in the
order specified, even though this causes alternate triangles to have
reversed winding order. For example, if the vertices are ABCDE, then
the GS is invoked on triangles ABC, BCD, and CDE, even though this
means that triangle BCD is in the reverse of the normal winding order.
The hardware automatically flags the triangles with reversed winding
order as _3DPRIM_TRISTRIP_REVERSE, so that face culling and two-sided
coloring can be adjusted to account for the reversed order.
In order to ensure that winding order is correct when streaming
vertices out to a transform feedback buffer, we need to alter the
ordering of BCD to BDC when the first provoking vertex convention is
in use, and to CBD when the last provoking vertex convention is in
use.
To do this, we precompute an array of indices indicating where each
vertex will be placed in the transform feedback buffer; normally this
is SVBI[0] + (0, 1, 2), indicating that vertex order should be
preserved. When the primitive type is _3DPRIM_TRISTRIP_REVERSE, we
change this order to either SVBI[0] + (0, 2, 1) or SVBI[0] + (1, 0,
2), depending on the provoking vertex convention.
Fixes piglit tests "EXT_transform_feedback/tessellation
triangle_strip" on Gen6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 7d2ff0bf0b7422c34676c2f47dbe754f57edb51e |
|
14-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Implement rasterizer discard.
This patch enables rasterizer discard functionality (a part of
transform feedback) in Gen6, by generating an alternate GS program
when rasterizer discard is active. Instead of forwarding vertices
down the pipeline, the alternate GS program uses a URB Write message
to deallocate the URB entry that was allocated by FF sync and
terminate the thread.
Note: parts of the Sandy Bridge PRM seem to imply that we could do
this more efficiently, by clearing the GEN6_GS_RENDERING_ENABLE bit,
and not allocating a URB entry at all. However, it's not clear how we
are supposed to terminate the thread if we do that. Volume 2 part 1,
section 4.5.4, says "GS threads must terminate by sending a URB_WRITE
message with the EOT and Complete bits set.", and my experiments so
far confirm that.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 21504b462acda4977c5fdfffc192e73273b8fb26 |
|
14-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement bounds checking for transform feedback output.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 9308f298300beaa757194a0db8ed50924754c011 |
|
28-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Initial implementation of transform feedback.
This patch adds basic transform feedback capability for Gen6 hardware.
This consists of several related pieces of functionality:
(1) In gen6_sol.c, we set up binding table entries for use by
transform feedback. We use one binding table entry per transform
feedback varying (this allows us to avoid doing pointer arithmetic in
the shader, since we can set up the binding table entries with the
appropriate offsets and surface pitches to place each varying at the
correct address).
(2) In brw_context.c, we advertise the hardware capabilities, which
are as follows:
MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64
MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4
MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16
OpenGL 3.0 requires these values to be at least 64, 4, and 4,
respectively. The reason we advertise a larger value than required
for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already
set aside 64 binding table entries, so we might as well make them all
available in both separate attribs and interleaved modes.
(3) We set aside a single SVBI ("streamed vertex buffer index") for
use by transform feedback. The hardware supports four independent
SVBI's, but we only need one, since vertices are added to all
transform feedback buffers at the same rate. Note: at the moment this
index is reset to 0 only when the driver is initialized. It needs to
be reset to 0 whenever BeginTransformFeedback() is called, and
otherwise preserved.
(4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader
program to output transform feedback data as a side effect.
(5) In gen6_gs_state.c, we configure the geometry shader stage to
handle the SVBI pointer correctly.
Note: ordering of vertices is not yet correct for triangle strips
(alternate triangles are improperly oriented). This will be addressed
in a future patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| d4976158c7f32705b48c773c3abd1b22bebe9c16 |
|
29-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Implement pass-through GS for transform feedback.
In Gen6, transform feedback is accomplished by having the geometry
shader send vertex data to the data port using "Streamed Vertex Buffer
Write" messages, while simultaneously passing vertices through to the
rest of the graphics pipeline (if rendering is enabled).
This patch adds a geometry shader program that simply passes vertices
through to the rest of the graphics pipeline. The rest of transform
feedback functionality will be added in future patches.
To make the new geometry shader easier to test, I've added an
environment variable "INTEL_FORCE_GS". If this environment variable
is enabled, then the pass-through geometry shader will always be used,
regardless of whether transform feedback is in effect.
On my Sandy Bridge laptop, I'm able to enable INTEL_FORCE_GS with no
Piglit regressions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 2252e5e3f1e8caece5c73df82f3ddf306baa2c91 |
|
02-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.
R02_PRIM_END and R02_PRIM_START don't actually refer to bits in DWORD
2 of R0 (as the name, and comments in the code, would seem to
indicate). Actually they refer to bits in DWORD 2 of the header for
URB_WRITE messages.
This patch renames the defines to reflect what they actually mean. It
also addes a define URB_WRITE_PRIM_TYPE_SHIFT, which previously was
just hardcoded in .c files.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 3f2283172bcaf3db00a99baad0319bc7e0be5fc2 |
|
29-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gs: Clean up dodgy register re-use, at the cost of a few MOVs.
Prior to this patch, in the Gen4 and Gen5 GS, we used GRF 0 (called
"R0" in the code) as a staging area to prepare the message header for
the FF_SYNC and URB_WRITE messages. This cleverly avoided an
unnecessary MOV operation (since the initial value of GRF 0 contains
data that needs to be included in the message header), but it made the
code confusing, since GRF 0 could no longer be relied upon to contain
its initial value once the GS started preparing its first message.
This patch avoids confusion by using a separate register ("header") as
the staging area, at the cost of one MOV instruction.
Worse yet, prior to this patch, the GS would completely overwrite the
contents of GRF 0 with the writeback data it received from a completed
FF_SYNC or URB_WRITE message. It did this because DWORD 0 of the
writeback data contains the new URB handle, and that neds to be
included in DWORD 0 of the next URB_WRITE message header. However,
that caused the rest of the message header to be corrupted either with
undefined data or zeros. Astonishingly, this did not produce any
known failures (probably by dumb luck). However, it seems really
dodgy--corrupting FFTID in particular seems likely to cause GPU hangs.
This patch avoids the corruption by storing the writeback data in a
temporary register and then copying just DWORD 0 to the header for the
next message. This costs one extra MOV instruction per message sent,
except for the final message.
Also, this patch moves the logic for overriding DWORD 2 of the header
(which contains PrimType, PrimStart, PrimEnd, and some other data that
we don't care about yet). This logic is now in the function
brw_gs_overwrite_header_dw2() rather than in brw_gs_emit_vue(). This
saves one MOV instruction in brw_gs_quads() and brw_gs_quad_strip(),
and paves the way for the Gen6 GS, which will need more complex logic
to override DWORD 2 of the header.
Finally, the function brw_gs_alloc_regs() contained a benign bug: it
neglected to increment the register counter when allocating space for
the "temp" register. This turned out not to have any effect because
the temp register wasn't used on Gen4 and Gen5, the only hardware
models (so far) to require a GS program. Now, all the registers
allocated by brw_gs_alloc_regs() are actually used, and properly
accounted for.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 728a830fae690a4c6063ba4829dabe450b6c287d |
|
14-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix inconsistent indentation in brw_gs_emit.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| a7fa203f0d645bdb06b3cb345ab1a0ccf4e62fe3 |
|
09-Apr-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Remove hint_gs_always and resulting dead code
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| e8e79c1d7eed0f5ae8820611cb86bdbd6ce595e6 |
|
14-Oct-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Fix GS hang on Sandybridge
Don't use r0 for FF_SYNC dest reg on Sandybridge, which would
smash FFID field in GS payload, that cause later URB write fail.
Also not use r0 in any URB write requiring allocate.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 81951393e1e675d6ca3ea052875def70d5e7ab93 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove constant or ignored-by-hw args from FF sync message setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| ab12e764ba3f57ad9f0d7252262cfc6e07839928 |
|
12-Nov-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: fix EXT_provoking_vertex support
This didn't work for quad/quadstrips at all, and for all other primitive types
it only worked when they were unclipped.
Fix up the former in gs stage (could probably do without these changes and
instead set QuadsFollowProvokingVertexConvention to false), and the rest in
clip stage.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| def85826a013ac61e3125db2c33d0ddf0ca5b45c |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: warning fix
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| f7cfc51b057d9d2fa109b32796b992e8f4f3bfcc |
|
18-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
Revert "[i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIP"
There is no information in GS to determinate when to reset line stipple count, still fallback to software
This reverts commit 5a0314b431ab147c6156c3011f4cb54161ba4b25.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 5a0314b431ab147c6156c3011f4cb54161ba4b25 |
|
18-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIP
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 747c9129c0b592941b14c290ff3d8ab22ad66acb |
|
17-Jan-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
I965: fix bug#9625-get the correct PV for quardstrip
The order of vertices in payload for quardstrip is (0, 1, 3, 2),
so the PV for quardstrip is c->reg.vertex[2].
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_emit.c
|