| 2da09a48dc4d5a3c585f897f256c2c6c5fa4eb5a |
|
11-Apr-2017 |
Artem Serov <artem.serov@linaro.org> |
Fix release of a QRegisters within a ScratchRegisterScope.
Test: ./tools/test.py
Change-Id: I11107d3a7c19eaf31a1dd8ad512c67d4600b7930
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 59bfe1ca76d3155c56ab97fba60646a734aeb01b |
|
24-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
[aarch64] Do not mix the Assembler and MacroAssembler in tests
Cleanup all of vixl64's test to stop use ExactAssemblyScope instead of
CodeBufferCheckScope. The latter allows for mixing the assembler and
macro-assembler.
Fixing the disassembler tests were not completely obvious. We used to
have a different SETUP macro for the Assembler and MacroAssembler. It's
much simpler to have a single SETUP macro that always creates a
MacroAssembler and then use COMPARE or COMPARE_MACRO to define the
tests. The former allows the Assembler with an ExactAssemblyScope while
the latter does not.
Change-Id: Ic37c25742b77767f257f88e06c7e4106ea55425f
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| bde2e4b5ce376456d50a972b6f3aaee3475f8786 |
|
24-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Enable clang-format in the tests
Extend the clang_format.py script to format everything by trace files in
the `test/` directory. Also, we have to add "on/off" marker in
`test-simualtor-inputs-aarch64.h` as clang-format is getting confused
there.
Change-Id: I1159498072bda1bfd049082aeccb347ec55e7825
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 4fea551fb8ef5884ebd7157a82b1635063ea651f |
|
17-Jan-2017 |
Jacob Bramley <jacob.bramley@arm.com> |
Add specialised W and X Register classes.
These allow for the register type to be determined at compile time, so that the
it can be used for overload resolution.
Note that this does break the API in the case of the ternary operator. The
following pattern will no longer work:
Register r0 = (condition) ? x0 : w0;
The workaround is to explicitly cast each register:
Register r0 = (condition) ? Register(x0) : Register(w0);
Some existing overload situation may also fail with the new scheme; in general,
resolutions can be added by simply providing specific WRegister and XRegister
implementations, which typically can fall through to the existing Register
implementation with an explicit cast.
In the future, we expect an extension which will make WRegister and XRegister
POD types.
Change-Id: I6da8e3f87161f23de7c13e3c5142d4fc40532090
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| e79723a010a6f42fe78e2515c7b0eb9308b93093 |
|
07-Jun-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Trace taken branches in the A64 simulator.
This is useful when debugging generated code, as it allows branch points to be
quickly identified and examined.
Change-Id: I2d1fdaf6fbf24582c73b2a301bc1a01217ef0fd3
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| a38f9aec7b79989b658790b2492e2de67a64b430 |
|
22-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Ensure `MacroAssembler::Nop` generates a single `nop`.
The `MacroAssembler` is allowed to emit any code that is functionally
equivalent to what is requested by the user, and is expected to
generate 'good' code. The user can expect calls such as
`masm.Add(r0, r0, 0)` to be optimized away (think that `0` may be the
value of a variable).
Following this we *could* generate no code for calls to `Nop()`. But
`Nop()` will likely not be used by mistake, so we ensure it generates
at least one `nop` instruction. This is useful for tests where we want
to generate 'some' code.
Change-Id: Iecf31b5cfd151a77b1633ea5158ff54fef9f8908
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 5b24fb388927a1f1801a15d460d4c9448f7aa733 |
|
02-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Fix simulator-aarch64 to satisfy UBSan.
Most changes are fixing shifts of signed integers, or out of range shifts.
Change-Id: Ic5787ac2e99f05fd0d3118060f80b39d9e8d5621
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 07d1aa5b941ace15deb01e5df2c79e677039c4ae |
|
25-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch64: follow the design guidelines for `ExactAssemblyScope`.
Change-Id: I5b942e033681c69f5e6cac3a669b3b3ebacbf1f8
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| fac0a468cc6d7319f12a279beaded4236b6b394d |
|
25-Oct-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Fix AreConsecutive and add tests
AreConsecutive misreported eg. (v0, NoVReg, v3, v4) as false, when the prototype
description says all registers after NoVReg are ignored.
Change-Id: I211dddaf828353fa84ca2815c32c0f5f73a02987
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| b953ea8255b36e27834f17941429cd17af12f6f2 |
|
20-Oct-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Fix simulation of NEON min/maxp and tbl
The simulation of [su](min|max)p, tbl and tbx was broken when source and
destination registers aliased. Fix these and add regression tests.
Change-Id: I3945e520df7a1f9453595c9941bdfbb3447ae581
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 9dd6fa37dbb79f62177aebd04d7e945ce1dc3108 |
|
12-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Follow the design guidelines for the AArch64 `CodeBufferCheckScope`.
The implementation of the scopes relies only on the `AssemblerBase` interface.
The AArch32 scopes will be updated in a separate commit.
Change-Id: Ibe0eab35f60da39fe0bcbd60a16bdc65b12e0dd5
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 6a049f97861bd71c69d81f643e42308d28c5de31 |
|
21-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Unify the `Assembler` helpers related to the code buffer.
A few helpers in `Assembler` classes that were simply wrappers around
`CodeBuffer` methods have been deprecated, and should be replaced by calls to
the `CodeBuffer` methods.
Change-Id: I72608c8c1f1f2823c58c8f6de042e932abe12629
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 919e3fe28a5024c53ede42922092bbc32e89dcb8 |
|
14-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Create a base class for assemblers.
This base class defines an interface that assemblers must adhere to.
For now, we use it to hold the code buffer.
Change-Id: I487430bb98c7044e57b348cffa1e74a2a4c8026f
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 5ffcded0741a916337d39246361d2e61737b06a4 |
|
17-Oct-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Don't assume that pointer offsets fit in 32 bits.
In particular, low-level instruction helpers like adr, b and the like should
accept full 64-bit offsets. In all cases, an int can hold the offset, but
narrowing the offset on input weakens the size assertion.
Also note that this breaks backwards-compatibility, but only for some esoteric
use-cases that access the Assembler directly: 'adr(x0, 0)' will now fail to
compile because the call is ambiguous between the int64_t and Label* variants.
Change-Id: I9821d742ff7b8e497e79fdede8af35a1d6325d23
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| bc01be684fe63a8a8c785f92e8aaa080cb6e87fa |
|
12-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce --disassemble option to test-runner
This patch adds a "--disassemble" option that one can pass to the
test-runner binary so that generated instructions will be printed to
standard output before executing.
Change-Id: Idb767a43d8f2bd8fdd4fa3718b973fb35204d0e0
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| ea4c632f0a2e6c8f75cb4a64658f66015408f0ed |
|
12-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Workaround for AArch64 platforms not supporting CRC32.
For now we disable the CRC32 tests when running natively, to let the
tests pass when running natively on platforms not supporting it. A
task is open to address the issue.
Change-Id: I7921440058d5d62205a99d94bf968b7327735b9c
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 0ec9dc10536b569b807274627e8c61bf6d6ceae7 |
|
05-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Rewrite `VIXL_CHECK` in terms of `abort`.
The `VIXL_CHECK` macro is meant to be used for runtime checks. However
VIXL is built, the check should always be done. We used `assert` to
implement `VIXL_CHECK`, but an assertion in C can be disabled with the
`NDEBUG` macro, which is also how Android builds VIXL.
This patch also replaces uses of asserts with `VIXL_CHECK`.
Change-Id: I576c5b4910c7dee66e37c3fd9f73ad4edca3f4b7
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 31dd2ae90d5e82871667fbf3ee2697a155e7c3ac |
|
05-Jul-2016 |
Alex Gilday <Alexander.Gilday2@arm.com> |
Correctly allocate executable memory in CodeBuffer
CodeBuffer allocates memory that is executable via an ExecuteMemory
function.
Change-Id: Ib2dca824e9edd3144694cfac627becd35dd48e3c
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 1c78c34397f2c08c012733cc661076e8bd029eab |
|
16-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch64: Do not bypass optimisations in `Mov` for registers.
Change-Id: I060e7518cf7e3bca5b531b714683a64f73ea8ba0
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 23703a72b1cd9a49428bcd850429f7be381c1e63 |
|
15-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
[test] Fix NEON tests that assume zero'ed registers
Some of the NEON AArch64 tests would rely on the top 64 bit of Q
registers to be initialized with zero, which is not guaranteed to be the
case.
Change-Id: I374d40b759fd57d58ce244dde1cb0491456f8b72
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 1372e357419917aaa4d7aa626e12fb4ac5092850 |
|
23-Aug-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch64: Avoid running the runtime call test for unsupported configurations.
Change-Id: I2e0ce910fe5f5bb71188b62e7b5b4bdade8fb763
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| a4055d25c688d1397fc369a40abf57fa4f1ab805 |
|
17-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Add guards around the AArch64 simulator
If VIXL_INCLUDE_SIMULATOR_AARCH64 is not defined, including the
"simulator-aarch64.h" header should have no effect. We couldn't do this
because the macro-assembler relies on TraceCommand and TraceParameter
being defined.
Change-Id: Ide0b9f87482e51addfb2b6199cb5453ca4f15f7f
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 1e85b7f2e8ad2bfb233de29405aade635ed207ce |
|
05-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce architecture specific guards for the simulator
This patch makes the VIXL_INCLUDE_SIMULATOR and
VIXL_GENERATE_SIMULATOR_CODE header guards specific to either AArch64 or
AArch32. Even though the simulator only support AArch64. The build
system was updated accordingly, the "simulator" variable now takes
"aarch64" or "none" as possible values instead of "on" and "off".
This fixes issues we have when we want to build VIXL natively on
AArch64 without a simulator, but still include the AArch32
macro-assembler. The later would check for VIXL_GENERATE_SIMULATOR_CODE
and then generate calls to native code, which breaks.
Change-Id: I2850782558d4cc37f37c1644f0efbd70a3123057
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| c3487d2febf913244d5789d096732df569e8b7fd |
|
12-Aug-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Fix macros for `CallRuntime` support.
The associated test was failing to compile natively.
Change-Id: I8962f348d3e019766c778dacd5c05f93b2295630
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 78973f258039f6e96eba85f1b5ecdb14b3c51dbb |
|
10-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly include C headers
This patch refactors VIXL to use `extern` block when including C header
that do not have a C++ counterpart.
Change-Id: I203d7d107755dbac3e5f4cf8d2f196f70dea1e07
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| de5bb0beb4a3342bb9f0d7e7fe16737a171517b0 |
|
04-Aug-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch64: Refactor `InstructionAccurateScope` and add a regression test.
The previous implementation was not emitting the pools when it needed to upon
construction, and was not correctly blocking emission of the pools.
Change-Id: I06db5b5891234946b139ba64898929c0e3ced3c4
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 482d4df29d1466ff87d94e74034f1a8659f1b354 |
|
05-Aug-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Work around a GCC bug in runtime call support.
For now, simulated runtime call support is disabled for GCC before
version 4.9.1. A proper fix requires another way to force evaluation
order.
Also, fix a compiler warning.
Change-Id: Iffb258aec6f36cdd0a1e0da2f419bd3de0c6ca72
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| ca73ba046c11d65b6dce59cfd26847d14aba06ab |
|
28-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Fix `#define` directives related to ABI and runtime call simulation.
Also add a regression test.
Change-Id: Iad770e7181f3b994590bdee069845885039e8bc4
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 064e02d4e85938b2e2be4d4b37a2691b2e015ebb |
|
12-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch64: Support runtime call simulation.
Change-Id: I063c2223a63791e90d8aa9cffc6e88f96d57187e
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 4e7c93cc256c7719d69279d64e4f5d09044b8b2c |
|
19-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch64: Introduce a new `GenericOperand` abstraction.
Currently, a `GenericOperand` can represent a `CPURegister` or a
memory area (`MemOperand` extended by a 'size' field).
Change-Id: Ic37c4da07ea888444ccb1bfbd82646d0c56bbe84
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| 703ff06a087f67fccde24a7ffbc8a2e74a406cb1 |
|
11-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Aarch64: Rename `allow_simulator_instructions_` to `generate_simulator_code_`.
Change-Id: I72956db90ab3380b5ad62b37d2ed203ec4045931
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|
| d3832965c62a8ad461b9ea9eb0994ca6b0a3da2c |
|
04-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Update naming to `aarch32` and `aarch64`.
Change-Id: I40a929b1095ee3e1b2ca5ef879c7006d8b59acc9
/external/vixl/test/aarch64/test-assembler-aarch64.cc
|