Searched defs:Imm (Results 1 - 25 of 155) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.h88 virtual bool selectVSplat(SDNode *N, APInt &Imm,
91 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
93 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
95 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
97 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
99 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
101 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
103 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
105 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
107 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons
123 getImm(const SDNode *Node, uint64_t Imm) argument
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H A DMipsAnalyzeImmediate.cpp29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument
43 unsigned Shamt = countTrailingZeros(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument
126 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.h73 inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) { argument
74 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
/external/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { argument
46 if (Imm == 0)
49 if (Imm.getBitWidth() <= 64) {
51 if (isInt<32>(Imm.getSExtValue()))
54 if (isUInt<32>(Imm.getZExtValue()))
57 if ((Imm.getZExtValue() & 0xffffffff) == 0)
67 const APInt &Imm, Type *Ty) {
90 if (Idx == 0 && Imm.getBitWidth() <= 64) {
95 if (isInt<16>(Imm.getSExtValue()))
100 if (Idx == 1 && Imm
66 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) argument
184 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) argument
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/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp88 const ConstantFP *Imm = MO.getFPImm(); local
89 if (Imm->getType()->isFloatTy())
90 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat());
91 else if (Imm->getType()->isDoubleTy())
92 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble());
H A DWebAssemblyRegNumbering.cpp76 int64_t Imm = MI.getOperand(1).getImm(); local
78 << Imm << "\n");
79 MFI.setWAReg(MI.getOperand(0).getReg(), Imm);
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h841 bool isLegalICmpImmediate(int64_t Imm) const override;
847 bool isLegalAddImmediate(int64_t Imm) const override;
903 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
942 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1023 void addLegalFPImmediate(const APFloat& Imm) { argument
1024 LegalFPImmediates.push_back(Imm);
H A DX86FrameLowering.cpp98 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) { argument
100 if (isInt<8>(Imm))
104 if (isInt<8>(Imm))
110 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) { argument
112 if (isInt<8>(Imm))
116 if (isInt<8>(Imm))
130 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) { argument
132 if (isInt<8>(Imm))
136 if (isInt<8>(Imm))
/external/llvm/lib/Target/WebAssembly/Disassembler/
H A DWebAssemblyDisassembler.cpp100 uint64_t Imm = support::endian::read64le(Bytes.data() + Pos);
102 MI.addOperand(MCOperand::createImm(Imm));
121 double Imm; local
122 memcpy(&Imm, &Bits, sizeof(Imm));
123 MI.addOperand(MCOperand::createFPImm(Imm));
138 uint64_t Imm = support::endian::read64le(Bytes.data() + Pos); local
139 MI.addOperand(MCOperand::createImm(Imm));
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DPseudoLoweringEmitter.h23 enum MapKind { Operand, Imm, Reg }; enumerator in enum:llvm::PseudoLoweringEmitter::OpData::MapKind
27 uint64_t Imm; // Integer immedate value. member in union:llvm::PseudoLoweringEmitter::OpData::__anon19141
/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp87 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { argument
90 return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
95 static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) { argument
100 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
102 Imm &= ~(0xFFFFLL << ShiftAmt);
104 return Imm | Chunk;
267 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
272 Imm &= ~(Mask << (Idx * 16));
275 Imm |= Mask << (Idx * 16);
277 return Imm;
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp89 static uint32_t getIntInlineImmEncoding(IntTy Imm) { argument
90 if (Imm >= 0 && Imm <= 64)
91 return 128 + Imm;
93 if (Imm >= -16 && Imm <= -1)
94 return 192 + std::abs(Imm);
166 int64_t Imm; local
172 Imm = C->getValue();
180 Imm
222 int64_t Imm = 0; local
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/external/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp129 uint64_t Imm = MO.isImm() ? MO.getImm() : 0; local
134 LE.write<uint32_t>(Imm >> 32);
136 BE.write<uint32_t>(Imm >> 32);
/external/llvm/lib/Target/Lanai/
H A DLanaiISelDAGToDAG.cpp86 inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) { argument
87 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
109 int32_t Imm = CN->getSExtValue(); local
110 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
131 int16_t Imm = CN->getSExtValue(); local
132 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
144 int16_t Imm = CN->getSExtValue(); local
145 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
301 SDValue Imm = CurDAG->getTargetConstant(0, DL, MVT::i32); local
307 CurDAG->SelectNodeTo(Node, Opc, VT, TFI, Imm);
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/external/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCTargetDesc.cpp93 int64_t Imm = Inst.getOperand(0).getImm(); variable
94 Target = Addr + Size + Imm;
97 int64_t Imm = Inst.getOperand(0).getImm(); variable
101 if (Imm == 0)
104 Target = Imm;
/external/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.cpp146 uint64_t Imm = MO.getImm(); local
147 Imm -= Offset;
148 Imm &= (1 << Bits) - 1;
149 Imm += Offset;
150 O << formatImm(Imm);
/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp95 int64_t Imm = MO.getImm(); local
99 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
103 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
107 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
145 int64_t Imm = MO.getImm(); local
149 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
152 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
219 int Imm = (int) MO.getImm(); local
221 if (Imm)
224 switch (Imm) {
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp277 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; local
278 return reverseBits(Imm | RegBits) >> 22;
293 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; local
294 return reverseBits(Imm | RegBits) >> 22;
309 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; local
310 return reverseBits(Imm | RegBits) >> 22;
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp74 int64_t Imm = MI->getOperand(Op).getImm(); local
75 switch (Imm) {
114 int64_t Imm = MI->getOperand(Op).getImm(); local
115 switch (Imm) {
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; local
131 switch (Imm) {
169 int64_t Imm = Op.getImm(); local
170 O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
178 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm <
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H A DX86IntelInstPrinter.cpp56 int64_t Imm = MI->getOperand(Op).getImm(); local
57 switch (Imm) {
96 int64_t Imm = MI->getOperand(Op).getImm(); local
97 switch (Imm) {
112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; local
113 switch (Imm) {
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
H A DMBlazeISelDAGToDAG.cpp89 inline SDValue getI32Imm(unsigned Imm) { argument
90 return CurDAG->getTargetConstant(Imm, MVT::i32);
100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) { argument
105 Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
107 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
109 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) { argument
113 return isIntS32Immediate(Op.getNode(), Imm);
166 uint32_t Imm = CN->getZExtValue(); local
167 Disp = CurDAG->getTargetConstant(Imm, C
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/
H A DPTXInstPrinter.cpp118 double Imm = Op.getFPImm(); local
119 APFloat FPImm(Imm);
/external/swiftshader/third_party/LLVM/lib/Target/X86/Utils/
H A DX86ShuffleDecode.cpp23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) { argument
31 unsigned ZMask = Imm & 15;
32 unsigned CountD = (Imm >> 4) & 3;
33 unsigned CountS = (Imm >> 6) & 3;
66 void DecodePSHUFMask(unsigned NElts, unsigned Imm, argument
69 ShuffleMask.push_back(Imm % NElts);
70 Imm /= NElts;
74 void DecodePSHUFHWMask(unsigned Imm, argument
81 ShuffleMask.push_back(4+(Imm & 3));
82 Imm >>
86 DecodePSHUFLWMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) argument
131 DecodeSHUFPSMask(unsigned NElts, unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) argument
193 DecodeVPERMILPSMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) argument
210 DecodeVPERMILPDMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) argument
223 DecodeVPERM2F128Mask(EVT VT, unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) argument
235 DecodeVPERM2F128Mask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) argument
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86FrameLowering.cpp58 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) { argument
60 if (isInt<8>(Imm))
64 if (isInt<8>(Imm))
70 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) { argument
72 if (isInt<8>(Imm))
76 if (isInt<8>(Imm))
/external/llvm/lib/CodeGen/
H A DStackMaps.cpp103 int64_t Imm = (++MOI)->getImm(); local
105 getDwarfRegNum(Reg, TRI), Imm);
112 int64_t Imm = (++MOI)->getImm(); local
114 getDwarfRegNum(Reg, TRI), Imm);
120 int64_t Imm = MOI->getImm(); local
121 Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, Imm);

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