1//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an Mips MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsInstPrinter.h"
15#include "MCTargetDesc/MipsMCExpr.h"
16#include "MipsInstrInfo.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCSymbol.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/raw_ostream.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "asm-printer"
27
28#define PRINT_ALIAS_INSTR
29#include "MipsGenAsmWriter.inc"
30
31template<unsigned R>
32static bool isReg(const MCInst &MI, unsigned OpNo) {
33  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
34  return MI.getOperand(OpNo).getReg() == R;
35}
36
37const char* Mips::MipsFCCToString(Mips::CondCode CC) {
38  switch (CC) {
39  case FCOND_F:
40  case FCOND_T:   return "f";
41  case FCOND_UN:
42  case FCOND_OR:  return "un";
43  case FCOND_OEQ:
44  case FCOND_UNE: return "eq";
45  case FCOND_UEQ:
46  case FCOND_ONE: return "ueq";
47  case FCOND_OLT:
48  case FCOND_UGE: return "olt";
49  case FCOND_ULT:
50  case FCOND_OGE: return "ult";
51  case FCOND_OLE:
52  case FCOND_UGT: return "ole";
53  case FCOND_ULE:
54  case FCOND_OGT: return "ule";
55  case FCOND_SF:
56  case FCOND_ST:  return "sf";
57  case FCOND_NGLE:
58  case FCOND_GLE: return "ngle";
59  case FCOND_SEQ:
60  case FCOND_SNE: return "seq";
61  case FCOND_NGL:
62  case FCOND_GL:  return "ngl";
63  case FCOND_LT:
64  case FCOND_NLT: return "lt";
65  case FCOND_NGE:
66  case FCOND_GE:  return "nge";
67  case FCOND_LE:
68  case FCOND_NLE: return "le";
69  case FCOND_NGT:
70  case FCOND_GT:  return "ngt";
71  }
72  llvm_unreachable("Impossible condition code!");
73}
74
75void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
76  OS << '$' << StringRef(getRegisterName(RegNo)).lower();
77}
78
79void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
80                                StringRef Annot, const MCSubtargetInfo &STI) {
81  switch (MI->getOpcode()) {
82  default:
83    break;
84  case Mips::RDHWR:
85  case Mips::RDHWR64:
86    O << "\t.set\tpush\n";
87    O << "\t.set\tmips32r2\n";
88    break;
89  case Mips::Save16:
90    O << "\tsave\t";
91    printSaveRestore(MI, O);
92    O << " # 16 bit inst\n";
93    return;
94  case Mips::SaveX16:
95    O << "\tsave\t";
96    printSaveRestore(MI, O);
97    O << "\n";
98    return;
99  case Mips::Restore16:
100    O << "\trestore\t";
101    printSaveRestore(MI, O);
102    O << " # 16 bit inst\n";
103    return;
104  case Mips::RestoreX16:
105    O << "\trestore\t";
106    printSaveRestore(MI, O);
107    O << "\n";
108    return;
109  }
110
111  // Try to print any aliases first.
112  if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
113    printInstruction(MI, O);
114  printAnnotation(O, Annot);
115
116  switch (MI->getOpcode()) {
117  default:
118    break;
119  case Mips::RDHWR:
120  case Mips::RDHWR64:
121    O << "\n\t.set\tpop";
122  }
123}
124
125void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
126                                   raw_ostream &O) {
127  const MCOperand &Op = MI->getOperand(OpNo);
128  if (Op.isReg()) {
129    printRegName(O, Op.getReg());
130    return;
131  }
132
133  if (Op.isImm()) {
134    O << formatImm(Op.getImm());
135    return;
136  }
137
138  assert(Op.isExpr() && "unknown operand kind in printOperand");
139  Op.getExpr()->print(O, &MAI, true);
140}
141
142template <unsigned Bits, unsigned Offset>
143void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
144  const MCOperand &MO = MI->getOperand(opNum);
145  if (MO.isImm()) {
146    uint64_t Imm = MO.getImm();
147    Imm -= Offset;
148    Imm &= (1 << Bits) - 1;
149    Imm += Offset;
150    O << formatImm(Imm);
151    return;
152  }
153
154  printOperand(MI, opNum, O);
155}
156
157void MipsInstPrinter::
158printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
159  // Load/Store memory operands -- imm($reg)
160  // If PIC target the target is loaded as the
161  // pattern lw $25,%call16($28)
162
163  // opNum can be invalid if instruction had reglist as operand.
164  // MemOperand is always last operand of instruction (base + offset).
165  switch (MI->getOpcode()) {
166  default:
167    break;
168  case Mips::SWM32_MM:
169  case Mips::LWM32_MM:
170  case Mips::SWM16_MM:
171  case Mips::SWM16_MMR6:
172  case Mips::LWM16_MM:
173  case Mips::LWM16_MMR6:
174    opNum = MI->getNumOperands() - 2;
175    break;
176  }
177
178  printOperand(MI, opNum+1, O);
179  O << "(";
180  printOperand(MI, opNum, O);
181  O << ")";
182}
183
184void MipsInstPrinter::
185printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
186  // when using stack locations for not load/store instructions
187  // print the same way as all normal 3 operand instructions.
188  printOperand(MI, opNum, O);
189  O << ", ";
190  printOperand(MI, opNum+1, O);
191  return;
192}
193
194void MipsInstPrinter::
195printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
196  const MCOperand& MO = MI->getOperand(opNum);
197  O << MipsFCCToString((Mips::CondCode)MO.getImm());
198}
199
200void MipsInstPrinter::
201printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) {
202  printRegName(O, MI->getOperand(opNum).getReg());
203}
204
205void MipsInstPrinter::
206printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
207  llvm_unreachable("TODO");
208}
209
210bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
211                                 unsigned OpNo, raw_ostream &OS) {
212  OS << "\t" << Str << "\t";
213  printOperand(&MI, OpNo, OS);
214  return true;
215}
216
217bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
218                                 unsigned OpNo0, unsigned OpNo1,
219                                 raw_ostream &OS) {
220  printAlias(Str, MI, OpNo0, OS);
221  OS << ", ";
222  printOperand(&MI, OpNo1, OS);
223  return true;
224}
225
226bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
227  switch (MI.getOpcode()) {
228  case Mips::BEQ:
229  case Mips::BEQ_MM:
230    // beq $zero, $zero, $L2 => b $L2
231    // beq $r0, $zero, $L2 => beqz $r0, $L2
232    return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
233            printAlias("b", MI, 2, OS)) ||
234           (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
235  case Mips::BEQ64:
236    // beq $r0, $zero, $L2 => beqz $r0, $L2
237    return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
238  case Mips::BNE:
239    // bne $r0, $zero, $L2 => bnez $r0, $L2
240    return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
241  case Mips::BNE64:
242    // bne $r0, $zero, $L2 => bnez $r0, $L2
243    return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
244  case Mips::BGEZAL:
245    // bgezal $zero, $L1 => bal $L1
246    return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
247  case Mips::BC1T:
248    // bc1t $fcc0, $L1 => bc1t $L1
249    return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
250  case Mips::BC1F:
251    // bc1f $fcc0, $L1 => bc1f $L1
252    return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
253  case Mips::JALR:
254    // jalr $ra, $r1 => jalr $r1
255    return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
256  case Mips::JALR64:
257    // jalr $ra, $r1 => jalr $r1
258    return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
259  case Mips::NOR:
260  case Mips::NOR_MM:
261  case Mips::NOR_MMR6:
262    // nor $r0, $r1, $zero => not $r0, $r1
263    return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
264  case Mips::NOR64:
265    // nor $r0, $r1, $zero => not $r0, $r1
266    return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
267  case Mips::OR:
268    // or $r0, $r1, $zero => move $r0, $r1
269    return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
270  default: return false;
271  }
272}
273
274void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
275  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
276    if (i != 0) O << ", ";
277    if (MI->getOperand(i).isReg())
278      printRegName(O, MI->getOperand(i).getReg());
279    else
280      printUImm<16>(MI, i, O);
281  }
282}
283
284void MipsInstPrinter::
285printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
286  // - 2 because register List is always first operand of instruction and it is
287  // always followed by memory operand (base + offset).
288  for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
289    if (i != opNum)
290      O << ", ";
291    printRegName(O, MI->getOperand(i).getReg());
292  }
293}
294