Searched defs:Insn (Results 1 - 17 of 17) sorted by relevance

/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DPseudoLoweringEmitter.cpp27 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, argument
46 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
50 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
54 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
56 OpsAdded += Insn.Operands[i].MINumOperands;
65 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
93 CodeGenInstruction Insn(Operator);
95 if (Insn.isCodeGenOnly || Insn.isPseudo)
99 if (Insn
[all...]
H A DARMDecoderEmitter.cpp424 void insnWithID(insn_t &Insn, unsigned Opcode) const { argument
431 Insn[i] = bitFromBits(Bits, i);
437 Insn[21] = BIT_TRUE;
450 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
479 insn_t &Insn);
558 insn_t Insn; local
561 Owner->insnWithID(Insn, Owner->Opcodes[i]);
565 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits);
853 bool ARMFilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, argument
858 if (Insn[StartBi
933 getIslands(std::vector<unsigned> &StartBits, std::vector<unsigned> &EndBits, std::vector<uint64_t> &FieldVals, insn_t &Insn) argument
998 insn_t Insn; local
1117 insn_t Insn; local
[all...]
H A DFixedLenDecoderEmitter.cpp285 void insnWithID(insn_t &Insn, unsigned Opcode) const { argument
289 Insn.push_back(bitFromBits(Bits, i));
302 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
331 insn_t &Insn);
396 insn_t Insn; local
399 Owner->insnWithID(Insn, Owner->Opcodes[i]);
403 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits);
600 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, argument
605 if (Insn[StartBit + i] == BIT_UNSET)
608 if (Insn[StartBi
680 getIslands(std::vector<unsigned> &StartBits, std::vector<unsigned> &EndBits, std::vector<uint64_t> &FieldVals, insn_t &Insn) argument
809 insn_t Insn; local
953 insn_t Insn; local
[all...]
/external/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldMachOARM.h163 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); variable
164 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff);
165 writeBytesUnaligned(Insn, LocalAddress, 4);
/external/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp53 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
56 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
59 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
62 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
69 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
75 uint64_t &Size, uint32_t &Insn) {
83 Insn =
89 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { argument
100 AluOp = (Insn >> 8) & 0x7;
104 AluOp |= 0x20 | (((Insn >>
74 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
135 uint32_t Insn; local
173 decodeRiMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
185 decodeRrMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
197 decodeSplsValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
218 decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address, const void *Decoder) argument
226 decodeShiftImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp56 CodeGenInstruction &Insn,
74 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, argument
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
103 OpsAdded += Insn.Operands[i].MINumOperands;
112 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
140 CodeGenInstruction Insn(Operator);
142 if (Insn.isCodeGenOnly || Insn
[all...]
H A DFixedLenDecoderEmitter.cpp367 void insnWithID(insn_t &Insn, unsigned Opcode) const { argument
380 Insn.push_back(BIT_UNSET);
382 Insn.push_back(bitFromBits(Bits, i));
396 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
424 const insn_t &Insn) const;
504 insn_t Insn; local
507 Owner->insnWithID(Insn, Owner->Opcodes[i]);
511 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits);
926 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn,
931 if (Insn[StartBi
[all...]
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp46 uint64_t &Size, uint16_t &Insn) {
53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
58 uint64_t &Size, uint32_t &Insn) {
65 Insn =
93 unsigned Insn,
98 unsigned Insn,
103 unsigned Insn,
108 unsigned Insn,
113 unsigned Insn,
118 unsigned Insn,
45 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint16_t &Insn) argument
57 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) argument
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3) argument
275 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
345 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
358 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
371 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
384 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
398 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
411 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
424 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
438 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
509 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
523 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
537 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
550 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
563 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
576 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
589 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
603 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
618 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
632 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
646 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
666 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
680 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
700 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
719 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp321 uint64_t &Size, uint32_t &Insn,
329 Insn = IsLittleEndian
343 uint32_t Insn; local
346 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
354 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
358 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
364 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
320 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian) argument
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
H A DCodeGenPrepare.cpp235 Instruction *Insn = dyn_cast<Instruction>(UPN->getIncomingValue(I)); local
236 if (Insn && Insn->getParent() == BB &&
237 Insn->getParent() != UPN->getIncomingBlock(I))
1154 Instruction *Insn = BI; ++BI; local
1155 DbgValueInst *DVI = dyn_cast<DbgValueInst>(Insn);
1157 PrevNonDbgInst = Insn;
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp144 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
223 uint32_t Insn = local
227 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
647 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, argument
652 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
653 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
654 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp102 unsigned Insn,
136 unsigned Insn,
206 unsigned Insn,
256 unsigned Insn,
261 unsigned Insn,
266 unsigned Insn,
271 unsigned Insn,
276 unsigned Insn,
281 unsigned Insn,
286 unsigned Insn,
908 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian) argument
928 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips) argument
967 uint32_t Insn; local
1266 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1288 DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1309 DecodeLoadByte9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1327 DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1345 DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1362 DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1379 DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1396 DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1413 DecodeStoreEvaOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1431 DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1446 DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1461 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1507 DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1565 DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1581 DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1597 DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1622 DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1643 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1679 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1697 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1715 DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1733 DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1751 DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1769 DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1787 DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1803 DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1987 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2064 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2124 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2135 DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2141 DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2147 DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2161 DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2200 DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2224 DecodeMovePRegPair(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2269 DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/ExecutionEngine/RuntimeDyld/
H A DRuntimeDyldELF.cpp509 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); local
519 Insn &= 0xfc000000;
520 Insn |= (Value & 0x0fffffff) >> 2;
521 writeBytesUnaligned(Insn, TargetPtr, 4);
525 Insn &= 0xffff0000;
526 Insn |= ((Value + 0x8000) >> 16) & 0xffff;
527 writeBytesUnaligned(Insn, TargetPtr, 4);
530 Insn &= 0xffff0000;
531 Insn |= Value & 0xffff;
532 writeBytesUnaligned(Insn, TargetPt
733 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
148 unsigned Insn,
151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
161 unsigned Insn,
164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1181 DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1336 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1480 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1591 DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1620 DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1705 DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1745 DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1785 DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1809 DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1835 DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1908 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1955 DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2204 DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2454 DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2493 DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2529 DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2564 DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2617 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2662 DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2705 DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2736 DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
2842 DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2980 DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3025 DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3036 DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3061 DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3072 DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3104 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3120 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3233 DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3256 DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3283 DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3308 DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3336 DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3361 DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3386 DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3445 DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3503 DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3570 DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3634 DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3704 DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3768 DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3842 DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3907 DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3933 DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3959 DecodeIT(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3986 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4023 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4057 DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
191 unsigned Insn,
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
204 unsigned Insn,
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
415 checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &OS, raw_ostream &CS, uint32_t Insn, DecodeStatus Result) argument
453 uint32_t Insn = local
1321 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1471 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1620 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1811 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1840 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1863 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1955 DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1977 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2024 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2066 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2090 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2117 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2145 DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2166 DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2260 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2287 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2330 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2604 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2617 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2632 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2645 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2655 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2926 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2973 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3021 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3056 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3109 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3154 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3197 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3233 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3356 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3438 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3522 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3602 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3641 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3797 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3884 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3895 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3920 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3931 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3984 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4000 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4227 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4248 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4273 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4298 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4326 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4351 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4376 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4443 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4509 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4576 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4640 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4710 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4774 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4855 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4927 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4953 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4979 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4999 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5036 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5070 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument
5096 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5123 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5182 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp447 Instruction *Insn = dyn_cast<Instruction>(UPN->getIncomingValue(I)); local
448 if (Insn && Insn->getParent() == BB &&
449 Insn->getParent() != UPN->getIncomingBlock(I))
5354 Instruction *Insn = &*BI++; local
5355 DbgValueInst *DVI = dyn_cast<DbgValueInst>(Insn);
5362 PrevNonDbgInst = Insn;
/external/dexmaker/lib/
H A Ddalvik-dx-1.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/android/ com/android/dx/ com/android/dx/cf/ ...

Completed in 1625 milliseconds