/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 44 uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize) const; 59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 163 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO, argument 167 if (MO.isExpr()) { 168 const MCConstantExpr *C = dyn_cast<MCConstantExpr>(MO.getExpr()); 175 assert(!MO.isFPImm()); 177 if (!MO.isImm()) 180 Imm = MO.getImm(); 245 const MCOperand &MO = MI.getOperand(OpNo); local 247 if (MO 257 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | R600EmitClauseMarkers.cpp | 67 MachineOperand &MO = *It; local 68 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
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/external/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFMCCodeEmitter.cpp | 50 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 77 const MCOperand &MO, 80 if (MO.isReg()) 81 return MRI.getEncodingValue(MO.getReg()); 82 if (MO.isImm()) 83 return static_cast<unsigned>(MO.getImm()); 85 assert(MO.isExpr()); 87 const MCExpr *Expr = MO.getExpr(); 128 const MCOperand &MO = MI.getOperand(1); local 129 uint64_t Imm = MO 76 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 107 const MachineOperand &MO = MI.getOperand(i); local 108 if (MO.isReg()) 109 Vector[i] = BT::RegisterRef(MO); 131 const MachineOperand &MO = MI.getOperand(i); 132 if (!MO.isReg() || !MO.isDef()) 135 assert(MO.getSubReg() == 0); 170 const MachineOperand &MO = MI.getOperand(i); 171 if (MO.isGlobal() || MO [all...] |
H A D | HexagonBranchRelaxation.cpp | 199 MachineOperand &MO = MI.getOperand(ExtOpNum); local 203 assert(MO.isMBB() && "Branch with unknown expandable field type"); 205 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
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/external/llvm/lib/Target/Lanai/ |
H A D | LanaiAsmPrinter.cpp | 67 const MachineOperand &MO = MI->getOperand(OpNum); local 69 switch (MO.getType()) { 71 O << LanaiInstPrinter::getRegisterName(MO.getReg()); 75 O << MO.getImm(); 79 O << *MO.getMBB()->getSymbol(); 83 O << *getSymbol(MO.getGlobal()); 87 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress()); 93 O << *GetExternalSymbolSymbol(MO.getSymbolName()); 98 << MO.getIndex(); 103 << MO 135 const MachineOperand &MO = MI->getOperand(RegOp); local [all...] |
H A D | LanaiDelaySlotFiller.cpp | 206 const MachineOperand &MO = MI->getOperand(I); local 209 if (!MO.isReg() || !(Reg = MO.getReg())) 212 if (MO.isDef()) { 217 if (MO.isUse()) { 235 const MachineOperand &MO = MI->getOperand(I); local 238 if (!MO.isReg() || !(Reg = MO.getReg())) 241 if (MO.isDef()) 243 else if (MO [all...] |
/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 144 const MCOperand &MO = MI->getOperand(opNum); local 145 if (MO.isImm()) { 146 uint64_t Imm = MO.getImm(); 196 const MCOperand& MO = MI->getOperand(opNum); local 197 O << MipsFCCToString((Mips::CondCode)MO.getImm());
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/external/llvm/lib/Target/Mips/ |
H A D | MipsMCInstLower.cpp | 36 MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, argument 44 switch(MO.getTargetFlags()) { 124 Symbol = MO.getMBB()->getSymbol(); 128 Symbol = AsmPrinter.getSymbol(MO.getGlobal()); 129 Offset += MO.getOffset(); 133 Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()); 134 Offset += MO.getOffset(); 138 Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName()); 139 Offset += MO.getOffset(); 143 Symbol = MO 178 LowerOperand(const MachineOperand &MO, unsigned offset) const argument 235 const MachineOperand &MO = MI->getOperand(I); local 274 const MachineOperand &MO = MI->getOperand(i); local [all...] |
/external/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.cpp | 94 const MCOperand &MO = MI->getOperand(OpNum); local 95 int64_t Imm = MO.getImm(); 144 const MCOperand &MO = MI->getOperand(OpNum); local 145 int64_t Imm = MO.getImm(); 218 const MCOperand &MO = MI->getOperand(OpNum); local 219 int Imm = (int) MO.getImm();
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 96 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 156 const MCOperand &MO = MI.getOperand(OpNo); local 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 160 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 168 const MCOperand &MO = MI.getOperand(OpNo); local 169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixup 181 const MCOperand &MO = MI.getOperand(OpNo); local 194 const MCOperand &MO = MI.getOperand(OpNo); local 206 const MCOperand &MO = MI.getOperand(OpNo); local 223 const MCOperand &MO = MI.getOperand(OpNo); local 242 const MCOperand &MO = MI.getOperand(OpNo); local 260 const MCOperand &MO = MI.getOperand(OpNo); local 275 const MCOperand &MO = MI.getOperand(OpNo); local 291 const MCOperand &MO = MI.getOperand(OpNo); local 307 const MCOperand &MO = MI.getOperand(OpNo); local 317 const MCOperand &MO = MI.getOperand(OpNo); local 336 const MCOperand &MO = MI.getOperand(OpNo+1); local 346 const MCOperand &MO = MI.getOperand(OpNo); local 355 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 379 MachineMemOperand *MO = *MI->memoperands_begin(); local 380 if (isLoadOfStoredAddress(MO->getSize(), 381 MO->getOffset(), MO->getValue())) 406 MachineMemOperand *MO = *MI->memoperands_begin(); local 407 StoreSize[NumStores] = MO->getSize(); 408 StoreOffset[NumStores] = MO->getOffset(); 409 StoreValue[NumStores] = MO->getValue();
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 57 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 105 const MCOperand &MO = MI.getOperand(tlsOpNo); local 106 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); 116 getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument 120 if (MO.isReg()) 121 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 123 if (MO.isImm()) 124 return MO.getImm(); 126 assert(MO.isExpr()); 127 const MCExpr *Expr = MO 146 const MCOperand &MO = MI.getOperand(OpNo); local 181 const MCOperand &MO = MI.getOperand(OpNo); local 194 const MCOperand &MO = MI.getOperand(OpNo); local 206 const MCOperand &MO = MI.getOperand(OpNo); local [all...] |
/external/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.cpp | 40 void SystemZInstPrinter::printOperand(const MCOperand &MO, const MCAsmInfo *MAI, argument 42 if (MO.isReg()) 43 O << '%' << getRegisterName(MO.getReg()); 44 else if (MO.isImm()) 45 O << MO.getImm(); 46 else if (MO.isExpr()) 47 MO.getExpr()->print(O, MAI); 146 const MCOperand &MO = MI->getOperand(OpNum); 147 if (MO.isImm()) { 149 O.write_hex(MO [all...] |
/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 51 // MO in MI. Fixups is the list of fixups against MI. 52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 137 getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument 140 if (MO.isReg()) 141 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 142 if (MO.isImm()) 143 return static_cast<uint64_t>(MO.getImm()); 217 const MCOperand &MO = MI.getOperand(OpNum); local 219 if (MO.isImm()) 220 Expr = MCConstantExpr::create(MO [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 178 MachineOperand &MO = MBBI->getOperand(i); local 179 if (!MO.isReg() || MO.isDef()) 181 unsigned Reg = MO.getReg(); 217 for (const MachineOperand &MO : MI.operands()) { 218 if (!MO.isReg()) 220 unsigned Reg = MO.getReg(); 227 if (!MO.isDef()) 2404 const MachineOperand &MO = MI.getOperand(0); 2407 if (!MO [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | LiveVariables.h | 225 MachineOperand &MO = MI->getOperand(i); local 226 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { 227 MO.setIsKill(false); 261 MachineOperand &MO = MI->getOperand(i); local 262 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) { 263 MO [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | ProcessImplicitDefs.cpp | 122 MachineOperand &MO = MI->getOperand(1); local 123 if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) { 124 if (MO.isKill()) { 125 LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg()); 142 MachineOperand& MO = MI->getOperand(i); local 143 if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO 190 MachineOperand& MO = MI->getOperand(i); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPURegisterInfo.cpp | 282 MachineOperand &MO = MI.getOperand(OpNo); local 285 Offset += MO.getImm() + MFI->getStackSize() + SPUFrameLowering::minStackSize(); 308 MO.ChangeToImmediate(Offset);
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
H A D | MBlazeMCCodeEmitter.cpp | 50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; 55 static unsigned GetMBlazeRegNum(const MCOperand &MO) { argument 109 const MCOperand &MO) const { 110 if (MO.isReg()) 111 return getMBlazeRegisterNumbering(MO.getReg()); 112 else if (MO.isImm()) 113 return static_cast<unsigned>(MO.getImm()); 114 else if (MO.isExpr()) 118 errs() << MO;
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 198 const MachineOperand &MO = candidate->getOperand(i); local 201 if (!MO.isReg() || !(Reg = MO.getReg())) 204 if (MO.isDef()) { 209 if (MO.isUse()) { 232 const MachineOperand &MO = MI->getOperand(i); local 235 if (!MO.isReg() || !(Reg = MO.getReg())) 238 if (MO.isDef()) 240 else if (MO [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 56 MachineRelocation GetRelocation(const MachineOperand &MO, 61 const MachineOperand &MO) const; 140 const MachineOperand &MO = MI.getOperand(OpNo); local 142 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 143 return 0x80 >> getPPCRegisterNumbering(MO.getReg()); 146 MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO, argument 159 if (MO.isGlobal()) 161 const_cast<GlobalValue *>(MO.getGlobal()), 162 Cst, isa<Function>(MO 181 const MachineOperand &MO = MI.getOperand(OpNo); local 190 const MachineOperand &MO = MI.getOperand(OpNo); local 197 const MachineOperand &MO = MI.getOperand(OpNo); local 206 const MachineOperand &MO = MI.getOperand(OpNo); local 220 const MachineOperand &MO = MI.getOperand(OpNo); local 236 const MachineOperand &MO = MI.getOperand(OpNo); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 212 const MachineOperand &MO = candidate->getOperand(i); local 213 if (!MO.isReg()) 216 unsigned Reg = MO.getReg(); 218 if (MO.isDef()) { 223 if (MO.isUse()) { 264 const MachineOperand &MO = MI->getOperand(i); local 265 if (!MO.isReg()) 268 unsigned Reg = MO.getReg(); 271 if (MO.isDef()) 273 if (MO 318 const MachineOperand &MO = I->getOperand(structSizeOpNum); local [all...] |
H A D | SparcAsmPrinter.cpp | 73 const MachineOperand &MO = MI->getOperand (opNum); local 75 if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) { 79 !MO.isReg() && !MO.isImm()) { 83 switch (MO.getType()) { 85 O << "%" << LowercaseString(getRegisterName(MO.getReg())); 89 O << (int)MO.getImm(); 92 O << *MO.getMBB()->getSymbol(); 95 O << *Mang->getSymbol(MO 142 const MachineOperand &MO = MI->getOperand(opNum); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 118 MachineOperand &MO = MBBI->getOperand(i); local 119 if (!MO.isReg() || MO.isDef()) 121 unsigned Reg = MO.getReg();
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