Searched defs:OpInfo (Results 26 - 28 of 28) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3471 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; local
3474 TLI->ComputeConstraintToUse(OpInfo, SDValue());
3478 if (OpInfo.CallOperandVal == OpVal &&
3479 (OpInfo.ConstraintType != TargetLowering::C_Memory ||
3480 !OpInfo.isIndirect))
4058 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; local
4061 TLI->ComputeConstraintToUse(OpInfo, SDValue());
4063 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4064 OpInfo.isIndirect) {
4067 } else if (OpInfo
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/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1723 const MCOperandInfo &OpInfo = MCID.OpInfo[i]; local
1724 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
1725 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
1757 const MCOperandInfo &OpInfo = MCID.OpInfo[i]; local
1758 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
1759 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
2649 int16_t DstRegClass = Desc.OpInfo[0].RegClass;
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp5686 /// OpInfo describes the operand.
5692 SDISelAsmOperandInfo &OpInfo,
5701 switch (OpInfo.Type) {
5707 isInReg = OpInfo.hasMatchingInput();
5726 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5727 OpInfo.ConstraintVT);
5730 if (OpInfo.ConstraintVT != MVT::Other) {
5734 if (OpInfo.Type == InlineAsm::isInput &&
5735 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5740 if (RegVT.getSizeInBits() == OpInfo
5689 GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI, DebugLoc DL, SDISelAsmOperandInfo &OpInfo, std::set<unsigned> &OutputRegs, std::set<unsigned> &InputRegs) argument
5836 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); local
5909 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; local
5995 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; local
6034 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; local
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