Searched defs:imm (Results 1 - 20 of 20) sorted by relevance

/art/compiler/utils/arm/
H A Dassembler_arm_vixl.h140 void Vmov(vixl32::DRegister rd, double imm) { argument
141 if (vixl::VFP::IsImmFP64(imm)) {
142 MacroAssembler::Vmov(rd, imm);
144 MacroAssembler::Vldr(rd, imm);
H A Djni_macro_assembler_arm.cc278 uint32_t imm,
282 __ LoadImmediate(scratch.AsCoreRegister(), imm);
277 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) argument
H A Djni_macro_assembler_arm_vixl.cc260 uint32_t imm,
266 asm_.LoadImmediate(mscratch.AsVIXLRegister(), imm);
259 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) argument
H A Dassembler_thumb2.cc1384 uint32_t imm = so.GetImmediate(); local
1386 uint32_t i = (imm >> 11) & 1;
1387 uint32_t imm3 = (imm >> 8) & 7U /* 0b111 */;
1388 uint32_t imm8 = imm & 0xff;
1400 uint32_t imm = ModifiedImmediate(so.encodingThumb()); local
1401 if (imm == kInvalidModifiedImmediate) {
1410 imm;
1672 // ADD sp, sp, #imm
1686 // ADD rd, SP, #imm
1732 // SUB sp, sp, #imm
2747 ldrex(Register rt, Register rn, uint16_t imm, Condition cond) argument
2767 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument
[all...]
/art/compiler/optimizing/
H A Dscheduler_arm64.cc84 int64_t imm = Int64FromConstant(instr->GetRight()->AsConstant()); local
85 if (imm == 0) {
88 } else if (imm == 1 || imm == -1) {
91 } else if (IsPowerOfTwo(AbsOrMin(imm))) {
95 DCHECK(imm <= -2 || imm >= 2);
152 int64_t imm = Int64FromConstant(instruction->GetRight()->AsConstant()); local
153 if (imm == 0) {
156 } else if (imm
[all...]
H A Dcode_generator_arm64.cc3288 int64_t imm = Int64FromConstant(second.GetConstant()); local
3289 DCHECK(imm == 1 || imm == -1);
3294 if (imm == 1) {
3311 int64_t imm = Int64FromConstant(second.GetConstant()); local
3312 uint64_t abs_imm = static_cast<uint64_t>(AbsOrMin(imm));
3322 if (imm > 0) {
3346 int64_t imm = Int64FromConstant(second.GetConstant()); local
3353 CalculateMagicAndShiftForDivRem(imm, type == Primitive::kPrimLong /* is_long */, &magic, &shift);
3367 if (imm >
3398 int64_t imm = Int64FromConstant(second.GetConstant()); local
[all...]
H A Dcode_generator_arm.cc4041 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
4042 DCHECK(imm == 1 || imm == -1);
4047 if (imm == 1) {
4066 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
4067 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm));
4080 if (imm < 0) {
4101 int64_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
4105 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift);
4110 if (imm >
4138 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
[all...]
H A Dcode_generator_arm_vixl.cc4034 int32_t imm = Int32ConstantFrom(second); local
4035 DCHECK(imm == 1 || imm == -1);
4040 if (imm == 1) {
4059 int32_t imm = Int32ConstantFrom(second); local
4060 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm));
4073 if (imm < 0) {
4094 int32_t imm = Int32ConstantFrom(second); local
4098 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift);
4104 if (imm >
4132 int32_t imm = Int32ConstantFrom(second); local
[all...]
H A Dcode_generator_x86.cc3233 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue());
3234 __ imull(out.AsRegister<Register>(), first.AsRegister<Register>(), imm);
3475 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local
3477 DCHECK(imm == 1 || imm == -1);
3483 if (imm == -1) {
3495 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local
3496 DCHECK(IsPowerOfTwo(AbsOrMin(imm)));
3497 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm));
3504 int shift = CTZ(imm);
3518 int imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local
3596 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
5890 __ movl(Address(ESP, destination.GetStackIndex()), imm); local
[all...]
H A Dcode_generator_x86_64.cc3219 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue());
3220 __ subl(first.AsRegister<CpuRegister>(), imm);
3322 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue());
3323 __ imull(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>(), imm);
3480 int64_t imm = Int64FromConstant(second.GetConstant()); local
3482 DCHECK(imm == 1 || imm == -1);
3490 if (imm == -1) {
3502 if (imm == -1) {
3521 int64_t imm local
3584 int imm = second.GetConstant()->AsIntConstant()->GetValue(); local
3616 int64_t imm = second.GetConstant()->AsLongConstant()->GetValue(); local
3684 int64_t imm = Int64FromConstant(second.GetConstant()); local
[all...]
/art/compiler/linker/arm/
H A Drelative_patcher_thumb2.cc80 uint32_t imm = (diff16 >> 11) & 0x1u; local
83 insn = (insn & 0xfbf08f00u) | (imm << 26) | (imm4 << 16) | (imm3 << 12) | imm8;
/art/compiler/utils/mips64/
H A Dassembler_mips64_test.cc652 DriverStr(RepeatFRIb(&mips64::Mips64Assembler::Lwc1, -16, "lwc1 ${reg1}, {imm}(${reg2})"),
657 DriverStr(RepeatFRIb(&mips64::Mips64Assembler::Ldc1, -16, "ldc1 ${reg1}, {imm}(${reg2})"),
662 DriverStr(RepeatFRIb(&mips64::Mips64Assembler::Swc1, -16, "swc1 ${reg1}, {imm}(${reg2})"),
667 DriverStr(RepeatFRIb(&mips64::Mips64Assembler::Sdc1, -16, "sdc1 ${reg1}, {imm}(${reg2})"),
933 // hence the sign extension from bit 18 with `imm - ((imm & 0x40000) << 1)`.
936 // We capture the value of the immediate with `.set imm, {imm}` because the value is needed
937 // twice for the sign extension, but `{imm}` is substituted only once.
938 const char* code = ".set imm, {im
1332 expected << "daui $" << *reg1 << ", $" << *reg2 << ", " << imm << "\\n"; local
[all...]
H A Dassembler_mips64.cc139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { argument
145 imm;
178 void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) { argument
183 imm;
2891 void Mips64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
2895 LoadConst32(scratch.AsGpuRegister(), imm);
/art/compiler/utils/x86/
H A Djni_macro_assembler_x86.cc162 void X86JNIMacroAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister) { argument
163 __ movl(Address(ESP, dest), Immediate(imm));
H A Dassembler_x86.cc81 void X86Assembler::pushl(const Immediate& imm) { argument
83 if (imm.is_int8()) {
85 EmitUint8(imm.value() & 0xFF);
88 EmitImmediate(imm);
106 void X86Assembler::movl(Register dst, const Immediate& imm) { argument
109 EmitImmediate(imm);
134 void X86Assembler::movl(const Address& dst, const Immediate& imm) { argument
138 EmitImmediate(imm);
249 void X86Assembler::movb(const Address& dst, const Immediate& imm) { argument
253 CHECK(imm
303 movw(const Address& dst, const Immediate& imm) argument
1046 roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1057 roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1316 shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1326 shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1335 pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1615 cmpb(const Address& address, const Immediate& imm) argument
1623 cmpw(const Address& address, const Immediate& imm) argument
1630 cmpl(Register reg, const Immediate& imm) argument
1671 cmpl(const Address& address, const Immediate& imm) argument
1716 testb(const Address& dst, const Immediate& imm) argument
1725 testl(const Address& dst, const Immediate& imm) argument
1747 andl(Register dst, const Immediate& imm) argument
1767 orl(Register dst, const Immediate& imm) argument
1787 xorl(Register dst, const Immediate& imm) argument
1793 addl(Register reg, const Immediate& imm) argument
1806 addl(const Address& address, const Immediate& imm) argument
1812 adcl(Register reg, const Immediate& imm) argument
1839 subl(Register reg, const Immediate& imm) argument
1880 imull(Register dst, Register src, const Immediate& imm) argument
1898 imull(Register reg, const Immediate& imm) argument
1946 sbbl(Register reg, const Immediate& imm) argument
1992 shll(Register reg, const Immediate& imm) argument
2002 shll(const Address& address, const Immediate& imm) argument
2012 shrl(Register reg, const Immediate& imm) argument
2022 shrl(const Address& address, const Immediate& imm) argument
2032 sarl(Register reg, const Immediate& imm) argument
2042 sarl(const Address& address, const Immediate& imm) argument
2061 shld(Register dst, Register src, const Immediate& imm) argument
2079 shrd(Register dst, Register src, const Immediate& imm) argument
2088 roll(Register reg, const Immediate& imm) argument
2098 rorl(Register reg, const Immediate& imm) argument
2122 enter(const Immediate& imm) argument
2144 ret(const Immediate& imm) argument
2372 AddImmediate(Register reg, const Immediate& imm) argument
2463 EmitImmediate(const Immediate& imm) argument
2524 EmitGenericShift(int reg_or_opcode, const Operand& operand, const Immediate& imm) argument
[all...]
/art/compiler/utils/x86_64/
H A Djni_macro_assembler_x86_64.cc200 uint32_t imm,
202 __ movl(Address(CpuRegister(RSP), dest), Immediate(imm)); // TODO(64) movq?
199 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister) argument
H A Dassembler_x86_64.cc78 void X86_64Assembler::pushq(const Immediate& imm) { argument
80 CHECK(imm.is_int32()); // pushq only supports 32b immediate.
81 if (imm.is_int8()) {
83 EmitUint8(imm.value() & 0xFF);
86 EmitImmediate(imm);
106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { argument
108 if (imm.is_int32()) {
113 EmitInt32(static_cast<int32_t>(imm.value()));
117 EmitInt64(imm.value());
122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { argument
131 movq(const Address& dst, const Immediate& imm) argument
189 movl(const Address& dst, const Immediate& imm) argument
292 movb(const Address& dst, const Immediate& imm) argument
352 movw(const Address& dst, const Immediate& imm) argument
1251 roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1263 roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1522 shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1533 shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1543 pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1863 cmpb(const Address& address, const Immediate& imm) argument
1873 cmpw(const Address& address, const Immediate& imm) argument
1882 cmpl(CpuRegister reg, const Immediate& imm) argument
1914 cmpl(const Address& address, const Immediate& imm) argument
1930 cmpq(CpuRegister reg, const Immediate& imm) argument
1946 cmpq(const Address& address, const Immediate& imm) argument
2028 testb(const Address& dst, const Immediate& imm) argument
2038 testl(const Address& dst, const Immediate& imm) argument
2063 andl(CpuRegister dst, const Immediate& imm) argument
2070 andq(CpuRegister reg, const Immediate& imm) argument
2110 orl(CpuRegister dst, const Immediate& imm) argument
2117 orq(CpuRegister dst, const Immediate& imm) argument
2157 xorl(CpuRegister dst, const Immediate& imm) argument
2172 xorq(CpuRegister dst, const Immediate& imm) argument
2240 addl(CpuRegister reg, const Immediate& imm) argument
2247 addq(CpuRegister reg, const Immediate& imm) argument
2280 addl(const Address& address, const Immediate& imm) argument
2295 subl(CpuRegister reg, const Immediate& imm) argument
2302 subq(CpuRegister reg, const Immediate& imm) argument
2371 imull(CpuRegister dst, CpuRegister src, const Immediate& imm) argument
2393 imull(CpuRegister reg, const Immediate& imm) argument
2416 imulq(CpuRegister reg, const Immediate& imm) argument
2420 imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) argument
2490 shll(CpuRegister reg, const Immediate& imm) argument
2495 shlq(CpuRegister reg, const Immediate& imm) argument
2510 shrl(CpuRegister reg, const Immediate& imm) argument
2515 shrq(CpuRegister reg, const Immediate& imm) argument
2530 sarl(CpuRegister reg, const Immediate& imm) argument
2540 sarq(CpuRegister reg, const Immediate& imm) argument
2550 roll(CpuRegister reg, const Immediate& imm) argument
2560 rorl(CpuRegister reg, const Immediate& imm) argument
2570 rolq(CpuRegister reg, const Immediate& imm) argument
2580 rorq(CpuRegister reg, const Immediate& imm) argument
2622 enter(const Immediate& imm) argument
2644 ret(const Immediate& imm) argument
2827 AddImmediate(CpuRegister reg, const Immediate& imm) argument
3066 EmitImmediate(const Immediate& imm) argument
3131 EmitGenericShift(bool wide, int reg_or_opcode, CpuRegister reg, const Immediate& imm) argument
[all...]
/art/compiler/utils/arm64/
H A Djni_macro_assembler_arm64.cc159 uint32_t imm,
163 LoadImmediate(scratch.AsXRegister(), imm);
158 StoreImmediateToFrame(FrameOffset offs, uint32_t imm, ManagedRegister m_scratch) argument
/art/compiler/utils/
H A Dassembler_test.h159 for (int64_t imm : imms) {
160 ImmType new_imm = CreateImmediate(imm);
179 sreg << imm * multiplier + bias;
213 for (int64_t imm : imms) {
214 ImmType new_imm = CreateImmediate(imm);
239 sreg << imm + bias;
272 for (int64_t imm : imms) {
273 ImmType new_imm = CreateImmediate(imm);
292 sreg << imm; local
320 for (int64_t imm
530 sreg << imm; local
1013 sreg << imm; local
1108 sreg << imm; local
[all...]
/art/compiler/utils/mips/
H A Dassembler_mips.cc350 uint32_t MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument
356 imm;
397 uint32_t MipsAssembler::EmitFI(int opcode, int fmt, FRegister ft, uint16_t imm) { argument
402 imm;
3446 void MipsAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, argument
3450 LoadConst32(scratch.AsCoreRegister(), imm);

Completed in 312 milliseconds