Searched defs:lane (Results 1 - 13 of 13) sorted by relevance

/external/v8/src/compiler/
H A Dsimd-scalar-lowering.cc256 int32_t lane = OpParameter<int32_t>(laneNode); local
258 GetReplacementsWithType(node->InputAt(0), rep_type)[lane], nullptr,
290 int32_t lane = OpParameter<int32_t>(laneNode); local
292 GetReplacementsWithType(node->InputAt(0), rep_type)[lane], nullptr,
H A Dwasm-compiler.cc3124 Node* WasmGraphBuilder::SimdExtractLane(wasm::WasmOpcode opcode, uint8_t lane, argument
3129 Int32Constant(lane));
3132 input, Int32Constant(lane));
/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_emit_nv50.cpp120 void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
779 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) argument
781 code[0] = 0xc0000000 | (lane << 16);
/external/vixl/src/aarch64/
H A Dsimulator-aarch64.h307 // unchanged. The lane parameter indicates where in the register the value
311 void Insert(int lane, T new_value) { argument
312 VIXL_ASSERT(lane >= 0);
313 VIXL_ASSERT((sizeof(new_value) + (lane * sizeof(new_value))) <=
315 memcpy(&value_[lane * sizeof(new_value)], &new_value, sizeof(new_value));
325 // Get the lane value as the specified type. The value is truncated if
328 T GetLane(int lane) const {
330 VIXL_ASSERT(lane >= 0);
331 VIXL_ASSERT((sizeof(result) + (lane * sizeof(result))) <= kSizeInBytes);
332 memcpy(&result, &value_[lane * sizeo
[all...]
H A Dassembler-aarch64.cc1599 int lane,
1604 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad2);
1632 int lane,
1637 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad3);
1668 int lane,
1673 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad4);
1739 int lane,
1744 LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore2);
1762 int lane,
1767 LoadStoreStructSingle(vt, lane, ds
1597 ld2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& src) argument
1629 ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) argument
1664 ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) argument
1737 st2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& dst) argument
1759 st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) argument
1783 st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) argument
1796 LoadStoreStructSingle(const VRegister& vt, uint32_t lane, const MemOperand& addr, NEONLoadStoreSingleStructOp op) argument
[all...]
H A Dsimulator-aarch64.cc783 for (int lane = leftmost_lane; lane >= rightmost_lane; lane--) {
785 ? ReadVRegister(code).GetLane<float>(lane)
786 : ReadVRegister(code).GetLane<double>(lane);
899 unsigned lane) {
908 lane);
939 unsigned lane) {
951 PrintVRegisterRawHelper(reg_code, reg_size, lane_size * lane);
953 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane);
896 PrintVRead(uintptr_t address, unsigned reg_code, PrintRegisterFormat format, unsigned lane) argument
936 PrintVWrite(uintptr_t address, unsigned reg_code, PrintRegisterFormat format, unsigned lane) argument
4223 int lane = instr->GetNEONLSIndex(index_shift); local
[all...]
H A Dmacro-assembler-aarch64.h2538 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { argument
2541 ld1(vt, lane, src);
2555 int lane,
2559 ld2(vt, vt2, lane, src);
2577 int lane,
2581 ld3(vt, vt2, vt3, lane, src);
2604 int lane,
2608 ld4(vt, vt2, vt3, vt4, lane, src);
2707 void St1(const VRegister& vt, int lane, const MemOperand& dst) { argument
2710 st1(vt, lane, ds
2553 Ld2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& src) argument
2574 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) argument
2600 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) argument
2734 St2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& dst) argument
2742 St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) argument
2751 St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) argument
[all...]
/external/v8/src/wasm/
H A Dast-decoder.cc154 uint8_t lane; member in struct:v8::internal::wasm::LaneOperand
158 lane = decoder->checked_read_u8(pc, 2, "lane");
259 if (operand.lane < 0 || operand.lane > 3) {
260 error(pc_, pc_ + 2, "invalid extract lane value");
1332 TFNode* node = BUILD(SimdExtractLane, opcode, operand.lane, input);
/external/vixl/src/aarch32/
H A Dassembler-aarch32.cc555 explicit Dt_U_opc1_opc2_1(DataType dt, const DRegisterLane& lane);
558 Dt_U_opc1_opc2_1::Dt_U_opc1_opc2_1(DataType dt, const DRegisterLane& lane) { argument
561 if ((lane.GetLane() & 7) != lane.GetLane()) {
564 SetEncodingValue(0x8 | lane.GetLane());
567 if ((lane.GetLane() & 3) != lane.GetLane()) {
570 SetEncodingValue(0x1 | (lane.GetLane() << 1));
573 if ((lane.GetLane() & 7) != lane
606 Dt_opc1_opc2_1(DataType dt, const DRegisterLane& lane) argument
642 Dt_imm4_1(DataType dt, const DRegisterLane& lane) argument
[all...]
H A Ddisasm-aarch32.cc73 DecodeNeon(int lane, SpacingType spacing) argument
74 : lane_(lane), spacing_(spacing), valid_(true) {}
327 DataTypeValue Dt_U_opc1_opc2_1_Decode(uint32_t value, unsigned* lane) { argument
329 *lane = value & 7;
333 *lane = (value >> 1) & 3;
337 *lane = value & 7;
341 *lane = (value >> 1) & 3;
345 *lane = (value >> 2) & 1;
348 *lane = -1;
352 DataTypeValue Dt_opc1_opc2_1_Decode(uint32_t value, unsigned* lane) { argument
369 Dt_imm4_1_Decode(uint32_t value, unsigned* lane) argument
829 int lane = (value >> 1) & 0x7; local
835 int lane = (value >> 2) & 0x3; local
841 int lane = (value >> 3) & 0x1; local
861 int lane = (value >> 1) & 0x7; local
874 int lane = (value >> 2) & 0x3; local
887 int lane = (value >> 3) & 0x1; local
908 int lane = (value >> 1) & 0x7; local
921 int lane = (value >> 2) & 0x3; local
934 int lane = (value >> 3) & 0x1; local
955 int lane = (value >> 1) & 0x7; local
968 int lane = (value >> 2) & 0x3; local
983 int lane = (value >> 3) & 0x1; local
14929 int lane = decode_neon.GetLane(); local
14943 lane), local
14971 int lane = decode_neon.GetLane(); local
14985 lane), local
15015 int lane = decode_neon.GetLane(); local
15030 lane), local
15078 int lane = decode_neon.GetLane(); local
15095 lane), local
15123 int lane = decode_neon.GetLane(); local
15140 lane), local
15170 int lane = decode_neon.GetLane(); local
15188 lane), local
15287 int lane = decode_neon.GetLane(); local
15304 lane), local
15331 int lane = decode_neon.GetLane(); local
15348 lane), local
15377 int lane = decode_neon.GetLane(); local
15396 lane), local
15444 int lane = decode_neon.GetLane(); local
15461 lane), local
15489 int lane = decode_neon.GetLane(); local
15506 lane), local
15536 int lane = decode_neon.GetLane(); local
15554 lane), local
15754 int lane = decode_neon.GetLane(); local
15768 lane), local
15796 int lane = decode_neon.GetLane(); local
15810 lane), local
15840 int lane = decode_neon.GetLane(); local
15855 lane), local
16064 int lane = decode_neon.GetLane(); local
16081 lane), local
16109 int lane = decode_neon.GetLane(); local
16126 lane), local
16156 int lane = decode_neon.GetLane(); local
16174 lane), local
16367 int lane = decode_neon.GetLane(); local
16384 lane), local
16407 int lane = decode_neon.GetLane(); local
16424 lane), local
16449 int lane = decode_neon.GetLane(); local
16468 lane), local
16681 int lane = decode_neon.GetLane(); local
16698 lane), local
16726 int lane = decode_neon.GetLane(); local
16743 lane), local
16773 int lane = decode_neon.GetLane(); local
16791 lane), local
25018 unsigned lane; local
25193 unsigned lane; local
28667 unsigned lane; local
28693 unsigned lane; local
28880 int lane; local
28920 int lane; local
28963 int lane; local
29258 int lane; local
29298 int lane; local
29341 int lane; local
29678 int lane; local
29787 int lane; local
29815 int lane; local
29851 int lane; local
29887 int lane; local
42859 unsigned lane; local
42881 unsigned lane; local
43057 int lane; local
43090 int lane; local
43126 int lane; local
43394 int lane; local
43427 int lane; local
43463 int lane; local
43775 int lane; local
43878 int lane; local
43902 int lane; local
43934 int lane; local
43966 int lane; local
51614 int lane = decode_neon.GetLane(); local
51654 int lane = decode_neon.GetLane(); local
51695 int lane = decode_neon.GetLane(); local
51755 int lane = decode_neon.GetLane(); local
51797 int lane = decode_neon.GetLane(); local
51840 int lane = decode_neon.GetLane(); local
51953 int lane = decode_neon.GetLane(); local
51994 int lane = decode_neon.GetLane(); local
52037 int lane = decode_neon.GetLane(); local
52100 int lane = decode_neon.GetLane(); local
52142 int lane = decode_neon.GetLane(); local
52185 int lane = decode_neon.GetLane(); local
54195 int lane = decode_neon.GetLane(); local
54235 int lane = decode_neon.GetLane(); local
54276 int lane = decode_neon.GetLane(); local
54490 int lane = decode_neon.GetLane(); local
54532 int lane = decode_neon.GetLane(); local
54575 int lane = decode_neon.GetLane(); local
54777 int lane = decode_neon.GetLane(); local
54814 int lane = decode_neon.GetLane(); local
54853 int lane = decode_neon.GetLane(); local
55076 int lane = decode_neon.GetLane(); local
55118 int lane = decode_neon.GetLane(); local
55161 int lane = decode_neon.GetLane(); local
67472 unsigned lane; local
67674 unsigned lane; local
[all...]
/external/valgrind/VEX/priv/
H A Dguest_x86_toIR.c513 least significant lane (rightmost in the register). */
7056 /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
7091 /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
7165 /* Lowest 32-bit lane only unary SSE operation, G = op(E). */
7208 /* Lowest 64-bit lane only unary SSE operation, G = op(E). */
7788 values (aa,bb), computes, for each lane:
7827 value aa, computes, for each lane
8531 assign( argR, getXMMRegLane32F( eregOfRM(modrm), 0/*lowest lane*/ ) );
8542 assign( argL, getXMMRegLane32F( gregOfRM(modrm), 0/*lowest lane*/ ) );
8874 put it into the specified lane o
8879 Int lane; local
10969 Int lane; local
10990 putXMMRegLane16( gregOfRM(modrm), lane & 7, mkexpr(t4) ); local
[all...]
H A Dguest_amd64_toIR.c1416 least significant lane (rightmost in the register). */
8845 /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
8881 /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
8957 /* Lowest 32-bit lane only unary SSE operation, G = op(E). */
9001 /* Lowest 64-bit lane only unary SSE operation, G = op(E). */
9684 values (aa,bb), computes, for each lane:
9724 value aa, computes, for each lane
10062 0/*lowest lane*/ ) );
10078 0/*lowest lane*/ ) );
10105 0/*lowest lane*/ ) );
14234 Int lane; local
14275 Int lane; local
27755 IRExpr* lane = (laneIs32 ? getYMMRegLane32 : getYMMRegLane64)( rV, i ); local
[all...]
H A Dguest_arm64_toIR.c1408 /* Find the offset of the laneNo'th lane of type laneTy in the given
1409 Qreg. Since the host is little-endian, the least significant lane
1415 /* Since the host is little-endian, the least significant lane
1435 /* Put to the least significant lane of a Qreg. */
1450 /* Get from the least significant lane of a Qreg. */
1535 /* Put to a specified lane of a Qreg. */
1552 /* Get from a specified lane of a Qreg. */
3829 // First, interleave at the 64-bit lane size.
3844 // First, interleave at the 32-bit lane size.
3859 // First, interleave at the 16-bit lane siz
8740 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8); local
8747 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8); local
8754 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16); local
8761 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16); local
8768 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32); local
8775 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32); local
8782 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I64); local
[all...]

Completed in 2066 milliseconds