| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 29 lsl, enumerator in enum:llvm::ARM_AM::ShiftOpc
48 case ARM_AM::lsl: return "lsl";
59 case ARM_AM::lsl: return 0;
104 // reg [asr|lsl|lsr|ror|rrx] reg
105 // reg [asr|lsl|lsr|ror|rrx] imm
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 30 lsl, enumerator in enum:llvm::ARM_AM::ShiftOpc
49 case ARM_AM::lsl: return "lsl";
60 case ARM_AM::lsl: return 0;
105 // reg [asr|lsl|lsr|ror|rrx] reg
106 // reg [asr|lsl|lsr|ror|rrx] imm
|
| /external/v8/src/arm64/ |
| H A D | assembler-arm64.h | 1192 void lsl(const Register& rd, const Register& rn, int shift) { function in class:v8::internal::Assembler
|
| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 766 void lsl(const Register& rd, const Register& rn, unsigned shift) { function in class:vixl::aarch64::Assembler
|
| /external/vixl/src/aarch32/ |
| H A D | assembler-aarch32.cc | 6083 void Assembler::lsl(Condition cond, function in class:vixl::aarch32::Assembler
6142 Delegate(kLsl, &Assembler::lsl, cond, size, rd, rm, operand);
|
| H A D | assembler-aarch32.h | 2470 void lsl(Condition cond,
2475 void lsl(Register rd, Register rm, const Operand& operand) { function in class:vixl::aarch32::Assembler
2476 lsl(al, Best, rd, rm, operand);
2478 void lsl(Condition cond, Register rd, Register rm, const Operand& operand) { function in class:vixl::aarch32::Assembler
2479 lsl(cond, Best, rd, rm, operand);
2481 void lsl(EncodingSize size, function in class:vixl::aarch32::Assembler
2485 lsl(al, size, rd, rm, operand);
|
| H A D | disasm-aarch32.cc | 1829 void Disassembler::lsl(Condition cond, function in class:vixl::aarch32::Disassembler
7171 lsl(CurrentCond(), Best, Register(rd), Register(rm), amount);
7357 lsl(CurrentCond(),
18266 lsl(CurrentCond(),
18276 lsl(CurrentCond(),
20488 lsl(CurrentCond(),
20495 lsl(CurrentCond(),
[all...] |