1// Copyright 2015, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27#ifndef VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 28#define VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 29 30#include "assembler-base-vixl.h" 31 32#include "aarch32/instructions-aarch32.h" 33#include "aarch32/label-aarch32.h" 34 35namespace vixl { 36namespace aarch32 { 37 38class Assembler : public internal::AssemblerBase { 39 InstructionSet isa_; 40 Condition first_condition_; 41 uint16_t it_mask_; 42 bool has_32_dregs_; 43 bool allow_unpredictable_; 44 bool allow_strongly_discouraged_; 45 46 protected: 47 void EmitT32_16(uint16_t instr); 48 void EmitT32_32(uint32_t instr); 49 void EmitA32(uint32_t instr); 50 // Check that the condition of the current instruction is consistent with the 51 // IT state. 52 void CheckIT(Condition condition) { 53#ifdef VIXL_DEBUG 54 PerformCheckIT(condition); 55#else 56 USE(condition); 57#endif 58 } 59#ifdef VIXL_DEBUG 60 void PerformCheckIT(Condition condition); 61#endif 62 void AdvanceIT() { it_mask_ = (it_mask_ << 1) & 0xf; } 63 void BindHelper(Label* label); 64 void PlaceHelper(RawLiteral* literal) { 65 BindHelper(literal); 66 GetBuffer()->EmitData(literal->GetDataAddress(), literal->GetSize()); 67 } 68 uint32_t Link(uint32_t instr, 69 Label* label, 70 const Label::LabelEmitOperator& op); 71 72 public: 73 class AllowUnpredictableScope { 74 Assembler* assembler_; 75 bool old_; 76 77 public: 78 explicit AllowUnpredictableScope(Assembler* assembler) 79 : assembler_(assembler), old_(assembler->allow_unpredictable_) { 80 assembler_->allow_unpredictable_ = true; 81 } 82 ~AllowUnpredictableScope() { assembler_->allow_unpredictable_ = old_; } 83 }; 84 class AllowStronglyDiscouragedScope { 85 Assembler* assembler_; 86 bool old_; 87 88 public: 89 explicit AllowStronglyDiscouragedScope(Assembler* assembler) 90 : assembler_(assembler), old_(assembler->allow_strongly_discouraged_) { 91 assembler_->allow_strongly_discouraged_ = true; 92 } 93 ~AllowStronglyDiscouragedScope() { 94 assembler_->allow_strongly_discouraged_ = old_; 95 } 96 }; 97 98 explicit Assembler(InstructionSet isa = kDefaultISA) 99 : isa_(isa), 100 first_condition_(al), 101 it_mask_(0), 102 has_32_dregs_(true), 103 allow_unpredictable_(false), 104 allow_strongly_discouraged_(false) { 105#if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 106 // Avoid compiler warning. 107 USE(isa_); 108 VIXL_ASSERT(isa == A32); 109#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 110 USE(isa_); 111 VIXL_ASSERT(isa == T32); 112#endif 113 } 114 explicit Assembler(size_t capacity, InstructionSet isa = kDefaultISA) 115 : AssemblerBase(capacity), 116 isa_(isa), 117 first_condition_(al), 118 it_mask_(0), 119 has_32_dregs_(true), 120 allow_unpredictable_(false), 121 allow_strongly_discouraged_(false) { 122#if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 123 VIXL_ASSERT(isa == A32); 124#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 125 VIXL_ASSERT(isa == T32); 126#endif 127 } 128 Assembler(byte* buffer, size_t capacity, InstructionSet isa = kDefaultISA) 129 : AssemblerBase(buffer, capacity), 130 isa_(isa), 131 first_condition_(al), 132 it_mask_(0), 133 has_32_dregs_(true), 134 allow_unpredictable_(false), 135 allow_strongly_discouraged_(false) { 136#if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 137 VIXL_ASSERT(isa == A32); 138#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 139 VIXL_ASSERT(isa == T32); 140#endif 141 } 142 virtual ~Assembler() {} 143 144 void UseInstructionSet(InstructionSet isa) { 145#if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 146 USE(isa); 147 VIXL_ASSERT(isa == A32); 148#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 149 USE(isa); 150 VIXL_ASSERT(isa == T32); 151#else 152 VIXL_ASSERT((isa_ == isa) || (GetCursorOffset() == 0)); 153 isa_ = isa; 154#endif 155 } 156 157#if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 158 InstructionSet GetInstructionSetInUse() const { return A32; } 159#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 160 InstructionSet GetInstructionSetInUse() const { return T32; } 161#else 162 InstructionSet GetInstructionSetInUse() const { return isa_; } 163#endif 164 165 void UseT32() { UseInstructionSet(T32); } 166 void UseA32() { UseInstructionSet(A32); } 167 bool IsUsingT32() const { return GetInstructionSetInUse() == T32; } 168 bool IsUsingA32() const { return GetInstructionSetInUse() == A32; } 169 170 void SetIT(Condition first_condition, uint16_t it_mask) { 171 VIXL_ASSERT(it_mask_ == 0); 172 first_condition_ = first_condition; 173 it_mask_ = it_mask; 174 } 175 bool Is16BitEncoding(uint16_t instr) const { 176 VIXL_ASSERT(IsUsingT32()); 177 return instr < 0xe800; 178 } 179 bool InITBlock() { return it_mask_ != 0; } 180 bool OutsideITBlock() { return it_mask_ == 0; } 181 bool OutsideITBlockOrLast() { return (it_mask_ == 0) || (it_mask_ == 0x8); } 182 bool OutsideITBlockAndAlOrLast(Condition cond) { 183 return ((it_mask_ == 0) && cond.Is(al)) || (it_mask_ == 0x8); 184 } 185 void CheckNotIT() { VIXL_ASSERT(it_mask_ == 0); } 186 bool Has32DRegs() const { return has_32_dregs_; } 187 void SetHas32DRegs(bool has_32_dregs) { has_32_dregs_ = has_32_dregs; } 188 189 int32_t GetCursorOffset() const { 190 ptrdiff_t offset = buffer_.GetCursorOffset(); 191 VIXL_ASSERT(IsInt32(offset)); 192 return static_cast<int32_t>(offset); 193 } 194 195 uint32_t GetArchitectureStatePCOffset() const { return IsUsingT32() ? 4 : 8; } 196 void bind(Label* label) { 197 VIXL_ASSERT(AllowAssembler()); 198 BindHelper(label); 199 } 200 void place(RawLiteral* literal) { 201 VIXL_ASSERT(AllowAssembler()); 202 VIXL_ASSERT(literal->IsManuallyPlaced()); 203 PlaceHelper(literal); 204 } 205 206 size_t GetSizeOfCodeGeneratedSince(Label* label) const { 207 VIXL_ASSERT(label->IsBound()); 208 return buffer_.GetOffsetFrom(label->GetLocation()); 209 } 210 211 void EncodeLabelFor(const Label::ForwardReference& forward, Label* label); 212 213 // Helpers for it instruction. 214 void it(Condition cond) { it(cond, 0x8); } 215 void itt(Condition cond) { it(cond, 0x4); } 216 void ite(Condition cond) { it(cond, 0xc); } 217 void ittt(Condition cond) { it(cond, 0x2); } 218 void itet(Condition cond) { it(cond, 0xa); } 219 void itte(Condition cond) { it(cond, 0x6); } 220 void itee(Condition cond) { it(cond, 0xe); } 221 void itttt(Condition cond) { it(cond, 0x1); } 222 void itett(Condition cond) { it(cond, 0x9); } 223 void ittet(Condition cond) { it(cond, 0x5); } 224 void iteet(Condition cond) { it(cond, 0xd); } 225 void ittte(Condition cond) { it(cond, 0x3); } 226 void itete(Condition cond) { it(cond, 0xb); } 227 void ittee(Condition cond) { it(cond, 0x7); } 228 void iteee(Condition cond) { it(cond, 0xf); } 229 230 // Start of generated code. 231 typedef void (Assembler::*InstructionCondSizeRROp)(Condition cond, 232 EncodingSize size, 233 Register rd, 234 Register rn, 235 const Operand& operand); 236 typedef void (Assembler::*InstructionCondROp)(Condition cond, 237 Register rd, 238 const Operand& operand); 239 typedef void (Assembler::*InstructionROp)(Register rd, 240 const Operand& operand); 241 typedef void (Assembler::*InstructionCondRROp)(Condition cond, 242 Register rd, 243 Register rn, 244 const Operand& operand); 245 typedef void (Assembler::*InstructionCondSizeRL)(Condition cond, 246 EncodingSize size, 247 Register rd, 248 Label* label); 249 typedef void (Assembler::*InstructionCondSizeL)(Condition cond, 250 EncodingSize size, 251 Label* label); 252 typedef void (Assembler::*InstructionCondRIOp)(Condition cond, 253 Register rd, 254 uint32_t lsb, 255 const Operand& operand); 256 typedef void (Assembler::*InstructionCondRRIOp)(Condition cond, 257 Register rd, 258 Register rn, 259 uint32_t lsb, 260 const Operand& operand); 261 typedef void (Assembler::*InstructionCondI)(Condition cond, uint32_t imm); 262 typedef void (Assembler::*InstructionCondL)(Condition cond, Label* label); 263 typedef void (Assembler::*InstructionCondR)(Condition cond, Register rm); 264 typedef void (Assembler::*InstructionRL)(Register rn, Label* label); 265 typedef void (Assembler::*InstructionCond)(Condition cond); 266 typedef void (Assembler::*InstructionCondRR)(Condition cond, 267 Register rd, 268 Register rm); 269 typedef void (Assembler::*InstructionCondSizeROp)(Condition cond, 270 EncodingSize size, 271 Register rn, 272 const Operand& operand); 273 typedef void (Assembler::*InstructionCondRRR)(Condition cond, 274 Register rd, 275 Register rn, 276 Register rm); 277 typedef void (Assembler::*InstructionCondBa)(Condition cond, 278 MemoryBarrier option); 279 typedef void (Assembler::*InstructionCondRwbDrl)(Condition cond, 280 Register rn, 281 WriteBack write_back, 282 DRegisterList dreglist); 283 typedef void (Assembler::*InstructionCondRMop)(Condition cond, 284 Register rt, 285 const MemOperand& operand); 286 typedef void (Assembler::*InstructionCondRRMop)(Condition cond, 287 Register rt, 288 Register rt2, 289 const MemOperand& operand); 290 typedef void (Assembler::*InstructionCondSizeRwbRl)(Condition cond, 291 EncodingSize size, 292 Register rn, 293 WriteBack write_back, 294 RegisterList registers); 295 typedef void (Assembler::*InstructionCondRwbRl)(Condition cond, 296 Register rn, 297 WriteBack write_back, 298 RegisterList registers); 299 typedef void (Assembler::*InstructionCondSizeRMop)(Condition cond, 300 EncodingSize size, 301 Register rt, 302 const MemOperand& operand); 303 typedef void (Assembler::*InstructionCondRL)(Condition cond, 304 Register rt, 305 Label* label); 306 typedef void (Assembler::*InstructionCondRRL)(Condition cond, 307 Register rt, 308 Register rt2, 309 Label* label); 310 typedef void (Assembler::*InstructionCondRRRR)( 311 Condition cond, Register rd, Register rn, Register rm, Register ra); 312 typedef void (Assembler::*InstructionCondRSr)(Condition cond, 313 Register rd, 314 SpecialRegister spec_reg); 315 typedef void (Assembler::*InstructionCondMsrOp)( 316 Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand); 317 typedef void (Assembler::*InstructionCondSizeRRR)( 318 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); 319 typedef void (Assembler::*InstructionCondSize)(Condition cond, 320 EncodingSize size); 321 typedef void (Assembler::*InstructionCondMop)(Condition cond, 322 const MemOperand& operand); 323 typedef void (Assembler::*InstructionCondSizeRl)(Condition cond, 324 EncodingSize size, 325 RegisterList registers); 326 typedef void (Assembler::*InstructionCondSizeOrl)(Condition cond, 327 EncodingSize size, 328 Register rt); 329 typedef void (Assembler::*InstructionCondSizeRR)(Condition cond, 330 EncodingSize size, 331 Register rd, 332 Register rm); 333 typedef void (Assembler::*InstructionDtQQQ)(DataType dt, 334 QRegister rd, 335 QRegister rn, 336 QRegister rm); 337 typedef void (Assembler::*InstructionCondRIR)(Condition cond, 338 Register rd, 339 uint32_t imm, 340 Register rn); 341 typedef void (Assembler::*InstructionCondRRRMop)(Condition cond, 342 Register rd, 343 Register rt, 344 Register rt2, 345 const MemOperand& operand); 346 typedef void (Assembler::*InstructionCondSizeI)(Condition cond, 347 EncodingSize size, 348 uint32_t imm); 349 typedef void (Assembler::*InstructionCondDtDDD)( 350 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 351 typedef void (Assembler::*InstructionCondDtQQQ)( 352 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 353 typedef void (Assembler::*InstructionCondDtQDD)( 354 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 355 typedef void (Assembler::*InstructionCondDtDD)(Condition cond, 356 DataType dt, 357 DRegister rd, 358 DRegister rm); 359 typedef void (Assembler::*InstructionCondDtQQ)(Condition cond, 360 DataType dt, 361 QRegister rd, 362 QRegister rm); 363 typedef void (Assembler::*InstructionCondDtSS)(Condition cond, 364 DataType dt, 365 SRegister rd, 366 SRegister rm); 367 typedef void (Assembler::*InstructionCondDtSSS)( 368 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 369 typedef void (Assembler::*InstructionCondDtDQQ)( 370 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 371 typedef void (Assembler::*InstructionCondDtQQD)( 372 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 373 typedef void (Assembler::*InstructionCondDtDDDop)(Condition cond, 374 DataType dt, 375 DRegister rd, 376 DRegister rn, 377 const DOperand& operand); 378 typedef void (Assembler::*InstructionCondDtQQQop)(Condition cond, 379 DataType dt, 380 QRegister rd, 381 QRegister rn, 382 const QOperand& operand); 383 typedef void (Assembler::*InstructionCondDtSFi)(Condition cond, 384 DataType dt, 385 SRegister rd, 386 double imm); 387 typedef void (Assembler::*InstructionCondDtDFi)(Condition cond, 388 DataType dt, 389 DRegister rd, 390 double imm); 391 typedef void (Assembler::*InstructionCondDtDtDS)( 392 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 393 typedef void (Assembler::*InstructionCondDtDtSD)( 394 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 395 typedef void (Assembler::*InstructionCondDtDtDDSi)(Condition cond, 396 DataType dt1, 397 DataType dt2, 398 DRegister rd, 399 DRegister rm, 400 int32_t fbits); 401 typedef void (Assembler::*InstructionCondDtDtQQSi)(Condition cond, 402 DataType dt1, 403 DataType dt2, 404 QRegister rd, 405 QRegister rm, 406 int32_t fbits); 407 typedef void (Assembler::*InstructionCondDtDtSSSi)(Condition cond, 408 DataType dt1, 409 DataType dt2, 410 SRegister rd, 411 SRegister rm, 412 int32_t fbits); 413 typedef void (Assembler::*InstructionCondDtDtDD)( 414 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 415 typedef void (Assembler::*InstructionCondDtDtQQ)( 416 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm); 417 typedef void (Assembler::*InstructionCondDtDtDQ)( 418 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm); 419 typedef void (Assembler::*InstructionCondDtDtQD)( 420 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm); 421 typedef void (Assembler::*InstructionCondDtDtSS)( 422 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 423 typedef void (Assembler::*InstructionDtDtDD)(DataType dt1, 424 DataType dt2, 425 DRegister rd, 426 DRegister rm); 427 typedef void (Assembler::*InstructionDtDtQQ)(DataType dt1, 428 DataType dt2, 429 QRegister rd, 430 QRegister rm); 431 typedef void (Assembler::*InstructionDtDtSS)(DataType dt1, 432 DataType dt2, 433 SRegister rd, 434 SRegister rm); 435 typedef void (Assembler::*InstructionDtDtSD)(DataType dt1, 436 DataType dt2, 437 SRegister rd, 438 DRegister rm); 439 typedef void (Assembler::*InstructionCondDtQR)(Condition cond, 440 DataType dt, 441 QRegister rd, 442 Register rt); 443 typedef void (Assembler::*InstructionCondDtDR)(Condition cond, 444 DataType dt, 445 DRegister rd, 446 Register rt); 447 typedef void (Assembler::*InstructionCondDtDDx)(Condition cond, 448 DataType dt, 449 DRegister rd, 450 DRegisterLane rm); 451 typedef void (Assembler::*InstructionCondDtQDx)(Condition cond, 452 DataType dt, 453 QRegister rd, 454 DRegisterLane rm); 455 typedef void (Assembler::*InstructionCondDtDDDDop)(Condition cond, 456 DataType dt, 457 DRegister rd, 458 DRegister rn, 459 DRegister rm, 460 const DOperand& operand); 461 typedef void (Assembler::*InstructionCondDtQQQQop)(Condition cond, 462 DataType dt, 463 QRegister rd, 464 QRegister rn, 465 QRegister rm, 466 const QOperand& operand); 467 typedef void (Assembler::*InstructionCondDtNrlAmop)( 468 Condition cond, 469 DataType dt, 470 const NeonRegisterList& nreglist, 471 const AlignedMemOperand& operand); 472 typedef void (Assembler::*InstructionCondDtNrlMop)( 473 Condition cond, 474 DataType dt, 475 const NeonRegisterList& nreglist, 476 const MemOperand& operand); 477 typedef void (Assembler::*InstructionCondDtRwbDrl)(Condition cond, 478 DataType dt, 479 Register rn, 480 WriteBack write_back, 481 DRegisterList dreglist); 482 typedef void (Assembler::*InstructionCondDtRwbSrl)(Condition cond, 483 DataType dt, 484 Register rn, 485 WriteBack write_back, 486 SRegisterList sreglist); 487 typedef void (Assembler::*InstructionCondDtDL)(Condition cond, 488 DataType dt, 489 DRegister rd, 490 Label* label); 491 typedef void (Assembler::*InstructionCondDtDMop)(Condition cond, 492 DataType dt, 493 DRegister rd, 494 const MemOperand& operand); 495 typedef void (Assembler::*InstructionCondDtSL)(Condition cond, 496 DataType dt, 497 SRegister rd, 498 Label* label); 499 typedef void (Assembler::*InstructionCondDtSMop)(Condition cond, 500 DataType dt, 501 SRegister rd, 502 const MemOperand& operand); 503 typedef void (Assembler::*InstructionDtDDD)(DataType dt, 504 DRegister rd, 505 DRegister rn, 506 DRegister rm); 507 typedef void (Assembler::*InstructionDtSSS)(DataType dt, 508 SRegister rd, 509 SRegister rn, 510 SRegister rm); 511 typedef void (Assembler::*InstructionCondDtDDDx)(Condition cond, 512 DataType dt, 513 DRegister rd, 514 DRegister rn, 515 DRegisterLane rm); 516 typedef void (Assembler::*InstructionCondDtQQDx)(Condition cond, 517 DataType dt, 518 QRegister rd, 519 QRegister rn, 520 DRegisterLane rm); 521 typedef void (Assembler::*InstructionCondDtQDDx)(Condition cond, 522 DataType dt, 523 QRegister rd, 524 DRegister rn, 525 DRegisterLane rm); 526 typedef void (Assembler::*InstructionCondRS)(Condition cond, 527 Register rt, 528 SRegister rn); 529 typedef void (Assembler::*InstructionCondSR)(Condition cond, 530 SRegister rn, 531 Register rt); 532 typedef void (Assembler::*InstructionCondRRD)(Condition cond, 533 Register rt, 534 Register rt2, 535 DRegister rm); 536 typedef void (Assembler::*InstructionCondDRR)(Condition cond, 537 DRegister rm, 538 Register rt, 539 Register rt2); 540 typedef void (Assembler::*InstructionCondRRSS)( 541 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1); 542 typedef void (Assembler::*InstructionCondSSRR)( 543 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2); 544 typedef void (Assembler::*InstructionCondDtDxR)(Condition cond, 545 DataType dt, 546 DRegisterLane rd, 547 Register rt); 548 typedef void (Assembler::*InstructionCondDtDDop)(Condition cond, 549 DataType dt, 550 DRegister rd, 551 const DOperand& operand); 552 typedef void (Assembler::*InstructionCondDtQQop)(Condition cond, 553 DataType dt, 554 QRegister rd, 555 const QOperand& operand); 556 typedef void (Assembler::*InstructionCondDtSSop)(Condition cond, 557 DataType dt, 558 SRegister rd, 559 const SOperand& operand); 560 typedef void (Assembler::*InstructionCondDtRDx)(Condition cond, 561 DataType dt, 562 Register rt, 563 DRegisterLane rn); 564 typedef void (Assembler::*InstructionCondDtQD)(Condition cond, 565 DataType dt, 566 QRegister rd, 567 DRegister rm); 568 typedef void (Assembler::*InstructionCondDtDQ)(Condition cond, 569 DataType dt, 570 DRegister rd, 571 QRegister rm); 572 typedef void (Assembler::*InstructionCondRoaSfp)(Condition cond, 573 RegisterOrAPSR_nzcv rt, 574 SpecialFPRegister spec_reg); 575 typedef void (Assembler::*InstructionCondSfpR)(Condition cond, 576 SpecialFPRegister spec_reg, 577 Register rt); 578 typedef void (Assembler::*InstructionCondDtDDIr)(Condition cond, 579 DataType dt, 580 DRegister rd, 581 DRegister rn, 582 DRegister dm, 583 unsigned index); 584 typedef void (Assembler::*InstructionCondDtQQIr)(Condition cond, 585 DataType dt, 586 QRegister rd, 587 QRegister rn, 588 DRegister dm, 589 unsigned index); 590 typedef void (Assembler::*InstructionCondDtQDIr)(Condition cond, 591 DataType dt, 592 QRegister rd, 593 DRegister rn, 594 DRegister dm, 595 unsigned index); 596 typedef void (Assembler::*InstructionCondDtDrl)(Condition cond, 597 DataType dt, 598 DRegisterList dreglist); 599 typedef void (Assembler::*InstructionCondDtSrl)(Condition cond, 600 DataType dt, 601 SRegisterList sreglist); 602 typedef void (Assembler::*InstructionCondDtDQQop)(Condition cond, 603 DataType dt, 604 DRegister rd, 605 QRegister rm, 606 const QOperand& operand); 607 typedef void (Assembler::*InstructionCondDtQDDop)(Condition cond, 608 DataType dt, 609 QRegister rd, 610 DRegister rm, 611 const DOperand& operand); 612 typedef void (Assembler::*InstructionCondDtDNrlD)( 613 Condition cond, 614 DataType dt, 615 DRegister rd, 616 const NeonRegisterList& nreglist, 617 DRegister rm); 618 virtual void Delegate(InstructionType type, 619 InstructionCondSizeRROp /*instruction*/, 620 Condition /*cond*/, 621 EncodingSize /*size*/, 622 Register /*rd*/, 623 Register /*rn*/, 624 const Operand& /*operand*/) { 625 USE(type); 626 VIXL_ASSERT((type == kAdc) || (type == kAdcs) || (type == kAdd) || 627 (type == kAdds) || (type == kAnd) || (type == kAnds) || 628 (type == kAsr) || (type == kAsrs) || (type == kBic) || 629 (type == kBics) || (type == kEor) || (type == kEors) || 630 (type == kLsl) || (type == kLsls) || (type == kLsr) || 631 (type == kLsrs) || (type == kOrr) || (type == kOrrs) || 632 (type == kRor) || (type == kRors) || (type == kRsb) || 633 (type == kRsbs) || (type == kSbc) || (type == kSbcs) || 634 (type == kSub) || (type == kSubs)); 635 UnimplementedDelegate(type); 636 } 637 virtual void Delegate(InstructionType type, 638 InstructionCondROp /*instruction*/, 639 Condition /*cond*/, 640 Register /*rd*/, 641 const Operand& /*operand*/) { 642 USE(type); 643 VIXL_ASSERT((type == kAdd) || (type == kMovt) || (type == kMovw) || 644 (type == kSub) || (type == kSxtb16) || (type == kTeq) || 645 (type == kUxtb16)); 646 UnimplementedDelegate(type); 647 } 648 virtual void Delegate(InstructionType type, 649 InstructionROp /*instruction*/, 650 Register /*rd*/, 651 const Operand& /*operand*/) { 652 USE(type); 653 VIXL_ASSERT((type == kAdds) || (type == kSubs)); 654 UnimplementedDelegate(type); 655 } 656 virtual void Delegate(InstructionType type, 657 InstructionCondRROp /*instruction*/, 658 Condition /*cond*/, 659 Register /*rd*/, 660 Register /*rn*/, 661 const Operand& /*operand*/) { 662 USE(type); 663 VIXL_ASSERT((type == kAddw) || (type == kOrn) || (type == kOrns) || 664 (type == kPkhbt) || (type == kPkhtb) || (type == kRsc) || 665 (type == kRscs) || (type == kSubw) || (type == kSxtab) || 666 (type == kSxtab16) || (type == kSxtah) || (type == kUxtab) || 667 (type == kUxtab16) || (type == kUxtah)); 668 UnimplementedDelegate(type); 669 } 670 virtual void Delegate(InstructionType type, 671 InstructionCondSizeRL /*instruction*/, 672 Condition /*cond*/, 673 EncodingSize /*size*/, 674 Register /*rd*/, 675 Label* /*label*/) { 676 USE(type); 677 VIXL_ASSERT((type == kAdr) || (type == kLdr)); 678 UnimplementedDelegate(type); 679 } 680 virtual void Delegate(InstructionType type, 681 InstructionCondSizeL /*instruction*/, 682 Condition /*cond*/, 683 EncodingSize /*size*/, 684 Label* /*label*/) { 685 USE(type); 686 VIXL_ASSERT((type == kB)); 687 UnimplementedDelegate(type); 688 } 689 virtual void Delegate(InstructionType type, 690 InstructionCondRIOp /*instruction*/, 691 Condition /*cond*/, 692 Register /*rd*/, 693 uint32_t /*lsb*/, 694 const Operand& /*operand*/) { 695 USE(type); 696 VIXL_ASSERT((type == kBfc) || (type == kSsat) || (type == kUsat)); 697 UnimplementedDelegate(type); 698 } 699 virtual void Delegate(InstructionType type, 700 InstructionCondRRIOp /*instruction*/, 701 Condition /*cond*/, 702 Register /*rd*/, 703 Register /*rn*/, 704 uint32_t /*lsb*/, 705 const Operand& /*operand*/) { 706 USE(type); 707 VIXL_ASSERT((type == kBfi) || (type == kSbfx) || (type == kUbfx)); 708 UnimplementedDelegate(type); 709 } 710 virtual void Delegate(InstructionType type, 711 InstructionCondI /*instruction*/, 712 Condition /*cond*/, 713 uint32_t /*imm*/) { 714 USE(type); 715 VIXL_ASSERT((type == kBkpt) || (type == kHlt) || (type == kHvc) || 716 (type == kSvc)); 717 UnimplementedDelegate(type); 718 } 719 virtual void Delegate(InstructionType type, 720 InstructionCondL /*instruction*/, 721 Condition /*cond*/, 722 Label* /*label*/) { 723 USE(type); 724 VIXL_ASSERT((type == kBl) || (type == kBlx) || (type == kPld) || 725 (type == kPli)); 726 UnimplementedDelegate(type); 727 } 728 virtual void Delegate(InstructionType type, 729 InstructionCondR /*instruction*/, 730 Condition /*cond*/, 731 Register /*rm*/) { 732 USE(type); 733 VIXL_ASSERT((type == kBlx) || (type == kBx) || (type == kBxj)); 734 UnimplementedDelegate(type); 735 } 736 virtual void Delegate(InstructionType type, 737 InstructionRL /*instruction*/, 738 Register /*rn*/, 739 Label* /*label*/) { 740 USE(type); 741 VIXL_ASSERT((type == kCbnz) || (type == kCbz)); 742 UnimplementedDelegate(type); 743 } 744 virtual void Delegate(InstructionType type, 745 InstructionCond /*instruction*/, 746 Condition /*cond*/) { 747 USE(type); 748 VIXL_ASSERT((type == kClrex)); 749 UnimplementedDelegate(type); 750 } 751 virtual void Delegate(InstructionType type, 752 InstructionCondRR /*instruction*/, 753 Condition /*cond*/, 754 Register /*rd*/, 755 Register /*rm*/) { 756 USE(type); 757 VIXL_ASSERT((type == kClz) || (type == kRbit) || (type == kRrx) || 758 (type == kRrxs)); 759 UnimplementedDelegate(type); 760 } 761 virtual void Delegate(InstructionType type, 762 InstructionCondSizeROp /*instruction*/, 763 Condition /*cond*/, 764 EncodingSize /*size*/, 765 Register /*rn*/, 766 const Operand& /*operand*/) { 767 USE(type); 768 VIXL_ASSERT((type == kCmn) || (type == kCmp) || (type == kMov) || 769 (type == kMovs) || (type == kMvn) || (type == kMvns) || 770 (type == kSxtb) || (type == kSxth) || (type == kTst) || 771 (type == kUxtb) || (type == kUxth)); 772 UnimplementedDelegate(type); 773 } 774 virtual void Delegate(InstructionType type, 775 InstructionCondRRR /*instruction*/, 776 Condition /*cond*/, 777 Register /*rd*/, 778 Register /*rn*/, 779 Register /*rm*/) { 780 USE(type); 781 VIXL_ASSERT((type == kCrc32b) || (type == kCrc32cb) || (type == kCrc32ch) || 782 (type == kCrc32cw) || (type == kCrc32h) || (type == kCrc32w) || 783 (type == kMuls) || (type == kQadd) || (type == kQadd16) || 784 (type == kQadd8) || (type == kQasx) || (type == kQdadd) || 785 (type == kQdsub) || (type == kQsax) || (type == kQsub) || 786 (type == kQsub16) || (type == kQsub8) || (type == kSadd16) || 787 (type == kSadd8) || (type == kSasx) || (type == kSdiv) || 788 (type == kSel) || (type == kShadd16) || (type == kShadd8) || 789 (type == kShasx) || (type == kShsax) || (type == kShsub16) || 790 (type == kShsub8) || (type == kSmmul) || (type == kSmmulr) || 791 (type == kSmuad) || (type == kSmuadx) || (type == kSmulbb) || 792 (type == kSmulbt) || (type == kSmultb) || (type == kSmultt) || 793 (type == kSmulwb) || (type == kSmulwt) || (type == kSmusd) || 794 (type == kSmusdx) || (type == kSsax) || (type == kSsub16) || 795 (type == kSsub8) || (type == kUadd16) || (type == kUadd8) || 796 (type == kUasx) || (type == kUdiv) || (type == kUhadd16) || 797 (type == kUhadd8) || (type == kUhasx) || (type == kUhsax) || 798 (type == kUhsub16) || (type == kUhsub8) || (type == kUqadd16) || 799 (type == kUqadd8) || (type == kUqasx) || (type == kUqsax) || 800 (type == kUqsub16) || (type == kUqsub8) || (type == kUsad8) || 801 (type == kUsax) || (type == kUsub16) || (type == kUsub8)); 802 UnimplementedDelegate(type); 803 } 804 virtual void Delegate(InstructionType type, 805 InstructionCondBa /*instruction*/, 806 Condition /*cond*/, 807 MemoryBarrier /*option*/) { 808 USE(type); 809 VIXL_ASSERT((type == kDmb) || (type == kDsb) || (type == kIsb)); 810 UnimplementedDelegate(type); 811 } 812 virtual void Delegate(InstructionType type, 813 InstructionCondRwbDrl /*instruction*/, 814 Condition /*cond*/, 815 Register /*rn*/, 816 WriteBack /*write_back*/, 817 DRegisterList /*dreglist*/) { 818 USE(type); 819 VIXL_ASSERT((type == kFldmdbx) || (type == kFldmiax) || 820 (type == kFstmdbx) || (type == kFstmiax)); 821 UnimplementedDelegate(type); 822 } 823 virtual void DelegateIt(Condition /*cond*/, uint16_t /*mask*/) { 824 UnimplementedDelegate(kIt); 825 } 826 virtual void Delegate(InstructionType type, 827 InstructionCondRMop /*instruction*/, 828 Condition /*cond*/, 829 Register /*rt*/, 830 const MemOperand& /*operand*/) { 831 USE(type); 832 VIXL_ASSERT((type == kLda) || (type == kLdab) || (type == kLdaex) || 833 (type == kLdaexb) || (type == kLdaexh) || (type == kLdah) || 834 (type == kLdrex) || (type == kLdrexb) || (type == kLdrexh) || 835 (type == kStl) || (type == kStlb) || (type == kStlh)); 836 UnimplementedDelegate(type); 837 } 838 virtual void Delegate(InstructionType type, 839 InstructionCondRRMop /*instruction*/, 840 Condition /*cond*/, 841 Register /*rt*/, 842 Register /*rt2*/, 843 const MemOperand& /*operand*/) { 844 USE(type); 845 VIXL_ASSERT((type == kLdaexd) || (type == kLdrd) || (type == kLdrexd) || 846 (type == kStlex) || (type == kStlexb) || (type == kStlexh) || 847 (type == kStrd) || (type == kStrex) || (type == kStrexb) || 848 (type == kStrexh)); 849 UnimplementedDelegate(type); 850 } 851 virtual void Delegate(InstructionType type, 852 InstructionCondSizeRwbRl /*instruction*/, 853 Condition /*cond*/, 854 EncodingSize /*size*/, 855 Register /*rn*/, 856 WriteBack /*write_back*/, 857 RegisterList /*registers*/) { 858 USE(type); 859 VIXL_ASSERT((type == kLdm) || (type == kLdmfd) || (type == kStm) || 860 (type == kStmdb) || (type == kStmea)); 861 UnimplementedDelegate(type); 862 } 863 virtual void Delegate(InstructionType type, 864 InstructionCondRwbRl /*instruction*/, 865 Condition /*cond*/, 866 Register /*rn*/, 867 WriteBack /*write_back*/, 868 RegisterList /*registers*/) { 869 USE(type); 870 VIXL_ASSERT((type == kLdmda) || (type == kLdmdb) || (type == kLdmea) || 871 (type == kLdmed) || (type == kLdmfa) || (type == kLdmib) || 872 (type == kStmda) || (type == kStmed) || (type == kStmfa) || 873 (type == kStmfd) || (type == kStmib)); 874 UnimplementedDelegate(type); 875 } 876 virtual void Delegate(InstructionType type, 877 InstructionCondSizeRMop /*instruction*/, 878 Condition /*cond*/, 879 EncodingSize /*size*/, 880 Register /*rt*/, 881 const MemOperand& /*operand*/) { 882 USE(type); 883 VIXL_ASSERT((type == kLdr) || (type == kLdrb) || (type == kLdrh) || 884 (type == kLdrsb) || (type == kLdrsh) || (type == kStr) || 885 (type == kStrb) || (type == kStrh)); 886 UnimplementedDelegate(type); 887 } 888 virtual void Delegate(InstructionType type, 889 InstructionCondRL /*instruction*/, 890 Condition /*cond*/, 891 Register /*rt*/, 892 Label* /*label*/) { 893 USE(type); 894 VIXL_ASSERT((type == kLdrb) || (type == kLdrh) || (type == kLdrsb) || 895 (type == kLdrsh)); 896 UnimplementedDelegate(type); 897 } 898 virtual void Delegate(InstructionType type, 899 InstructionCondRRL /*instruction*/, 900 Condition /*cond*/, 901 Register /*rt*/, 902 Register /*rt2*/, 903 Label* /*label*/) { 904 USE(type); 905 VIXL_ASSERT((type == kLdrd)); 906 UnimplementedDelegate(type); 907 } 908 virtual void Delegate(InstructionType type, 909 InstructionCondRRRR /*instruction*/, 910 Condition /*cond*/, 911 Register /*rd*/, 912 Register /*rn*/, 913 Register /*rm*/, 914 Register /*ra*/) { 915 USE(type); 916 VIXL_ASSERT((type == kMla) || (type == kMlas) || (type == kMls) || 917 (type == kSmlabb) || (type == kSmlabt) || (type == kSmlad) || 918 (type == kSmladx) || (type == kSmlal) || (type == kSmlalbb) || 919 (type == kSmlalbt) || (type == kSmlald) || (type == kSmlaldx) || 920 (type == kSmlals) || (type == kSmlaltb) || (type == kSmlaltt) || 921 (type == kSmlatb) || (type == kSmlatt) || (type == kSmlawb) || 922 (type == kSmlawt) || (type == kSmlsd) || (type == kSmlsdx) || 923 (type == kSmlsld) || (type == kSmlsldx) || (type == kSmmla) || 924 (type == kSmmlar) || (type == kSmmls) || (type == kSmmlsr) || 925 (type == kSmull) || (type == kSmulls) || (type == kUmaal) || 926 (type == kUmlal) || (type == kUmlals) || (type == kUmull) || 927 (type == kUmulls) || (type == kUsada8)); 928 UnimplementedDelegate(type); 929 } 930 virtual void Delegate(InstructionType type, 931 InstructionCondRSr /*instruction*/, 932 Condition /*cond*/, 933 Register /*rd*/, 934 SpecialRegister /*spec_reg*/) { 935 USE(type); 936 VIXL_ASSERT((type == kMrs)); 937 UnimplementedDelegate(type); 938 } 939 virtual void Delegate(InstructionType type, 940 InstructionCondMsrOp /*instruction*/, 941 Condition /*cond*/, 942 MaskedSpecialRegister /*spec_reg*/, 943 const Operand& /*operand*/) { 944 USE(type); 945 VIXL_ASSERT((type == kMsr)); 946 UnimplementedDelegate(type); 947 } 948 virtual void Delegate(InstructionType type, 949 InstructionCondSizeRRR /*instruction*/, 950 Condition /*cond*/, 951 EncodingSize /*size*/, 952 Register /*rd*/, 953 Register /*rn*/, 954 Register /*rm*/) { 955 USE(type); 956 VIXL_ASSERT((type == kMul)); 957 UnimplementedDelegate(type); 958 } 959 virtual void Delegate(InstructionType type, 960 InstructionCondSize /*instruction*/, 961 Condition /*cond*/, 962 EncodingSize /*size*/) { 963 USE(type); 964 VIXL_ASSERT((type == kNop) || (type == kYield)); 965 UnimplementedDelegate(type); 966 } 967 virtual void Delegate(InstructionType type, 968 InstructionCondMop /*instruction*/, 969 Condition /*cond*/, 970 const MemOperand& /*operand*/) { 971 USE(type); 972 VIXL_ASSERT((type == kPld) || (type == kPldw) || (type == kPli)); 973 UnimplementedDelegate(type); 974 } 975 virtual void Delegate(InstructionType type, 976 InstructionCondSizeRl /*instruction*/, 977 Condition /*cond*/, 978 EncodingSize /*size*/, 979 RegisterList /*registers*/) { 980 USE(type); 981 VIXL_ASSERT((type == kPop) || (type == kPush)); 982 UnimplementedDelegate(type); 983 } 984 virtual void Delegate(InstructionType type, 985 InstructionCondSizeOrl /*instruction*/, 986 Condition /*cond*/, 987 EncodingSize /*size*/, 988 Register /*rt*/) { 989 USE(type); 990 VIXL_ASSERT((type == kPop) || (type == kPush)); 991 UnimplementedDelegate(type); 992 } 993 virtual void Delegate(InstructionType type, 994 InstructionCondSizeRR /*instruction*/, 995 Condition /*cond*/, 996 EncodingSize /*size*/, 997 Register /*rd*/, 998 Register /*rm*/) { 999 USE(type); 1000 VIXL_ASSERT((type == kRev) || (type == kRev16) || (type == kRevsh)); 1001 UnimplementedDelegate(type); 1002 } 1003 virtual void Delegate(InstructionType type, 1004 InstructionDtQQQ /*instruction*/, 1005 DataType /*dt*/, 1006 QRegister /*rd*/, 1007 QRegister /*rn*/, 1008 QRegister /*rm*/) { 1009 USE(type); 1010 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm)); 1011 UnimplementedDelegate(type); 1012 } 1013 virtual void Delegate(InstructionType type, 1014 InstructionCondRIR /*instruction*/, 1015 Condition /*cond*/, 1016 Register /*rd*/, 1017 uint32_t /*imm*/, 1018 Register /*rn*/) { 1019 USE(type); 1020 VIXL_ASSERT((type == kSsat16) || (type == kUsat16)); 1021 UnimplementedDelegate(type); 1022 } 1023 virtual void Delegate(InstructionType type, 1024 InstructionCondRRRMop /*instruction*/, 1025 Condition /*cond*/, 1026 Register /*rd*/, 1027 Register /*rt*/, 1028 Register /*rt2*/, 1029 const MemOperand& /*operand*/) { 1030 USE(type); 1031 VIXL_ASSERT((type == kStlexd) || (type == kStrexd)); 1032 UnimplementedDelegate(type); 1033 } 1034 virtual void Delegate(InstructionType type, 1035 InstructionCondSizeI /*instruction*/, 1036 Condition /*cond*/, 1037 EncodingSize /*size*/, 1038 uint32_t /*imm*/) { 1039 USE(type); 1040 VIXL_ASSERT((type == kUdf)); 1041 UnimplementedDelegate(type); 1042 } 1043 virtual void Delegate(InstructionType type, 1044 InstructionCondDtDDD /*instruction*/, 1045 Condition /*cond*/, 1046 DataType /*dt*/, 1047 DRegister /*rd*/, 1048 DRegister /*rn*/, 1049 DRegister /*rm*/) { 1050 USE(type); 1051 VIXL_ASSERT((type == kVaba) || (type == kVabd) || (type == kVacge) || 1052 (type == kVacgt) || (type == kVacle) || (type == kVaclt) || 1053 (type == kVadd) || (type == kVbif) || (type == kVbit) || 1054 (type == kVbsl) || (type == kVceq) || (type == kVcge) || 1055 (type == kVcgt) || (type == kVcle) || (type == kVclt) || 1056 (type == kVdiv) || (type == kVeor) || (type == kVfma) || 1057 (type == kVfms) || (type == kVfnma) || (type == kVfnms) || 1058 (type == kVhadd) || (type == kVhsub) || (type == kVmax) || 1059 (type == kVmin) || (type == kVmla) || (type == kVmls) || 1060 (type == kVmul) || (type == kVnmla) || (type == kVnmls) || 1061 (type == kVnmul) || (type == kVpadd) || (type == kVpmax) || 1062 (type == kVpmin) || (type == kVqadd) || (type == kVqdmulh) || 1063 (type == kVqrdmulh) || (type == kVqrshl) || (type == kVqsub) || 1064 (type == kVrecps) || (type == kVrhadd) || (type == kVrshl) || 1065 (type == kVrsqrts) || (type == kVsub) || (type == kVtst)); 1066 UnimplementedDelegate(type); 1067 } 1068 virtual void Delegate(InstructionType type, 1069 InstructionCondDtQQQ /*instruction*/, 1070 Condition /*cond*/, 1071 DataType /*dt*/, 1072 QRegister /*rd*/, 1073 QRegister /*rn*/, 1074 QRegister /*rm*/) { 1075 USE(type); 1076 VIXL_ASSERT((type == kVaba) || (type == kVabd) || (type == kVacge) || 1077 (type == kVacgt) || (type == kVacle) || (type == kVaclt) || 1078 (type == kVadd) || (type == kVbif) || (type == kVbit) || 1079 (type == kVbsl) || (type == kVceq) || (type == kVcge) || 1080 (type == kVcgt) || (type == kVcle) || (type == kVclt) || 1081 (type == kVeor) || (type == kVfma) || (type == kVfms) || 1082 (type == kVhadd) || (type == kVhsub) || (type == kVmax) || 1083 (type == kVmin) || (type == kVmla) || (type == kVmls) || 1084 (type == kVmul) || (type == kVqadd) || (type == kVqdmulh) || 1085 (type == kVqrdmulh) || (type == kVqrshl) || (type == kVqsub) || 1086 (type == kVrecps) || (type == kVrhadd) || (type == kVrshl) || 1087 (type == kVrsqrts) || (type == kVsub) || (type == kVtst)); 1088 UnimplementedDelegate(type); 1089 } 1090 virtual void Delegate(InstructionType type, 1091 InstructionCondDtQDD /*instruction*/, 1092 Condition /*cond*/, 1093 DataType /*dt*/, 1094 QRegister /*rd*/, 1095 DRegister /*rn*/, 1096 DRegister /*rm*/) { 1097 USE(type); 1098 VIXL_ASSERT((type == kVabal) || (type == kVabdl) || (type == kVaddl) || 1099 (type == kVmlal) || (type == kVmlsl) || (type == kVmull) || 1100 (type == kVqdmlal) || (type == kVqdmlsl) || 1101 (type == kVqdmull) || (type == kVsubl)); 1102 UnimplementedDelegate(type); 1103 } 1104 virtual void Delegate(InstructionType type, 1105 InstructionCondDtDD /*instruction*/, 1106 Condition /*cond*/, 1107 DataType /*dt*/, 1108 DRegister /*rd*/, 1109 DRegister /*rm*/) { 1110 USE(type); 1111 VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) || 1112 (type == kVcmp) || (type == kVcmpe) || (type == kVcnt) || 1113 (type == kVneg) || (type == kVpadal) || (type == kVpaddl) || 1114 (type == kVqabs) || (type == kVqneg) || (type == kVrecpe) || 1115 (type == kVrev16) || (type == kVrev32) || (type == kVrev64) || 1116 (type == kVrsqrte) || (type == kVsqrt) || (type == kVswp) || 1117 (type == kVtrn) || (type == kVuzp) || (type == kVzip)); 1118 UnimplementedDelegate(type); 1119 } 1120 virtual void Delegate(InstructionType type, 1121 InstructionCondDtQQ /*instruction*/, 1122 Condition /*cond*/, 1123 DataType /*dt*/, 1124 QRegister /*rd*/, 1125 QRegister /*rm*/) { 1126 USE(type); 1127 VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) || 1128 (type == kVcnt) || (type == kVneg) || (type == kVpadal) || 1129 (type == kVpaddl) || (type == kVqabs) || (type == kVqneg) || 1130 (type == kVrecpe) || (type == kVrev16) || (type == kVrev32) || 1131 (type == kVrev64) || (type == kVrsqrte) || (type == kVswp) || 1132 (type == kVtrn) || (type == kVuzp) || (type == kVzip)); 1133 UnimplementedDelegate(type); 1134 } 1135 virtual void Delegate(InstructionType type, 1136 InstructionCondDtSS /*instruction*/, 1137 Condition /*cond*/, 1138 DataType /*dt*/, 1139 SRegister /*rd*/, 1140 SRegister /*rm*/) { 1141 USE(type); 1142 VIXL_ASSERT((type == kVabs) || (type == kVcmp) || (type == kVcmpe) || 1143 (type == kVneg) || (type == kVsqrt)); 1144 UnimplementedDelegate(type); 1145 } 1146 virtual void Delegate(InstructionType type, 1147 InstructionCondDtSSS /*instruction*/, 1148 Condition /*cond*/, 1149 DataType /*dt*/, 1150 SRegister /*rd*/, 1151 SRegister /*rn*/, 1152 SRegister /*rm*/) { 1153 USE(type); 1154 VIXL_ASSERT((type == kVadd) || (type == kVdiv) || (type == kVfma) || 1155 (type == kVfms) || (type == kVfnma) || (type == kVfnms) || 1156 (type == kVmla) || (type == kVmls) || (type == kVmul) || 1157 (type == kVnmla) || (type == kVnmls) || (type == kVnmul) || 1158 (type == kVsub)); 1159 UnimplementedDelegate(type); 1160 } 1161 virtual void Delegate(InstructionType type, 1162 InstructionCondDtDQQ /*instruction*/, 1163 Condition /*cond*/, 1164 DataType /*dt*/, 1165 DRegister /*rd*/, 1166 QRegister /*rn*/, 1167 QRegister /*rm*/) { 1168 USE(type); 1169 VIXL_ASSERT((type == kVaddhn) || (type == kVraddhn) || (type == kVrsubhn) || 1170 (type == kVsubhn)); 1171 UnimplementedDelegate(type); 1172 } 1173 virtual void Delegate(InstructionType type, 1174 InstructionCondDtQQD /*instruction*/, 1175 Condition /*cond*/, 1176 DataType /*dt*/, 1177 QRegister /*rd*/, 1178 QRegister /*rn*/, 1179 DRegister /*rm*/) { 1180 USE(type); 1181 VIXL_ASSERT((type == kVaddw) || (type == kVsubw)); 1182 UnimplementedDelegate(type); 1183 } 1184 virtual void Delegate(InstructionType type, 1185 InstructionCondDtDDDop /*instruction*/, 1186 Condition /*cond*/, 1187 DataType /*dt*/, 1188 DRegister /*rd*/, 1189 DRegister /*rn*/, 1190 const DOperand& /*operand*/) { 1191 USE(type); 1192 VIXL_ASSERT((type == kVand) || (type == kVbic) || (type == kVceq) || 1193 (type == kVcge) || (type == kVcgt) || (type == kVcle) || 1194 (type == kVclt) || (type == kVorn) || (type == kVorr) || 1195 (type == kVqshl) || (type == kVqshlu) || (type == kVrshr) || 1196 (type == kVrsra) || (type == kVshl) || (type == kVshr) || 1197 (type == kVsli) || (type == kVsra) || (type == kVsri)); 1198 UnimplementedDelegate(type); 1199 } 1200 virtual void Delegate(InstructionType type, 1201 InstructionCondDtQQQop /*instruction*/, 1202 Condition /*cond*/, 1203 DataType /*dt*/, 1204 QRegister /*rd*/, 1205 QRegister /*rn*/, 1206 const QOperand& /*operand*/) { 1207 USE(type); 1208 VIXL_ASSERT((type == kVand) || (type == kVbic) || (type == kVceq) || 1209 (type == kVcge) || (type == kVcgt) || (type == kVcle) || 1210 (type == kVclt) || (type == kVorn) || (type == kVorr) || 1211 (type == kVqshl) || (type == kVqshlu) || (type == kVrshr) || 1212 (type == kVrsra) || (type == kVshl) || (type == kVshr) || 1213 (type == kVsli) || (type == kVsra) || (type == kVsri)); 1214 UnimplementedDelegate(type); 1215 } 1216 virtual void Delegate(InstructionType type, 1217 InstructionCondDtSFi /*instruction*/, 1218 Condition /*cond*/, 1219 DataType /*dt*/, 1220 SRegister /*rd*/, 1221 double /*imm*/) { 1222 USE(type); 1223 VIXL_ASSERT((type == kVcmp) || (type == kVcmpe)); 1224 UnimplementedDelegate(type); 1225 } 1226 virtual void Delegate(InstructionType type, 1227 InstructionCondDtDFi /*instruction*/, 1228 Condition /*cond*/, 1229 DataType /*dt*/, 1230 DRegister /*rd*/, 1231 double /*imm*/) { 1232 USE(type); 1233 VIXL_ASSERT((type == kVcmp) || (type == kVcmpe)); 1234 UnimplementedDelegate(type); 1235 } 1236 virtual void Delegate(InstructionType type, 1237 InstructionCondDtDtDS /*instruction*/, 1238 Condition /*cond*/, 1239 DataType /*dt1*/, 1240 DataType /*dt2*/, 1241 DRegister /*rd*/, 1242 SRegister /*rm*/) { 1243 USE(type); 1244 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtt)); 1245 UnimplementedDelegate(type); 1246 } 1247 virtual void Delegate(InstructionType type, 1248 InstructionCondDtDtSD /*instruction*/, 1249 Condition /*cond*/, 1250 DataType /*dt1*/, 1251 DataType /*dt2*/, 1252 SRegister /*rd*/, 1253 DRegister /*rm*/) { 1254 USE(type); 1255 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtr) || 1256 (type == kVcvtt)); 1257 UnimplementedDelegate(type); 1258 } 1259 virtual void Delegate(InstructionType type, 1260 InstructionCondDtDtDDSi /*instruction*/, 1261 Condition /*cond*/, 1262 DataType /*dt1*/, 1263 DataType /*dt2*/, 1264 DRegister /*rd*/, 1265 DRegister /*rm*/, 1266 int32_t /*fbits*/) { 1267 USE(type); 1268 VIXL_ASSERT((type == kVcvt)); 1269 UnimplementedDelegate(type); 1270 } 1271 virtual void Delegate(InstructionType type, 1272 InstructionCondDtDtQQSi /*instruction*/, 1273 Condition /*cond*/, 1274 DataType /*dt1*/, 1275 DataType /*dt2*/, 1276 QRegister /*rd*/, 1277 QRegister /*rm*/, 1278 int32_t /*fbits*/) { 1279 USE(type); 1280 VIXL_ASSERT((type == kVcvt)); 1281 UnimplementedDelegate(type); 1282 } 1283 virtual void Delegate(InstructionType type, 1284 InstructionCondDtDtSSSi /*instruction*/, 1285 Condition /*cond*/, 1286 DataType /*dt1*/, 1287 DataType /*dt2*/, 1288 SRegister /*rd*/, 1289 SRegister /*rm*/, 1290 int32_t /*fbits*/) { 1291 USE(type); 1292 VIXL_ASSERT((type == kVcvt)); 1293 UnimplementedDelegate(type); 1294 } 1295 virtual void Delegate(InstructionType type, 1296 InstructionCondDtDtDD /*instruction*/, 1297 Condition /*cond*/, 1298 DataType /*dt1*/, 1299 DataType /*dt2*/, 1300 DRegister /*rd*/, 1301 DRegister /*rm*/) { 1302 USE(type); 1303 VIXL_ASSERT((type == kVcvt) || (type == kVrintr) || (type == kVrintx) || 1304 (type == kVrintz)); 1305 UnimplementedDelegate(type); 1306 } 1307 virtual void Delegate(InstructionType type, 1308 InstructionCondDtDtQQ /*instruction*/, 1309 Condition /*cond*/, 1310 DataType /*dt1*/, 1311 DataType /*dt2*/, 1312 QRegister /*rd*/, 1313 QRegister /*rm*/) { 1314 USE(type); 1315 VIXL_ASSERT((type == kVcvt)); 1316 UnimplementedDelegate(type); 1317 } 1318 virtual void Delegate(InstructionType type, 1319 InstructionCondDtDtDQ /*instruction*/, 1320 Condition /*cond*/, 1321 DataType /*dt1*/, 1322 DataType /*dt2*/, 1323 DRegister /*rd*/, 1324 QRegister /*rm*/) { 1325 USE(type); 1326 VIXL_ASSERT((type == kVcvt)); 1327 UnimplementedDelegate(type); 1328 } 1329 virtual void Delegate(InstructionType type, 1330 InstructionCondDtDtQD /*instruction*/, 1331 Condition /*cond*/, 1332 DataType /*dt1*/, 1333 DataType /*dt2*/, 1334 QRegister /*rd*/, 1335 DRegister /*rm*/) { 1336 USE(type); 1337 VIXL_ASSERT((type == kVcvt)); 1338 UnimplementedDelegate(type); 1339 } 1340 virtual void Delegate(InstructionType type, 1341 InstructionCondDtDtSS /*instruction*/, 1342 Condition /*cond*/, 1343 DataType /*dt1*/, 1344 DataType /*dt2*/, 1345 SRegister /*rd*/, 1346 SRegister /*rm*/) { 1347 USE(type); 1348 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtr) || 1349 (type == kVcvtt) || (type == kVrintr) || (type == kVrintx) || 1350 (type == kVrintz)); 1351 UnimplementedDelegate(type); 1352 } 1353 virtual void Delegate(InstructionType type, 1354 InstructionDtDtDD /*instruction*/, 1355 DataType /*dt1*/, 1356 DataType /*dt2*/, 1357 DRegister /*rd*/, 1358 DRegister /*rm*/) { 1359 USE(type); 1360 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1361 (type == kVcvtp) || (type == kVrinta) || (type == kVrintm) || 1362 (type == kVrintn) || (type == kVrintp)); 1363 UnimplementedDelegate(type); 1364 } 1365 virtual void Delegate(InstructionType type, 1366 InstructionDtDtQQ /*instruction*/, 1367 DataType /*dt1*/, 1368 DataType /*dt2*/, 1369 QRegister /*rd*/, 1370 QRegister /*rm*/) { 1371 USE(type); 1372 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1373 (type == kVcvtp) || (type == kVrinta) || (type == kVrintm) || 1374 (type == kVrintn) || (type == kVrintp) || (type == kVrintx) || 1375 (type == kVrintz)); 1376 UnimplementedDelegate(type); 1377 } 1378 virtual void Delegate(InstructionType type, 1379 InstructionDtDtSS /*instruction*/, 1380 DataType /*dt1*/, 1381 DataType /*dt2*/, 1382 SRegister /*rd*/, 1383 SRegister /*rm*/) { 1384 USE(type); 1385 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1386 (type == kVcvtp) || (type == kVrinta) || (type == kVrintm) || 1387 (type == kVrintn) || (type == kVrintp)); 1388 UnimplementedDelegate(type); 1389 } 1390 virtual void Delegate(InstructionType type, 1391 InstructionDtDtSD /*instruction*/, 1392 DataType /*dt1*/, 1393 DataType /*dt2*/, 1394 SRegister /*rd*/, 1395 DRegister /*rm*/) { 1396 USE(type); 1397 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1398 (type == kVcvtp)); 1399 UnimplementedDelegate(type); 1400 } 1401 virtual void Delegate(InstructionType type, 1402 InstructionCondDtQR /*instruction*/, 1403 Condition /*cond*/, 1404 DataType /*dt*/, 1405 QRegister /*rd*/, 1406 Register /*rt*/) { 1407 USE(type); 1408 VIXL_ASSERT((type == kVdup)); 1409 UnimplementedDelegate(type); 1410 } 1411 virtual void Delegate(InstructionType type, 1412 InstructionCondDtDR /*instruction*/, 1413 Condition /*cond*/, 1414 DataType /*dt*/, 1415 DRegister /*rd*/, 1416 Register /*rt*/) { 1417 USE(type); 1418 VIXL_ASSERT((type == kVdup)); 1419 UnimplementedDelegate(type); 1420 } 1421 virtual void Delegate(InstructionType type, 1422 InstructionCondDtDDx /*instruction*/, 1423 Condition /*cond*/, 1424 DataType /*dt*/, 1425 DRegister /*rd*/, 1426 DRegisterLane /*rm*/) { 1427 USE(type); 1428 VIXL_ASSERT((type == kVdup)); 1429 UnimplementedDelegate(type); 1430 } 1431 virtual void Delegate(InstructionType type, 1432 InstructionCondDtQDx /*instruction*/, 1433 Condition /*cond*/, 1434 DataType /*dt*/, 1435 QRegister /*rd*/, 1436 DRegisterLane /*rm*/) { 1437 USE(type); 1438 VIXL_ASSERT((type == kVdup)); 1439 UnimplementedDelegate(type); 1440 } 1441 virtual void Delegate(InstructionType type, 1442 InstructionCondDtDDDDop /*instruction*/, 1443 Condition /*cond*/, 1444 DataType /*dt*/, 1445 DRegister /*rd*/, 1446 DRegister /*rn*/, 1447 DRegister /*rm*/, 1448 const DOperand& /*operand*/) { 1449 USE(type); 1450 VIXL_ASSERT((type == kVext)); 1451 UnimplementedDelegate(type); 1452 } 1453 virtual void Delegate(InstructionType type, 1454 InstructionCondDtQQQQop /*instruction*/, 1455 Condition /*cond*/, 1456 DataType /*dt*/, 1457 QRegister /*rd*/, 1458 QRegister /*rn*/, 1459 QRegister /*rm*/, 1460 const QOperand& /*operand*/) { 1461 USE(type); 1462 VIXL_ASSERT((type == kVext)); 1463 UnimplementedDelegate(type); 1464 } 1465 virtual void Delegate(InstructionType type, 1466 InstructionCondDtNrlAmop /*instruction*/, 1467 Condition /*cond*/, 1468 DataType /*dt*/, 1469 const NeonRegisterList& /*nreglist*/, 1470 const AlignedMemOperand& /*operand*/) { 1471 USE(type); 1472 VIXL_ASSERT((type == kVld1) || (type == kVld2) || (type == kVld3) || 1473 (type == kVld4) || (type == kVst1) || (type == kVst2) || 1474 (type == kVst3) || (type == kVst4)); 1475 UnimplementedDelegate(type); 1476 } 1477 virtual void Delegate(InstructionType type, 1478 InstructionCondDtNrlMop /*instruction*/, 1479 Condition /*cond*/, 1480 DataType /*dt*/, 1481 const NeonRegisterList& /*nreglist*/, 1482 const MemOperand& /*operand*/) { 1483 USE(type); 1484 VIXL_ASSERT((type == kVld3) || (type == kVst3)); 1485 UnimplementedDelegate(type); 1486 } 1487 virtual void Delegate(InstructionType type, 1488 InstructionCondDtRwbDrl /*instruction*/, 1489 Condition /*cond*/, 1490 DataType /*dt*/, 1491 Register /*rn*/, 1492 WriteBack /*write_back*/, 1493 DRegisterList /*dreglist*/) { 1494 USE(type); 1495 VIXL_ASSERT((type == kVldm) || (type == kVldmdb) || (type == kVldmia) || 1496 (type == kVstm) || (type == kVstmdb) || (type == kVstmia)); 1497 UnimplementedDelegate(type); 1498 } 1499 virtual void Delegate(InstructionType type, 1500 InstructionCondDtRwbSrl /*instruction*/, 1501 Condition /*cond*/, 1502 DataType /*dt*/, 1503 Register /*rn*/, 1504 WriteBack /*write_back*/, 1505 SRegisterList /*sreglist*/) { 1506 USE(type); 1507 VIXL_ASSERT((type == kVldm) || (type == kVldmdb) || (type == kVldmia) || 1508 (type == kVstm) || (type == kVstmdb) || (type == kVstmia)); 1509 UnimplementedDelegate(type); 1510 } 1511 virtual void Delegate(InstructionType type, 1512 InstructionCondDtDL /*instruction*/, 1513 Condition /*cond*/, 1514 DataType /*dt*/, 1515 DRegister /*rd*/, 1516 Label* /*label*/) { 1517 USE(type); 1518 VIXL_ASSERT((type == kVldr)); 1519 UnimplementedDelegate(type); 1520 } 1521 virtual void Delegate(InstructionType type, 1522 InstructionCondDtDMop /*instruction*/, 1523 Condition /*cond*/, 1524 DataType /*dt*/, 1525 DRegister /*rd*/, 1526 const MemOperand& /*operand*/) { 1527 USE(type); 1528 VIXL_ASSERT((type == kVldr) || (type == kVstr)); 1529 UnimplementedDelegate(type); 1530 } 1531 virtual void Delegate(InstructionType type, 1532 InstructionCondDtSL /*instruction*/, 1533 Condition /*cond*/, 1534 DataType /*dt*/, 1535 SRegister /*rd*/, 1536 Label* /*label*/) { 1537 USE(type); 1538 VIXL_ASSERT((type == kVldr)); 1539 UnimplementedDelegate(type); 1540 } 1541 virtual void Delegate(InstructionType type, 1542 InstructionCondDtSMop /*instruction*/, 1543 Condition /*cond*/, 1544 DataType /*dt*/, 1545 SRegister /*rd*/, 1546 const MemOperand& /*operand*/) { 1547 USE(type); 1548 VIXL_ASSERT((type == kVldr) || (type == kVstr)); 1549 UnimplementedDelegate(type); 1550 } 1551 virtual void Delegate(InstructionType type, 1552 InstructionDtDDD /*instruction*/, 1553 DataType /*dt*/, 1554 DRegister /*rd*/, 1555 DRegister /*rn*/, 1556 DRegister /*rm*/) { 1557 USE(type); 1558 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm) || (type == kVseleq) || 1559 (type == kVselge) || (type == kVselgt) || (type == kVselvs)); 1560 UnimplementedDelegate(type); 1561 } 1562 virtual void Delegate(InstructionType type, 1563 InstructionDtSSS /*instruction*/, 1564 DataType /*dt*/, 1565 SRegister /*rd*/, 1566 SRegister /*rn*/, 1567 SRegister /*rm*/) { 1568 USE(type); 1569 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm) || (type == kVseleq) || 1570 (type == kVselge) || (type == kVselgt) || (type == kVselvs)); 1571 UnimplementedDelegate(type); 1572 } 1573 virtual void Delegate(InstructionType type, 1574 InstructionCondDtDDDx /*instruction*/, 1575 Condition /*cond*/, 1576 DataType /*dt*/, 1577 DRegister /*rd*/, 1578 DRegister /*rn*/, 1579 DRegisterLane /*rm*/) { 1580 USE(type); 1581 VIXL_ASSERT((type == kVmla) || (type == kVmls) || (type == kVqdmulh) || 1582 (type == kVqrdmulh)); 1583 UnimplementedDelegate(type); 1584 } 1585 virtual void Delegate(InstructionType type, 1586 InstructionCondDtQQDx /*instruction*/, 1587 Condition /*cond*/, 1588 DataType /*dt*/, 1589 QRegister /*rd*/, 1590 QRegister /*rn*/, 1591 DRegisterLane /*rm*/) { 1592 USE(type); 1593 VIXL_ASSERT((type == kVmla) || (type == kVmls) || (type == kVqdmulh) || 1594 (type == kVqrdmulh)); 1595 UnimplementedDelegate(type); 1596 } 1597 virtual void Delegate(InstructionType type, 1598 InstructionCondDtQDDx /*instruction*/, 1599 Condition /*cond*/, 1600 DataType /*dt*/, 1601 QRegister /*rd*/, 1602 DRegister /*rn*/, 1603 DRegisterLane /*rm*/) { 1604 USE(type); 1605 VIXL_ASSERT((type == kVmlal) || (type == kVmlsl) || (type == kVqdmull)); 1606 UnimplementedDelegate(type); 1607 } 1608 virtual void Delegate(InstructionType type, 1609 InstructionCondRS /*instruction*/, 1610 Condition /*cond*/, 1611 Register /*rt*/, 1612 SRegister /*rn*/) { 1613 USE(type); 1614 VIXL_ASSERT((type == kVmov)); 1615 UnimplementedDelegate(type); 1616 } 1617 virtual void Delegate(InstructionType type, 1618 InstructionCondSR /*instruction*/, 1619 Condition /*cond*/, 1620 SRegister /*rn*/, 1621 Register /*rt*/) { 1622 USE(type); 1623 VIXL_ASSERT((type == kVmov)); 1624 UnimplementedDelegate(type); 1625 } 1626 virtual void Delegate(InstructionType type, 1627 InstructionCondRRD /*instruction*/, 1628 Condition /*cond*/, 1629 Register /*rt*/, 1630 Register /*rt2*/, 1631 DRegister /*rm*/) { 1632 USE(type); 1633 VIXL_ASSERT((type == kVmov)); 1634 UnimplementedDelegate(type); 1635 } 1636 virtual void Delegate(InstructionType type, 1637 InstructionCondDRR /*instruction*/, 1638 Condition /*cond*/, 1639 DRegister /*rm*/, 1640 Register /*rt*/, 1641 Register /*rt2*/) { 1642 USE(type); 1643 VIXL_ASSERT((type == kVmov)); 1644 UnimplementedDelegate(type); 1645 } 1646 virtual void Delegate(InstructionType type, 1647 InstructionCondRRSS /*instruction*/, 1648 Condition /*cond*/, 1649 Register /*rt*/, 1650 Register /*rt2*/, 1651 SRegister /*rm*/, 1652 SRegister /*rm1*/) { 1653 USE(type); 1654 VIXL_ASSERT((type == kVmov)); 1655 UnimplementedDelegate(type); 1656 } 1657 virtual void Delegate(InstructionType type, 1658 InstructionCondSSRR /*instruction*/, 1659 Condition /*cond*/, 1660 SRegister /*rm*/, 1661 SRegister /*rm1*/, 1662 Register /*rt*/, 1663 Register /*rt2*/) { 1664 USE(type); 1665 VIXL_ASSERT((type == kVmov)); 1666 UnimplementedDelegate(type); 1667 } 1668 virtual void Delegate(InstructionType type, 1669 InstructionCondDtDxR /*instruction*/, 1670 Condition /*cond*/, 1671 DataType /*dt*/, 1672 DRegisterLane /*rd*/, 1673 Register /*rt*/) { 1674 USE(type); 1675 VIXL_ASSERT((type == kVmov)); 1676 UnimplementedDelegate(type); 1677 } 1678 virtual void Delegate(InstructionType type, 1679 InstructionCondDtDDop /*instruction*/, 1680 Condition /*cond*/, 1681 DataType /*dt*/, 1682 DRegister /*rd*/, 1683 const DOperand& /*operand*/) { 1684 USE(type); 1685 VIXL_ASSERT((type == kVmov) || (type == kVmvn)); 1686 UnimplementedDelegate(type); 1687 } 1688 virtual void Delegate(InstructionType type, 1689 InstructionCondDtQQop /*instruction*/, 1690 Condition /*cond*/, 1691 DataType /*dt*/, 1692 QRegister /*rd*/, 1693 const QOperand& /*operand*/) { 1694 USE(type); 1695 VIXL_ASSERT((type == kVmov) || (type == kVmvn)); 1696 UnimplementedDelegate(type); 1697 } 1698 virtual void Delegate(InstructionType type, 1699 InstructionCondDtSSop /*instruction*/, 1700 Condition /*cond*/, 1701 DataType /*dt*/, 1702 SRegister /*rd*/, 1703 const SOperand& /*operand*/) { 1704 USE(type); 1705 VIXL_ASSERT((type == kVmov)); 1706 UnimplementedDelegate(type); 1707 } 1708 virtual void Delegate(InstructionType type, 1709 InstructionCondDtRDx /*instruction*/, 1710 Condition /*cond*/, 1711 DataType /*dt*/, 1712 Register /*rt*/, 1713 DRegisterLane /*rn*/) { 1714 USE(type); 1715 VIXL_ASSERT((type == kVmov)); 1716 UnimplementedDelegate(type); 1717 } 1718 virtual void Delegate(InstructionType type, 1719 InstructionCondDtQD /*instruction*/, 1720 Condition /*cond*/, 1721 DataType /*dt*/, 1722 QRegister /*rd*/, 1723 DRegister /*rm*/) { 1724 USE(type); 1725 VIXL_ASSERT((type == kVmovl)); 1726 UnimplementedDelegate(type); 1727 } 1728 virtual void Delegate(InstructionType type, 1729 InstructionCondDtDQ /*instruction*/, 1730 Condition /*cond*/, 1731 DataType /*dt*/, 1732 DRegister /*rd*/, 1733 QRegister /*rm*/) { 1734 USE(type); 1735 VIXL_ASSERT((type == kVmovn) || (type == kVqmovn) || (type == kVqmovun)); 1736 UnimplementedDelegate(type); 1737 } 1738 virtual void Delegate(InstructionType type, 1739 InstructionCondRoaSfp /*instruction*/, 1740 Condition /*cond*/, 1741 RegisterOrAPSR_nzcv /*rt*/, 1742 SpecialFPRegister /*spec_reg*/) { 1743 USE(type); 1744 VIXL_ASSERT((type == kVmrs)); 1745 UnimplementedDelegate(type); 1746 } 1747 virtual void Delegate(InstructionType type, 1748 InstructionCondSfpR /*instruction*/, 1749 Condition /*cond*/, 1750 SpecialFPRegister /*spec_reg*/, 1751 Register /*rt*/) { 1752 USE(type); 1753 VIXL_ASSERT((type == kVmsr)); 1754 UnimplementedDelegate(type); 1755 } 1756 virtual void Delegate(InstructionType type, 1757 InstructionCondDtDDIr /*instruction*/, 1758 Condition /*cond*/, 1759 DataType /*dt*/, 1760 DRegister /*rd*/, 1761 DRegister /*rn*/, 1762 DRegister /*dm*/, 1763 unsigned /*index*/) { 1764 USE(type); 1765 VIXL_ASSERT((type == kVmul)); 1766 UnimplementedDelegate(type); 1767 } 1768 virtual void Delegate(InstructionType type, 1769 InstructionCondDtQQIr /*instruction*/, 1770 Condition /*cond*/, 1771 DataType /*dt*/, 1772 QRegister /*rd*/, 1773 QRegister /*rn*/, 1774 DRegister /*dm*/, 1775 unsigned /*index*/) { 1776 USE(type); 1777 VIXL_ASSERT((type == kVmul)); 1778 UnimplementedDelegate(type); 1779 } 1780 virtual void Delegate(InstructionType type, 1781 InstructionCondDtQDIr /*instruction*/, 1782 Condition /*cond*/, 1783 DataType /*dt*/, 1784 QRegister /*rd*/, 1785 DRegister /*rn*/, 1786 DRegister /*dm*/, 1787 unsigned /*index*/) { 1788 USE(type); 1789 VIXL_ASSERT((type == kVmull) || (type == kVqdmlal) || (type == kVqdmlsl)); 1790 UnimplementedDelegate(type); 1791 } 1792 virtual void Delegate(InstructionType type, 1793 InstructionCondDtDrl /*instruction*/, 1794 Condition /*cond*/, 1795 DataType /*dt*/, 1796 DRegisterList /*dreglist*/) { 1797 USE(type); 1798 VIXL_ASSERT((type == kVpop) || (type == kVpush)); 1799 UnimplementedDelegate(type); 1800 } 1801 virtual void Delegate(InstructionType type, 1802 InstructionCondDtSrl /*instruction*/, 1803 Condition /*cond*/, 1804 DataType /*dt*/, 1805 SRegisterList /*sreglist*/) { 1806 USE(type); 1807 VIXL_ASSERT((type == kVpop) || (type == kVpush)); 1808 UnimplementedDelegate(type); 1809 } 1810 virtual void Delegate(InstructionType type, 1811 InstructionCondDtDQQop /*instruction*/, 1812 Condition /*cond*/, 1813 DataType /*dt*/, 1814 DRegister /*rd*/, 1815 QRegister /*rm*/, 1816 const QOperand& /*operand*/) { 1817 USE(type); 1818 VIXL_ASSERT((type == kVqrshrn) || (type == kVqrshrun) || 1819 (type == kVqshrn) || (type == kVqshrun) || (type == kVrshrn) || 1820 (type == kVshrn)); 1821 UnimplementedDelegate(type); 1822 } 1823 virtual void Delegate(InstructionType type, 1824 InstructionCondDtQDDop /*instruction*/, 1825 Condition /*cond*/, 1826 DataType /*dt*/, 1827 QRegister /*rd*/, 1828 DRegister /*rm*/, 1829 const DOperand& /*operand*/) { 1830 USE(type); 1831 VIXL_ASSERT((type == kVshll)); 1832 UnimplementedDelegate(type); 1833 } 1834 virtual void Delegate(InstructionType type, 1835 InstructionCondDtDNrlD /*instruction*/, 1836 Condition /*cond*/, 1837 DataType /*dt*/, 1838 DRegister /*rd*/, 1839 const NeonRegisterList& /*nreglist*/, 1840 DRegister /*rm*/) { 1841 USE(type); 1842 VIXL_ASSERT((type == kVtbl) || (type == kVtbx)); 1843 UnimplementedDelegate(type); 1844 } 1845 1846 void adc(Condition cond, 1847 EncodingSize size, 1848 Register rd, 1849 Register rn, 1850 const Operand& operand); 1851 void adc(Register rd, Register rn, const Operand& operand) { 1852 adc(al, Best, rd, rn, operand); 1853 } 1854 void adc(Condition cond, Register rd, Register rn, const Operand& operand) { 1855 adc(cond, Best, rd, rn, operand); 1856 } 1857 void adc(EncodingSize size, 1858 Register rd, 1859 Register rn, 1860 const Operand& operand) { 1861 adc(al, size, rd, rn, operand); 1862 } 1863 1864 void adcs(Condition cond, 1865 EncodingSize size, 1866 Register rd, 1867 Register rn, 1868 const Operand& operand); 1869 void adcs(Register rd, Register rn, const Operand& operand) { 1870 adcs(al, Best, rd, rn, operand); 1871 } 1872 void adcs(Condition cond, Register rd, Register rn, const Operand& operand) { 1873 adcs(cond, Best, rd, rn, operand); 1874 } 1875 void adcs(EncodingSize size, 1876 Register rd, 1877 Register rn, 1878 const Operand& operand) { 1879 adcs(al, size, rd, rn, operand); 1880 } 1881 1882 void add(Condition cond, 1883 EncodingSize size, 1884 Register rd, 1885 Register rn, 1886 const Operand& operand); 1887 void add(Register rd, Register rn, const Operand& operand) { 1888 add(al, Best, rd, rn, operand); 1889 } 1890 void add(Condition cond, Register rd, Register rn, const Operand& operand) { 1891 add(cond, Best, rd, rn, operand); 1892 } 1893 void add(EncodingSize size, 1894 Register rd, 1895 Register rn, 1896 const Operand& operand) { 1897 add(al, size, rd, rn, operand); 1898 } 1899 1900 void add(Condition cond, Register rd, const Operand& operand); 1901 void add(Register rd, const Operand& operand) { add(al, rd, operand); } 1902 1903 void adds(Condition cond, 1904 EncodingSize size, 1905 Register rd, 1906 Register rn, 1907 const Operand& operand); 1908 void adds(Register rd, Register rn, const Operand& operand) { 1909 adds(al, Best, rd, rn, operand); 1910 } 1911 void adds(Condition cond, Register rd, Register rn, const Operand& operand) { 1912 adds(cond, Best, rd, rn, operand); 1913 } 1914 void adds(EncodingSize size, 1915 Register rd, 1916 Register rn, 1917 const Operand& operand) { 1918 adds(al, size, rd, rn, operand); 1919 } 1920 1921 void adds(Register rd, const Operand& operand); 1922 1923 void addw(Condition cond, Register rd, Register rn, const Operand& operand); 1924 void addw(Register rd, Register rn, const Operand& operand) { 1925 addw(al, rd, rn, operand); 1926 } 1927 1928 void adr(Condition cond, EncodingSize size, Register rd, Label* label); 1929 void adr(Register rd, Label* label) { adr(al, Best, rd, label); } 1930 void adr(Condition cond, Register rd, Label* label) { 1931 adr(cond, Best, rd, label); 1932 } 1933 void adr(EncodingSize size, Register rd, Label* label) { 1934 adr(al, size, rd, label); 1935 } 1936 1937 void and_(Condition cond, 1938 EncodingSize size, 1939 Register rd, 1940 Register rn, 1941 const Operand& operand); 1942 void and_(Register rd, Register rn, const Operand& operand) { 1943 and_(al, Best, rd, rn, operand); 1944 } 1945 void and_(Condition cond, Register rd, Register rn, const Operand& operand) { 1946 and_(cond, Best, rd, rn, operand); 1947 } 1948 void and_(EncodingSize size, 1949 Register rd, 1950 Register rn, 1951 const Operand& operand) { 1952 and_(al, size, rd, rn, operand); 1953 } 1954 1955 void ands(Condition cond, 1956 EncodingSize size, 1957 Register rd, 1958 Register rn, 1959 const Operand& operand); 1960 void ands(Register rd, Register rn, const Operand& operand) { 1961 ands(al, Best, rd, rn, operand); 1962 } 1963 void ands(Condition cond, Register rd, Register rn, const Operand& operand) { 1964 ands(cond, Best, rd, rn, operand); 1965 } 1966 void ands(EncodingSize size, 1967 Register rd, 1968 Register rn, 1969 const Operand& operand) { 1970 ands(al, size, rd, rn, operand); 1971 } 1972 1973 void asr(Condition cond, 1974 EncodingSize size, 1975 Register rd, 1976 Register rm, 1977 const Operand& operand); 1978 void asr(Register rd, Register rm, const Operand& operand) { 1979 asr(al, Best, rd, rm, operand); 1980 } 1981 void asr(Condition cond, Register rd, Register rm, const Operand& operand) { 1982 asr(cond, Best, rd, rm, operand); 1983 } 1984 void asr(EncodingSize size, 1985 Register rd, 1986 Register rm, 1987 const Operand& operand) { 1988 asr(al, size, rd, rm, operand); 1989 } 1990 1991 void asrs(Condition cond, 1992 EncodingSize size, 1993 Register rd, 1994 Register rm, 1995 const Operand& operand); 1996 void asrs(Register rd, Register rm, const Operand& operand) { 1997 asrs(al, Best, rd, rm, operand); 1998 } 1999 void asrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2000 asrs(cond, Best, rd, rm, operand); 2001 } 2002 void asrs(EncodingSize size, 2003 Register rd, 2004 Register rm, 2005 const Operand& operand) { 2006 asrs(al, size, rd, rm, operand); 2007 } 2008 2009 void b(Condition cond, EncodingSize size, Label* label); 2010 void b(Label* label) { b(al, Best, label); } 2011 void b(Condition cond, Label* label) { b(cond, Best, label); } 2012 void b(EncodingSize size, Label* label) { b(al, size, label); } 2013 2014 void bfc(Condition cond, Register rd, uint32_t lsb, const Operand& operand); 2015 void bfc(Register rd, uint32_t lsb, const Operand& operand) { 2016 bfc(al, rd, lsb, operand); 2017 } 2018 2019 void bfi(Condition cond, 2020 Register rd, 2021 Register rn, 2022 uint32_t lsb, 2023 const Operand& operand); 2024 void bfi(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 2025 bfi(al, rd, rn, lsb, operand); 2026 } 2027 2028 void bic(Condition cond, 2029 EncodingSize size, 2030 Register rd, 2031 Register rn, 2032 const Operand& operand); 2033 void bic(Register rd, Register rn, const Operand& operand) { 2034 bic(al, Best, rd, rn, operand); 2035 } 2036 void bic(Condition cond, Register rd, Register rn, const Operand& operand) { 2037 bic(cond, Best, rd, rn, operand); 2038 } 2039 void bic(EncodingSize size, 2040 Register rd, 2041 Register rn, 2042 const Operand& operand) { 2043 bic(al, size, rd, rn, operand); 2044 } 2045 2046 void bics(Condition cond, 2047 EncodingSize size, 2048 Register rd, 2049 Register rn, 2050 const Operand& operand); 2051 void bics(Register rd, Register rn, const Operand& operand) { 2052 bics(al, Best, rd, rn, operand); 2053 } 2054 void bics(Condition cond, Register rd, Register rn, const Operand& operand) { 2055 bics(cond, Best, rd, rn, operand); 2056 } 2057 void bics(EncodingSize size, 2058 Register rd, 2059 Register rn, 2060 const Operand& operand) { 2061 bics(al, size, rd, rn, operand); 2062 } 2063 2064 void bkpt(Condition cond, uint32_t imm); 2065 void bkpt(uint32_t imm) { bkpt(al, imm); } 2066 2067 void bl(Condition cond, Label* label); 2068 void bl(Label* label) { bl(al, label); } 2069 2070 void blx(Condition cond, Label* label); 2071 void blx(Label* label) { blx(al, label); } 2072 2073 void blx(Condition cond, Register rm); 2074 void blx(Register rm) { blx(al, rm); } 2075 2076 void bx(Condition cond, Register rm); 2077 void bx(Register rm) { bx(al, rm); } 2078 2079 void bxj(Condition cond, Register rm); 2080 void bxj(Register rm) { bxj(al, rm); } 2081 2082 void cbnz(Register rn, Label* label); 2083 2084 void cbz(Register rn, Label* label); 2085 2086 void clrex(Condition cond); 2087 void clrex() { clrex(al); } 2088 2089 void clz(Condition cond, Register rd, Register rm); 2090 void clz(Register rd, Register rm) { clz(al, rd, rm); } 2091 2092 void cmn(Condition cond, 2093 EncodingSize size, 2094 Register rn, 2095 const Operand& operand); 2096 void cmn(Register rn, const Operand& operand) { cmn(al, Best, rn, operand); } 2097 void cmn(Condition cond, Register rn, const Operand& operand) { 2098 cmn(cond, Best, rn, operand); 2099 } 2100 void cmn(EncodingSize size, Register rn, const Operand& operand) { 2101 cmn(al, size, rn, operand); 2102 } 2103 2104 void cmp(Condition cond, 2105 EncodingSize size, 2106 Register rn, 2107 const Operand& operand); 2108 void cmp(Register rn, const Operand& operand) { cmp(al, Best, rn, operand); } 2109 void cmp(Condition cond, Register rn, const Operand& operand) { 2110 cmp(cond, Best, rn, operand); 2111 } 2112 void cmp(EncodingSize size, Register rn, const Operand& operand) { 2113 cmp(al, size, rn, operand); 2114 } 2115 2116 void crc32b(Condition cond, Register rd, Register rn, Register rm); 2117 void crc32b(Register rd, Register rn, Register rm) { crc32b(al, rd, rn, rm); } 2118 2119 void crc32cb(Condition cond, Register rd, Register rn, Register rm); 2120 void crc32cb(Register rd, Register rn, Register rm) { 2121 crc32cb(al, rd, rn, rm); 2122 } 2123 2124 void crc32ch(Condition cond, Register rd, Register rn, Register rm); 2125 void crc32ch(Register rd, Register rn, Register rm) { 2126 crc32ch(al, rd, rn, rm); 2127 } 2128 2129 void crc32cw(Condition cond, Register rd, Register rn, Register rm); 2130 void crc32cw(Register rd, Register rn, Register rm) { 2131 crc32cw(al, rd, rn, rm); 2132 } 2133 2134 void crc32h(Condition cond, Register rd, Register rn, Register rm); 2135 void crc32h(Register rd, Register rn, Register rm) { crc32h(al, rd, rn, rm); } 2136 2137 void crc32w(Condition cond, Register rd, Register rn, Register rm); 2138 void crc32w(Register rd, Register rn, Register rm) { crc32w(al, rd, rn, rm); } 2139 2140 void dmb(Condition cond, MemoryBarrier option); 2141 void dmb(MemoryBarrier option) { dmb(al, option); } 2142 2143 void dsb(Condition cond, MemoryBarrier option); 2144 void dsb(MemoryBarrier option) { dsb(al, option); } 2145 2146 void eor(Condition cond, 2147 EncodingSize size, 2148 Register rd, 2149 Register rn, 2150 const Operand& operand); 2151 void eor(Register rd, Register rn, const Operand& operand) { 2152 eor(al, Best, rd, rn, operand); 2153 } 2154 void eor(Condition cond, Register rd, Register rn, const Operand& operand) { 2155 eor(cond, Best, rd, rn, operand); 2156 } 2157 void eor(EncodingSize size, 2158 Register rd, 2159 Register rn, 2160 const Operand& operand) { 2161 eor(al, size, rd, rn, operand); 2162 } 2163 2164 void eors(Condition cond, 2165 EncodingSize size, 2166 Register rd, 2167 Register rn, 2168 const Operand& operand); 2169 void eors(Register rd, Register rn, const Operand& operand) { 2170 eors(al, Best, rd, rn, operand); 2171 } 2172 void eors(Condition cond, Register rd, Register rn, const Operand& operand) { 2173 eors(cond, Best, rd, rn, operand); 2174 } 2175 void eors(EncodingSize size, 2176 Register rd, 2177 Register rn, 2178 const Operand& operand) { 2179 eors(al, size, rd, rn, operand); 2180 } 2181 2182 void fldmdbx(Condition cond, 2183 Register rn, 2184 WriteBack write_back, 2185 DRegisterList dreglist); 2186 void fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 2187 fldmdbx(al, rn, write_back, dreglist); 2188 } 2189 2190 void fldmiax(Condition cond, 2191 Register rn, 2192 WriteBack write_back, 2193 DRegisterList dreglist); 2194 void fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 2195 fldmiax(al, rn, write_back, dreglist); 2196 } 2197 2198 void fstmdbx(Condition cond, 2199 Register rn, 2200 WriteBack write_back, 2201 DRegisterList dreglist); 2202 void fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 2203 fstmdbx(al, rn, write_back, dreglist); 2204 } 2205 2206 void fstmiax(Condition cond, 2207 Register rn, 2208 WriteBack write_back, 2209 DRegisterList dreglist); 2210 void fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 2211 fstmiax(al, rn, write_back, dreglist); 2212 } 2213 2214 void hlt(Condition cond, uint32_t imm); 2215 void hlt(uint32_t imm) { hlt(al, imm); } 2216 2217 void hvc(Condition cond, uint32_t imm); 2218 void hvc(uint32_t imm) { hvc(al, imm); } 2219 2220 void isb(Condition cond, MemoryBarrier option); 2221 void isb(MemoryBarrier option) { isb(al, option); } 2222 2223 void it(Condition cond, uint16_t mask); 2224 2225 void lda(Condition cond, Register rt, const MemOperand& operand); 2226 void lda(Register rt, const MemOperand& operand) { lda(al, rt, operand); } 2227 2228 void ldab(Condition cond, Register rt, const MemOperand& operand); 2229 void ldab(Register rt, const MemOperand& operand) { ldab(al, rt, operand); } 2230 2231 void ldaex(Condition cond, Register rt, const MemOperand& operand); 2232 void ldaex(Register rt, const MemOperand& operand) { ldaex(al, rt, operand); } 2233 2234 void ldaexb(Condition cond, Register rt, const MemOperand& operand); 2235 void ldaexb(Register rt, const MemOperand& operand) { 2236 ldaexb(al, rt, operand); 2237 } 2238 2239 void ldaexd(Condition cond, 2240 Register rt, 2241 Register rt2, 2242 const MemOperand& operand); 2243 void ldaexd(Register rt, Register rt2, const MemOperand& operand) { 2244 ldaexd(al, rt, rt2, operand); 2245 } 2246 2247 void ldaexh(Condition cond, Register rt, const MemOperand& operand); 2248 void ldaexh(Register rt, const MemOperand& operand) { 2249 ldaexh(al, rt, operand); 2250 } 2251 2252 void ldah(Condition cond, Register rt, const MemOperand& operand); 2253 void ldah(Register rt, const MemOperand& operand) { ldah(al, rt, operand); } 2254 2255 void ldm(Condition cond, 2256 EncodingSize size, 2257 Register rn, 2258 WriteBack write_back, 2259 RegisterList registers); 2260 void ldm(Register rn, WriteBack write_back, RegisterList registers) { 2261 ldm(al, Best, rn, write_back, registers); 2262 } 2263 void ldm(Condition cond, 2264 Register rn, 2265 WriteBack write_back, 2266 RegisterList registers) { 2267 ldm(cond, Best, rn, write_back, registers); 2268 } 2269 void ldm(EncodingSize size, 2270 Register rn, 2271 WriteBack write_back, 2272 RegisterList registers) { 2273 ldm(al, size, rn, write_back, registers); 2274 } 2275 2276 void ldmda(Condition cond, 2277 Register rn, 2278 WriteBack write_back, 2279 RegisterList registers); 2280 void ldmda(Register rn, WriteBack write_back, RegisterList registers) { 2281 ldmda(al, rn, write_back, registers); 2282 } 2283 2284 void ldmdb(Condition cond, 2285 Register rn, 2286 WriteBack write_back, 2287 RegisterList registers); 2288 void ldmdb(Register rn, WriteBack write_back, RegisterList registers) { 2289 ldmdb(al, rn, write_back, registers); 2290 } 2291 2292 void ldmea(Condition cond, 2293 Register rn, 2294 WriteBack write_back, 2295 RegisterList registers); 2296 void ldmea(Register rn, WriteBack write_back, RegisterList registers) { 2297 ldmea(al, rn, write_back, registers); 2298 } 2299 2300 void ldmed(Condition cond, 2301 Register rn, 2302 WriteBack write_back, 2303 RegisterList registers); 2304 void ldmed(Register rn, WriteBack write_back, RegisterList registers) { 2305 ldmed(al, rn, write_back, registers); 2306 } 2307 2308 void ldmfa(Condition cond, 2309 Register rn, 2310 WriteBack write_back, 2311 RegisterList registers); 2312 void ldmfa(Register rn, WriteBack write_back, RegisterList registers) { 2313 ldmfa(al, rn, write_back, registers); 2314 } 2315 2316 void ldmfd(Condition cond, 2317 EncodingSize size, 2318 Register rn, 2319 WriteBack write_back, 2320 RegisterList registers); 2321 void ldmfd(Register rn, WriteBack write_back, RegisterList registers) { 2322 ldmfd(al, Best, rn, write_back, registers); 2323 } 2324 void ldmfd(Condition cond, 2325 Register rn, 2326 WriteBack write_back, 2327 RegisterList registers) { 2328 ldmfd(cond, Best, rn, write_back, registers); 2329 } 2330 void ldmfd(EncodingSize size, 2331 Register rn, 2332 WriteBack write_back, 2333 RegisterList registers) { 2334 ldmfd(al, size, rn, write_back, registers); 2335 } 2336 2337 void ldmib(Condition cond, 2338 Register rn, 2339 WriteBack write_back, 2340 RegisterList registers); 2341 void ldmib(Register rn, WriteBack write_back, RegisterList registers) { 2342 ldmib(al, rn, write_back, registers); 2343 } 2344 2345 void ldr(Condition cond, 2346 EncodingSize size, 2347 Register rt, 2348 const MemOperand& operand); 2349 void ldr(Register rt, const MemOperand& operand) { 2350 ldr(al, Best, rt, operand); 2351 } 2352 void ldr(Condition cond, Register rt, const MemOperand& operand) { 2353 ldr(cond, Best, rt, operand); 2354 } 2355 void ldr(EncodingSize size, Register rt, const MemOperand& operand) { 2356 ldr(al, size, rt, operand); 2357 } 2358 2359 void ldr(Condition cond, EncodingSize size, Register rt, Label* label); 2360 void ldr(Register rt, Label* label) { ldr(al, Best, rt, label); } 2361 void ldr(Condition cond, Register rt, Label* label) { 2362 ldr(cond, Best, rt, label); 2363 } 2364 void ldr(EncodingSize size, Register rt, Label* label) { 2365 ldr(al, size, rt, label); 2366 } 2367 2368 void ldrb(Condition cond, 2369 EncodingSize size, 2370 Register rt, 2371 const MemOperand& operand); 2372 void ldrb(Register rt, const MemOperand& operand) { 2373 ldrb(al, Best, rt, operand); 2374 } 2375 void ldrb(Condition cond, Register rt, const MemOperand& operand) { 2376 ldrb(cond, Best, rt, operand); 2377 } 2378 void ldrb(EncodingSize size, Register rt, const MemOperand& operand) { 2379 ldrb(al, size, rt, operand); 2380 } 2381 2382 void ldrb(Condition cond, Register rt, Label* label); 2383 void ldrb(Register rt, Label* label) { ldrb(al, rt, label); } 2384 2385 void ldrd(Condition cond, 2386 Register rt, 2387 Register rt2, 2388 const MemOperand& operand); 2389 void ldrd(Register rt, Register rt2, const MemOperand& operand) { 2390 ldrd(al, rt, rt2, operand); 2391 } 2392 2393 void ldrd(Condition cond, Register rt, Register rt2, Label* label); 2394 void ldrd(Register rt, Register rt2, Label* label) { 2395 ldrd(al, rt, rt2, label); 2396 } 2397 2398 void ldrex(Condition cond, Register rt, const MemOperand& operand); 2399 void ldrex(Register rt, const MemOperand& operand) { ldrex(al, rt, operand); } 2400 2401 void ldrexb(Condition cond, Register rt, const MemOperand& operand); 2402 void ldrexb(Register rt, const MemOperand& operand) { 2403 ldrexb(al, rt, operand); 2404 } 2405 2406 void ldrexd(Condition cond, 2407 Register rt, 2408 Register rt2, 2409 const MemOperand& operand); 2410 void ldrexd(Register rt, Register rt2, const MemOperand& operand) { 2411 ldrexd(al, rt, rt2, operand); 2412 } 2413 2414 void ldrexh(Condition cond, Register rt, const MemOperand& operand); 2415 void ldrexh(Register rt, const MemOperand& operand) { 2416 ldrexh(al, rt, operand); 2417 } 2418 2419 void ldrh(Condition cond, 2420 EncodingSize size, 2421 Register rt, 2422 const MemOperand& operand); 2423 void ldrh(Register rt, const MemOperand& operand) { 2424 ldrh(al, Best, rt, operand); 2425 } 2426 void ldrh(Condition cond, Register rt, const MemOperand& operand) { 2427 ldrh(cond, Best, rt, operand); 2428 } 2429 void ldrh(EncodingSize size, Register rt, const MemOperand& operand) { 2430 ldrh(al, size, rt, operand); 2431 } 2432 2433 void ldrh(Condition cond, Register rt, Label* label); 2434 void ldrh(Register rt, Label* label) { ldrh(al, rt, label); } 2435 2436 void ldrsb(Condition cond, 2437 EncodingSize size, 2438 Register rt, 2439 const MemOperand& operand); 2440 void ldrsb(Register rt, const MemOperand& operand) { 2441 ldrsb(al, Best, rt, operand); 2442 } 2443 void ldrsb(Condition cond, Register rt, const MemOperand& operand) { 2444 ldrsb(cond, Best, rt, operand); 2445 } 2446 void ldrsb(EncodingSize size, Register rt, const MemOperand& operand) { 2447 ldrsb(al, size, rt, operand); 2448 } 2449 2450 void ldrsb(Condition cond, Register rt, Label* label); 2451 void ldrsb(Register rt, Label* label) { ldrsb(al, rt, label); } 2452 2453 void ldrsh(Condition cond, 2454 EncodingSize size, 2455 Register rt, 2456 const MemOperand& operand); 2457 void ldrsh(Register rt, const MemOperand& operand) { 2458 ldrsh(al, Best, rt, operand); 2459 } 2460 void ldrsh(Condition cond, Register rt, const MemOperand& operand) { 2461 ldrsh(cond, Best, rt, operand); 2462 } 2463 void ldrsh(EncodingSize size, Register rt, const MemOperand& operand) { 2464 ldrsh(al, size, rt, operand); 2465 } 2466 2467 void ldrsh(Condition cond, Register rt, Label* label); 2468 void ldrsh(Register rt, Label* label) { ldrsh(al, rt, label); } 2469 2470 void lsl(Condition cond, 2471 EncodingSize size, 2472 Register rd, 2473 Register rm, 2474 const Operand& operand); 2475 void lsl(Register rd, Register rm, const Operand& operand) { 2476 lsl(al, Best, rd, rm, operand); 2477 } 2478 void lsl(Condition cond, Register rd, Register rm, const Operand& operand) { 2479 lsl(cond, Best, rd, rm, operand); 2480 } 2481 void lsl(EncodingSize size, 2482 Register rd, 2483 Register rm, 2484 const Operand& operand) { 2485 lsl(al, size, rd, rm, operand); 2486 } 2487 2488 void lsls(Condition cond, 2489 EncodingSize size, 2490 Register rd, 2491 Register rm, 2492 const Operand& operand); 2493 void lsls(Register rd, Register rm, const Operand& operand) { 2494 lsls(al, Best, rd, rm, operand); 2495 } 2496 void lsls(Condition cond, Register rd, Register rm, const Operand& operand) { 2497 lsls(cond, Best, rd, rm, operand); 2498 } 2499 void lsls(EncodingSize size, 2500 Register rd, 2501 Register rm, 2502 const Operand& operand) { 2503 lsls(al, size, rd, rm, operand); 2504 } 2505 2506 void lsr(Condition cond, 2507 EncodingSize size, 2508 Register rd, 2509 Register rm, 2510 const Operand& operand); 2511 void lsr(Register rd, Register rm, const Operand& operand) { 2512 lsr(al, Best, rd, rm, operand); 2513 } 2514 void lsr(Condition cond, Register rd, Register rm, const Operand& operand) { 2515 lsr(cond, Best, rd, rm, operand); 2516 } 2517 void lsr(EncodingSize size, 2518 Register rd, 2519 Register rm, 2520 const Operand& operand) { 2521 lsr(al, size, rd, rm, operand); 2522 } 2523 2524 void lsrs(Condition cond, 2525 EncodingSize size, 2526 Register rd, 2527 Register rm, 2528 const Operand& operand); 2529 void lsrs(Register rd, Register rm, const Operand& operand) { 2530 lsrs(al, Best, rd, rm, operand); 2531 } 2532 void lsrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2533 lsrs(cond, Best, rd, rm, operand); 2534 } 2535 void lsrs(EncodingSize size, 2536 Register rd, 2537 Register rm, 2538 const Operand& operand) { 2539 lsrs(al, size, rd, rm, operand); 2540 } 2541 2542 void mla(Condition cond, Register rd, Register rn, Register rm, Register ra); 2543 void mla(Register rd, Register rn, Register rm, Register ra) { 2544 mla(al, rd, rn, rm, ra); 2545 } 2546 2547 void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra); 2548 void mlas(Register rd, Register rn, Register rm, Register ra) { 2549 mlas(al, rd, rn, rm, ra); 2550 } 2551 2552 void mls(Condition cond, Register rd, Register rn, Register rm, Register ra); 2553 void mls(Register rd, Register rn, Register rm, Register ra) { 2554 mls(al, rd, rn, rm, ra); 2555 } 2556 2557 void mov(Condition cond, 2558 EncodingSize size, 2559 Register rd, 2560 const Operand& operand); 2561 void mov(Register rd, const Operand& operand) { mov(al, Best, rd, operand); } 2562 void mov(Condition cond, Register rd, const Operand& operand) { 2563 mov(cond, Best, rd, operand); 2564 } 2565 void mov(EncodingSize size, Register rd, const Operand& operand) { 2566 mov(al, size, rd, operand); 2567 } 2568 2569 void movs(Condition cond, 2570 EncodingSize size, 2571 Register rd, 2572 const Operand& operand); 2573 void movs(Register rd, const Operand& operand) { 2574 movs(al, Best, rd, operand); 2575 } 2576 void movs(Condition cond, Register rd, const Operand& operand) { 2577 movs(cond, Best, rd, operand); 2578 } 2579 void movs(EncodingSize size, Register rd, const Operand& operand) { 2580 movs(al, size, rd, operand); 2581 } 2582 2583 void movt(Condition cond, Register rd, const Operand& operand); 2584 void movt(Register rd, const Operand& operand) { movt(al, rd, operand); } 2585 2586 void movw(Condition cond, Register rd, const Operand& operand); 2587 void movw(Register rd, const Operand& operand) { movw(al, rd, operand); } 2588 2589 void mrs(Condition cond, Register rd, SpecialRegister spec_reg); 2590 void mrs(Register rd, SpecialRegister spec_reg) { mrs(al, rd, spec_reg); } 2591 2592 void msr(Condition cond, 2593 MaskedSpecialRegister spec_reg, 2594 const Operand& operand); 2595 void msr(MaskedSpecialRegister spec_reg, const Operand& operand) { 2596 msr(al, spec_reg, operand); 2597 } 2598 2599 void mul( 2600 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); 2601 void mul(Register rd, Register rn, Register rm) { mul(al, Best, rd, rn, rm); } 2602 void mul(Condition cond, Register rd, Register rn, Register rm) { 2603 mul(cond, Best, rd, rn, rm); 2604 } 2605 void mul(EncodingSize size, Register rd, Register rn, Register rm) { 2606 mul(al, size, rd, rn, rm); 2607 } 2608 2609 void muls(Condition cond, Register rd, Register rn, Register rm); 2610 void muls(Register rd, Register rn, Register rm) { muls(al, rd, rn, rm); } 2611 2612 void mvn(Condition cond, 2613 EncodingSize size, 2614 Register rd, 2615 const Operand& operand); 2616 void mvn(Register rd, const Operand& operand) { mvn(al, Best, rd, operand); } 2617 void mvn(Condition cond, Register rd, const Operand& operand) { 2618 mvn(cond, Best, rd, operand); 2619 } 2620 void mvn(EncodingSize size, Register rd, const Operand& operand) { 2621 mvn(al, size, rd, operand); 2622 } 2623 2624 void mvns(Condition cond, 2625 EncodingSize size, 2626 Register rd, 2627 const Operand& operand); 2628 void mvns(Register rd, const Operand& operand) { 2629 mvns(al, Best, rd, operand); 2630 } 2631 void mvns(Condition cond, Register rd, const Operand& operand) { 2632 mvns(cond, Best, rd, operand); 2633 } 2634 void mvns(EncodingSize size, Register rd, const Operand& operand) { 2635 mvns(al, size, rd, operand); 2636 } 2637 2638 void nop(Condition cond, EncodingSize size); 2639 void nop() { nop(al, Best); } 2640 void nop(Condition cond) { nop(cond, Best); } 2641 void nop(EncodingSize size) { nop(al, size); } 2642 2643 void orn(Condition cond, Register rd, Register rn, const Operand& operand); 2644 void orn(Register rd, Register rn, const Operand& operand) { 2645 orn(al, rd, rn, operand); 2646 } 2647 2648 void orns(Condition cond, Register rd, Register rn, const Operand& operand); 2649 void orns(Register rd, Register rn, const Operand& operand) { 2650 orns(al, rd, rn, operand); 2651 } 2652 2653 void orr(Condition cond, 2654 EncodingSize size, 2655 Register rd, 2656 Register rn, 2657 const Operand& operand); 2658 void orr(Register rd, Register rn, const Operand& operand) { 2659 orr(al, Best, rd, rn, operand); 2660 } 2661 void orr(Condition cond, Register rd, Register rn, const Operand& operand) { 2662 orr(cond, Best, rd, rn, operand); 2663 } 2664 void orr(EncodingSize size, 2665 Register rd, 2666 Register rn, 2667 const Operand& operand) { 2668 orr(al, size, rd, rn, operand); 2669 } 2670 2671 void orrs(Condition cond, 2672 EncodingSize size, 2673 Register rd, 2674 Register rn, 2675 const Operand& operand); 2676 void orrs(Register rd, Register rn, const Operand& operand) { 2677 orrs(al, Best, rd, rn, operand); 2678 } 2679 void orrs(Condition cond, Register rd, Register rn, const Operand& operand) { 2680 orrs(cond, Best, rd, rn, operand); 2681 } 2682 void orrs(EncodingSize size, 2683 Register rd, 2684 Register rn, 2685 const Operand& operand) { 2686 orrs(al, size, rd, rn, operand); 2687 } 2688 2689 void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand); 2690 void pkhbt(Register rd, Register rn, const Operand& operand) { 2691 pkhbt(al, rd, rn, operand); 2692 } 2693 2694 void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand); 2695 void pkhtb(Register rd, Register rn, const Operand& operand) { 2696 pkhtb(al, rd, rn, operand); 2697 } 2698 2699 void pld(Condition cond, Label* label); 2700 void pld(Label* label) { pld(al, label); } 2701 2702 void pld(Condition cond, const MemOperand& operand); 2703 void pld(const MemOperand& operand) { pld(al, operand); } 2704 2705 void pldw(Condition cond, const MemOperand& operand); 2706 void pldw(const MemOperand& operand) { pldw(al, operand); } 2707 2708 void pli(Condition cond, const MemOperand& operand); 2709 void pli(const MemOperand& operand) { pli(al, operand); } 2710 2711 void pli(Condition cond, Label* label); 2712 void pli(Label* label) { pli(al, label); } 2713 2714 void pop(Condition cond, EncodingSize size, RegisterList registers); 2715 void pop(RegisterList registers) { pop(al, Best, registers); } 2716 void pop(Condition cond, RegisterList registers) { 2717 pop(cond, Best, registers); 2718 } 2719 void pop(EncodingSize size, RegisterList registers) { 2720 pop(al, size, registers); 2721 } 2722 2723 void pop(Condition cond, EncodingSize size, Register rt); 2724 void pop(Register rt) { pop(al, Best, rt); } 2725 void pop(Condition cond, Register rt) { pop(cond, Best, rt); } 2726 void pop(EncodingSize size, Register rt) { pop(al, size, rt); } 2727 2728 void push(Condition cond, EncodingSize size, RegisterList registers); 2729 void push(RegisterList registers) { push(al, Best, registers); } 2730 void push(Condition cond, RegisterList registers) { 2731 push(cond, Best, registers); 2732 } 2733 void push(EncodingSize size, RegisterList registers) { 2734 push(al, size, registers); 2735 } 2736 2737 void push(Condition cond, EncodingSize size, Register rt); 2738 void push(Register rt) { push(al, Best, rt); } 2739 void push(Condition cond, Register rt) { push(cond, Best, rt); } 2740 void push(EncodingSize size, Register rt) { push(al, size, rt); } 2741 2742 void qadd(Condition cond, Register rd, Register rm, Register rn); 2743 void qadd(Register rd, Register rm, Register rn) { qadd(al, rd, rm, rn); } 2744 2745 void qadd16(Condition cond, Register rd, Register rn, Register rm); 2746 void qadd16(Register rd, Register rn, Register rm) { qadd16(al, rd, rn, rm); } 2747 2748 void qadd8(Condition cond, Register rd, Register rn, Register rm); 2749 void qadd8(Register rd, Register rn, Register rm) { qadd8(al, rd, rn, rm); } 2750 2751 void qasx(Condition cond, Register rd, Register rn, Register rm); 2752 void qasx(Register rd, Register rn, Register rm) { qasx(al, rd, rn, rm); } 2753 2754 void qdadd(Condition cond, Register rd, Register rm, Register rn); 2755 void qdadd(Register rd, Register rm, Register rn) { qdadd(al, rd, rm, rn); } 2756 2757 void qdsub(Condition cond, Register rd, Register rm, Register rn); 2758 void qdsub(Register rd, Register rm, Register rn) { qdsub(al, rd, rm, rn); } 2759 2760 void qsax(Condition cond, Register rd, Register rn, Register rm); 2761 void qsax(Register rd, Register rn, Register rm) { qsax(al, rd, rn, rm); } 2762 2763 void qsub(Condition cond, Register rd, Register rm, Register rn); 2764 void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); } 2765 2766 void qsub16(Condition cond, Register rd, Register rn, Register rm); 2767 void qsub16(Register rd, Register rn, Register rm) { qsub16(al, rd, rn, rm); } 2768 2769 void qsub8(Condition cond, Register rd, Register rn, Register rm); 2770 void qsub8(Register rd, Register rn, Register rm) { qsub8(al, rd, rn, rm); } 2771 2772 void rbit(Condition cond, Register rd, Register rm); 2773 void rbit(Register rd, Register rm) { rbit(al, rd, rm); } 2774 2775 void rev(Condition cond, EncodingSize size, Register rd, Register rm); 2776 void rev(Register rd, Register rm) { rev(al, Best, rd, rm); } 2777 void rev(Condition cond, Register rd, Register rm) { 2778 rev(cond, Best, rd, rm); 2779 } 2780 void rev(EncodingSize size, Register rd, Register rm) { 2781 rev(al, size, rd, rm); 2782 } 2783 2784 void rev16(Condition cond, EncodingSize size, Register rd, Register rm); 2785 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } 2786 void rev16(Condition cond, Register rd, Register rm) { 2787 rev16(cond, Best, rd, rm); 2788 } 2789 void rev16(EncodingSize size, Register rd, Register rm) { 2790 rev16(al, size, rd, rm); 2791 } 2792 2793 void revsh(Condition cond, EncodingSize size, Register rd, Register rm); 2794 void revsh(Register rd, Register rm) { revsh(al, Best, rd, rm); } 2795 void revsh(Condition cond, Register rd, Register rm) { 2796 revsh(cond, Best, rd, rm); 2797 } 2798 void revsh(EncodingSize size, Register rd, Register rm) { 2799 revsh(al, size, rd, rm); 2800 } 2801 2802 void ror(Condition cond, 2803 EncodingSize size, 2804 Register rd, 2805 Register rm, 2806 const Operand& operand); 2807 void ror(Register rd, Register rm, const Operand& operand) { 2808 ror(al, Best, rd, rm, operand); 2809 } 2810 void ror(Condition cond, Register rd, Register rm, const Operand& operand) { 2811 ror(cond, Best, rd, rm, operand); 2812 } 2813 void ror(EncodingSize size, 2814 Register rd, 2815 Register rm, 2816 const Operand& operand) { 2817 ror(al, size, rd, rm, operand); 2818 } 2819 2820 void rors(Condition cond, 2821 EncodingSize size, 2822 Register rd, 2823 Register rm, 2824 const Operand& operand); 2825 void rors(Register rd, Register rm, const Operand& operand) { 2826 rors(al, Best, rd, rm, operand); 2827 } 2828 void rors(Condition cond, Register rd, Register rm, const Operand& operand) { 2829 rors(cond, Best, rd, rm, operand); 2830 } 2831 void rors(EncodingSize size, 2832 Register rd, 2833 Register rm, 2834 const Operand& operand) { 2835 rors(al, size, rd, rm, operand); 2836 } 2837 2838 void rrx(Condition cond, Register rd, Register rm); 2839 void rrx(Register rd, Register rm) { rrx(al, rd, rm); } 2840 2841 void rrxs(Condition cond, Register rd, Register rm); 2842 void rrxs(Register rd, Register rm) { rrxs(al, rd, rm); } 2843 2844 void rsb(Condition cond, 2845 EncodingSize size, 2846 Register rd, 2847 Register rn, 2848 const Operand& operand); 2849 void rsb(Register rd, Register rn, const Operand& operand) { 2850 rsb(al, Best, rd, rn, operand); 2851 } 2852 void rsb(Condition cond, Register rd, Register rn, const Operand& operand) { 2853 rsb(cond, Best, rd, rn, operand); 2854 } 2855 void rsb(EncodingSize size, 2856 Register rd, 2857 Register rn, 2858 const Operand& operand) { 2859 rsb(al, size, rd, rn, operand); 2860 } 2861 2862 void rsbs(Condition cond, 2863 EncodingSize size, 2864 Register rd, 2865 Register rn, 2866 const Operand& operand); 2867 void rsbs(Register rd, Register rn, const Operand& operand) { 2868 rsbs(al, Best, rd, rn, operand); 2869 } 2870 void rsbs(Condition cond, Register rd, Register rn, const Operand& operand) { 2871 rsbs(cond, Best, rd, rn, operand); 2872 } 2873 void rsbs(EncodingSize size, 2874 Register rd, 2875 Register rn, 2876 const Operand& operand) { 2877 rsbs(al, size, rd, rn, operand); 2878 } 2879 2880 void rsc(Condition cond, Register rd, Register rn, const Operand& operand); 2881 void rsc(Register rd, Register rn, const Operand& operand) { 2882 rsc(al, rd, rn, operand); 2883 } 2884 2885 void rscs(Condition cond, Register rd, Register rn, const Operand& operand); 2886 void rscs(Register rd, Register rn, const Operand& operand) { 2887 rscs(al, rd, rn, operand); 2888 } 2889 2890 void sadd16(Condition cond, Register rd, Register rn, Register rm); 2891 void sadd16(Register rd, Register rn, Register rm) { sadd16(al, rd, rn, rm); } 2892 2893 void sadd8(Condition cond, Register rd, Register rn, Register rm); 2894 void sadd8(Register rd, Register rn, Register rm) { sadd8(al, rd, rn, rm); } 2895 2896 void sasx(Condition cond, Register rd, Register rn, Register rm); 2897 void sasx(Register rd, Register rn, Register rm) { sasx(al, rd, rn, rm); } 2898 2899 void sbc(Condition cond, 2900 EncodingSize size, 2901 Register rd, 2902 Register rn, 2903 const Operand& operand); 2904 void sbc(Register rd, Register rn, const Operand& operand) { 2905 sbc(al, Best, rd, rn, operand); 2906 } 2907 void sbc(Condition cond, Register rd, Register rn, const Operand& operand) { 2908 sbc(cond, Best, rd, rn, operand); 2909 } 2910 void sbc(EncodingSize size, 2911 Register rd, 2912 Register rn, 2913 const Operand& operand) { 2914 sbc(al, size, rd, rn, operand); 2915 } 2916 2917 void sbcs(Condition cond, 2918 EncodingSize size, 2919 Register rd, 2920 Register rn, 2921 const Operand& operand); 2922 void sbcs(Register rd, Register rn, const Operand& operand) { 2923 sbcs(al, Best, rd, rn, operand); 2924 } 2925 void sbcs(Condition cond, Register rd, Register rn, const Operand& operand) { 2926 sbcs(cond, Best, rd, rn, operand); 2927 } 2928 void sbcs(EncodingSize size, 2929 Register rd, 2930 Register rn, 2931 const Operand& operand) { 2932 sbcs(al, size, rd, rn, operand); 2933 } 2934 2935 void sbfx(Condition cond, 2936 Register rd, 2937 Register rn, 2938 uint32_t lsb, 2939 const Operand& operand); 2940 void sbfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 2941 sbfx(al, rd, rn, lsb, operand); 2942 } 2943 2944 void sdiv(Condition cond, Register rd, Register rn, Register rm); 2945 void sdiv(Register rd, Register rn, Register rm) { sdiv(al, rd, rn, rm); } 2946 2947 void sel(Condition cond, Register rd, Register rn, Register rm); 2948 void sel(Register rd, Register rn, Register rm) { sel(al, rd, rn, rm); } 2949 2950 void shadd16(Condition cond, Register rd, Register rn, Register rm); 2951 void shadd16(Register rd, Register rn, Register rm) { 2952 shadd16(al, rd, rn, rm); 2953 } 2954 2955 void shadd8(Condition cond, Register rd, Register rn, Register rm); 2956 void shadd8(Register rd, Register rn, Register rm) { shadd8(al, rd, rn, rm); } 2957 2958 void shasx(Condition cond, Register rd, Register rn, Register rm); 2959 void shasx(Register rd, Register rn, Register rm) { shasx(al, rd, rn, rm); } 2960 2961 void shsax(Condition cond, Register rd, Register rn, Register rm); 2962 void shsax(Register rd, Register rn, Register rm) { shsax(al, rd, rn, rm); } 2963 2964 void shsub16(Condition cond, Register rd, Register rn, Register rm); 2965 void shsub16(Register rd, Register rn, Register rm) { 2966 shsub16(al, rd, rn, rm); 2967 } 2968 2969 void shsub8(Condition cond, Register rd, Register rn, Register rm); 2970 void shsub8(Register rd, Register rn, Register rm) { shsub8(al, rd, rn, rm); } 2971 2972 void smlabb( 2973 Condition cond, Register rd, Register rn, Register rm, Register ra); 2974 void smlabb(Register rd, Register rn, Register rm, Register ra) { 2975 smlabb(al, rd, rn, rm, ra); 2976 } 2977 2978 void smlabt( 2979 Condition cond, Register rd, Register rn, Register rm, Register ra); 2980 void smlabt(Register rd, Register rn, Register rm, Register ra) { 2981 smlabt(al, rd, rn, rm, ra); 2982 } 2983 2984 void smlad( 2985 Condition cond, Register rd, Register rn, Register rm, Register ra); 2986 void smlad(Register rd, Register rn, Register rm, Register ra) { 2987 smlad(al, rd, rn, rm, ra); 2988 } 2989 2990 void smladx( 2991 Condition cond, Register rd, Register rn, Register rm, Register ra); 2992 void smladx(Register rd, Register rn, Register rm, Register ra) { 2993 smladx(al, rd, rn, rm, ra); 2994 } 2995 2996 void smlal( 2997 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2998 void smlal(Register rdlo, Register rdhi, Register rn, Register rm) { 2999 smlal(al, rdlo, rdhi, rn, rm); 3000 } 3001 3002 void smlalbb( 3003 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3004 void smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) { 3005 smlalbb(al, rdlo, rdhi, rn, rm); 3006 } 3007 3008 void smlalbt( 3009 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3010 void smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) { 3011 smlalbt(al, rdlo, rdhi, rn, rm); 3012 } 3013 3014 void smlald( 3015 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3016 void smlald(Register rdlo, Register rdhi, Register rn, Register rm) { 3017 smlald(al, rdlo, rdhi, rn, rm); 3018 } 3019 3020 void smlaldx( 3021 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3022 void smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3023 smlaldx(al, rdlo, rdhi, rn, rm); 3024 } 3025 3026 void smlals( 3027 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3028 void smlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3029 smlals(al, rdlo, rdhi, rn, rm); 3030 } 3031 3032 void smlaltb( 3033 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3034 void smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) { 3035 smlaltb(al, rdlo, rdhi, rn, rm); 3036 } 3037 3038 void smlaltt( 3039 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3040 void smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) { 3041 smlaltt(al, rdlo, rdhi, rn, rm); 3042 } 3043 3044 void smlatb( 3045 Condition cond, Register rd, Register rn, Register rm, Register ra); 3046 void smlatb(Register rd, Register rn, Register rm, Register ra) { 3047 smlatb(al, rd, rn, rm, ra); 3048 } 3049 3050 void smlatt( 3051 Condition cond, Register rd, Register rn, Register rm, Register ra); 3052 void smlatt(Register rd, Register rn, Register rm, Register ra) { 3053 smlatt(al, rd, rn, rm, ra); 3054 } 3055 3056 void smlawb( 3057 Condition cond, Register rd, Register rn, Register rm, Register ra); 3058 void smlawb(Register rd, Register rn, Register rm, Register ra) { 3059 smlawb(al, rd, rn, rm, ra); 3060 } 3061 3062 void smlawt( 3063 Condition cond, Register rd, Register rn, Register rm, Register ra); 3064 void smlawt(Register rd, Register rn, Register rm, Register ra) { 3065 smlawt(al, rd, rn, rm, ra); 3066 } 3067 3068 void smlsd( 3069 Condition cond, Register rd, Register rn, Register rm, Register ra); 3070 void smlsd(Register rd, Register rn, Register rm, Register ra) { 3071 smlsd(al, rd, rn, rm, ra); 3072 } 3073 3074 void smlsdx( 3075 Condition cond, Register rd, Register rn, Register rm, Register ra); 3076 void smlsdx(Register rd, Register rn, Register rm, Register ra) { 3077 smlsdx(al, rd, rn, rm, ra); 3078 } 3079 3080 void smlsld( 3081 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3082 void smlsld(Register rdlo, Register rdhi, Register rn, Register rm) { 3083 smlsld(al, rdlo, rdhi, rn, rm); 3084 } 3085 3086 void smlsldx( 3087 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3088 void smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3089 smlsldx(al, rdlo, rdhi, rn, rm); 3090 } 3091 3092 void smmla( 3093 Condition cond, Register rd, Register rn, Register rm, Register ra); 3094 void smmla(Register rd, Register rn, Register rm, Register ra) { 3095 smmla(al, rd, rn, rm, ra); 3096 } 3097 3098 void smmlar( 3099 Condition cond, Register rd, Register rn, Register rm, Register ra); 3100 void smmlar(Register rd, Register rn, Register rm, Register ra) { 3101 smmlar(al, rd, rn, rm, ra); 3102 } 3103 3104 void smmls( 3105 Condition cond, Register rd, Register rn, Register rm, Register ra); 3106 void smmls(Register rd, Register rn, Register rm, Register ra) { 3107 smmls(al, rd, rn, rm, ra); 3108 } 3109 3110 void smmlsr( 3111 Condition cond, Register rd, Register rn, Register rm, Register ra); 3112 void smmlsr(Register rd, Register rn, Register rm, Register ra) { 3113 smmlsr(al, rd, rn, rm, ra); 3114 } 3115 3116 void smmul(Condition cond, Register rd, Register rn, Register rm); 3117 void smmul(Register rd, Register rn, Register rm) { smmul(al, rd, rn, rm); } 3118 3119 void smmulr(Condition cond, Register rd, Register rn, Register rm); 3120 void smmulr(Register rd, Register rn, Register rm) { smmulr(al, rd, rn, rm); } 3121 3122 void smuad(Condition cond, Register rd, Register rn, Register rm); 3123 void smuad(Register rd, Register rn, Register rm) { smuad(al, rd, rn, rm); } 3124 3125 void smuadx(Condition cond, Register rd, Register rn, Register rm); 3126 void smuadx(Register rd, Register rn, Register rm) { smuadx(al, rd, rn, rm); } 3127 3128 void smulbb(Condition cond, Register rd, Register rn, Register rm); 3129 void smulbb(Register rd, Register rn, Register rm) { smulbb(al, rd, rn, rm); } 3130 3131 void smulbt(Condition cond, Register rd, Register rn, Register rm); 3132 void smulbt(Register rd, Register rn, Register rm) { smulbt(al, rd, rn, rm); } 3133 3134 void smull( 3135 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3136 void smull(Register rdlo, Register rdhi, Register rn, Register rm) { 3137 smull(al, rdlo, rdhi, rn, rm); 3138 } 3139 3140 void smulls( 3141 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3142 void smulls(Register rdlo, Register rdhi, Register rn, Register rm) { 3143 smulls(al, rdlo, rdhi, rn, rm); 3144 } 3145 3146 void smultb(Condition cond, Register rd, Register rn, Register rm); 3147 void smultb(Register rd, Register rn, Register rm) { smultb(al, rd, rn, rm); } 3148 3149 void smultt(Condition cond, Register rd, Register rn, Register rm); 3150 void smultt(Register rd, Register rn, Register rm) { smultt(al, rd, rn, rm); } 3151 3152 void smulwb(Condition cond, Register rd, Register rn, Register rm); 3153 void smulwb(Register rd, Register rn, Register rm) { smulwb(al, rd, rn, rm); } 3154 3155 void smulwt(Condition cond, Register rd, Register rn, Register rm); 3156 void smulwt(Register rd, Register rn, Register rm) { smulwt(al, rd, rn, rm); } 3157 3158 void smusd(Condition cond, Register rd, Register rn, Register rm); 3159 void smusd(Register rd, Register rn, Register rm) { smusd(al, rd, rn, rm); } 3160 3161 void smusdx(Condition cond, Register rd, Register rn, Register rm); 3162 void smusdx(Register rd, Register rn, Register rm) { smusdx(al, rd, rn, rm); } 3163 3164 void ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand); 3165 void ssat(Register rd, uint32_t imm, const Operand& operand) { 3166 ssat(al, rd, imm, operand); 3167 } 3168 3169 void ssat16(Condition cond, Register rd, uint32_t imm, Register rn); 3170 void ssat16(Register rd, uint32_t imm, Register rn) { 3171 ssat16(al, rd, imm, rn); 3172 } 3173 3174 void ssax(Condition cond, Register rd, Register rn, Register rm); 3175 void ssax(Register rd, Register rn, Register rm) { ssax(al, rd, rn, rm); } 3176 3177 void ssub16(Condition cond, Register rd, Register rn, Register rm); 3178 void ssub16(Register rd, Register rn, Register rm) { ssub16(al, rd, rn, rm); } 3179 3180 void ssub8(Condition cond, Register rd, Register rn, Register rm); 3181 void ssub8(Register rd, Register rn, Register rm) { ssub8(al, rd, rn, rm); } 3182 3183 void stl(Condition cond, Register rt, const MemOperand& operand); 3184 void stl(Register rt, const MemOperand& operand) { stl(al, rt, operand); } 3185 3186 void stlb(Condition cond, Register rt, const MemOperand& operand); 3187 void stlb(Register rt, const MemOperand& operand) { stlb(al, rt, operand); } 3188 3189 void stlex(Condition cond, 3190 Register rd, 3191 Register rt, 3192 const MemOperand& operand); 3193 void stlex(Register rd, Register rt, const MemOperand& operand) { 3194 stlex(al, rd, rt, operand); 3195 } 3196 3197 void stlexb(Condition cond, 3198 Register rd, 3199 Register rt, 3200 const MemOperand& operand); 3201 void stlexb(Register rd, Register rt, const MemOperand& operand) { 3202 stlexb(al, rd, rt, operand); 3203 } 3204 3205 void stlexd(Condition cond, 3206 Register rd, 3207 Register rt, 3208 Register rt2, 3209 const MemOperand& operand); 3210 void stlexd(Register rd, 3211 Register rt, 3212 Register rt2, 3213 const MemOperand& operand) { 3214 stlexd(al, rd, rt, rt2, operand); 3215 } 3216 3217 void stlexh(Condition cond, 3218 Register rd, 3219 Register rt, 3220 const MemOperand& operand); 3221 void stlexh(Register rd, Register rt, const MemOperand& operand) { 3222 stlexh(al, rd, rt, operand); 3223 } 3224 3225 void stlh(Condition cond, Register rt, const MemOperand& operand); 3226 void stlh(Register rt, const MemOperand& operand) { stlh(al, rt, operand); } 3227 3228 void stm(Condition cond, 3229 EncodingSize size, 3230 Register rn, 3231 WriteBack write_back, 3232 RegisterList registers); 3233 void stm(Register rn, WriteBack write_back, RegisterList registers) { 3234 stm(al, Best, rn, write_back, registers); 3235 } 3236 void stm(Condition cond, 3237 Register rn, 3238 WriteBack write_back, 3239 RegisterList registers) { 3240 stm(cond, Best, rn, write_back, registers); 3241 } 3242 void stm(EncodingSize size, 3243 Register rn, 3244 WriteBack write_back, 3245 RegisterList registers) { 3246 stm(al, size, rn, write_back, registers); 3247 } 3248 3249 void stmda(Condition cond, 3250 Register rn, 3251 WriteBack write_back, 3252 RegisterList registers); 3253 void stmda(Register rn, WriteBack write_back, RegisterList registers) { 3254 stmda(al, rn, write_back, registers); 3255 } 3256 3257 void stmdb(Condition cond, 3258 EncodingSize size, 3259 Register rn, 3260 WriteBack write_back, 3261 RegisterList registers); 3262 void stmdb(Register rn, WriteBack write_back, RegisterList registers) { 3263 stmdb(al, Best, rn, write_back, registers); 3264 } 3265 void stmdb(Condition cond, 3266 Register rn, 3267 WriteBack write_back, 3268 RegisterList registers) { 3269 stmdb(cond, Best, rn, write_back, registers); 3270 } 3271 void stmdb(EncodingSize size, 3272 Register rn, 3273 WriteBack write_back, 3274 RegisterList registers) { 3275 stmdb(al, size, rn, write_back, registers); 3276 } 3277 3278 void stmea(Condition cond, 3279 EncodingSize size, 3280 Register rn, 3281 WriteBack write_back, 3282 RegisterList registers); 3283 void stmea(Register rn, WriteBack write_back, RegisterList registers) { 3284 stmea(al, Best, rn, write_back, registers); 3285 } 3286 void stmea(Condition cond, 3287 Register rn, 3288 WriteBack write_back, 3289 RegisterList registers) { 3290 stmea(cond, Best, rn, write_back, registers); 3291 } 3292 void stmea(EncodingSize size, 3293 Register rn, 3294 WriteBack write_back, 3295 RegisterList registers) { 3296 stmea(al, size, rn, write_back, registers); 3297 } 3298 3299 void stmed(Condition cond, 3300 Register rn, 3301 WriteBack write_back, 3302 RegisterList registers); 3303 void stmed(Register rn, WriteBack write_back, RegisterList registers) { 3304 stmed(al, rn, write_back, registers); 3305 } 3306 3307 void stmfa(Condition cond, 3308 Register rn, 3309 WriteBack write_back, 3310 RegisterList registers); 3311 void stmfa(Register rn, WriteBack write_back, RegisterList registers) { 3312 stmfa(al, rn, write_back, registers); 3313 } 3314 3315 void stmfd(Condition cond, 3316 Register rn, 3317 WriteBack write_back, 3318 RegisterList registers); 3319 void stmfd(Register rn, WriteBack write_back, RegisterList registers) { 3320 stmfd(al, rn, write_back, registers); 3321 } 3322 3323 void stmib(Condition cond, 3324 Register rn, 3325 WriteBack write_back, 3326 RegisterList registers); 3327 void stmib(Register rn, WriteBack write_back, RegisterList registers) { 3328 stmib(al, rn, write_back, registers); 3329 } 3330 3331 void str(Condition cond, 3332 EncodingSize size, 3333 Register rt, 3334 const MemOperand& operand); 3335 void str(Register rt, const MemOperand& operand) { 3336 str(al, Best, rt, operand); 3337 } 3338 void str(Condition cond, Register rt, const MemOperand& operand) { 3339 str(cond, Best, rt, operand); 3340 } 3341 void str(EncodingSize size, Register rt, const MemOperand& operand) { 3342 str(al, size, rt, operand); 3343 } 3344 3345 void strb(Condition cond, 3346 EncodingSize size, 3347 Register rt, 3348 const MemOperand& operand); 3349 void strb(Register rt, const MemOperand& operand) { 3350 strb(al, Best, rt, operand); 3351 } 3352 void strb(Condition cond, Register rt, const MemOperand& operand) { 3353 strb(cond, Best, rt, operand); 3354 } 3355 void strb(EncodingSize size, Register rt, const MemOperand& operand) { 3356 strb(al, size, rt, operand); 3357 } 3358 3359 void strd(Condition cond, 3360 Register rt, 3361 Register rt2, 3362 const MemOperand& operand); 3363 void strd(Register rt, Register rt2, const MemOperand& operand) { 3364 strd(al, rt, rt2, operand); 3365 } 3366 3367 void strex(Condition cond, 3368 Register rd, 3369 Register rt, 3370 const MemOperand& operand); 3371 void strex(Register rd, Register rt, const MemOperand& operand) { 3372 strex(al, rd, rt, operand); 3373 } 3374 3375 void strexb(Condition cond, 3376 Register rd, 3377 Register rt, 3378 const MemOperand& operand); 3379 void strexb(Register rd, Register rt, const MemOperand& operand) { 3380 strexb(al, rd, rt, operand); 3381 } 3382 3383 void strexd(Condition cond, 3384 Register rd, 3385 Register rt, 3386 Register rt2, 3387 const MemOperand& operand); 3388 void strexd(Register rd, 3389 Register rt, 3390 Register rt2, 3391 const MemOperand& operand) { 3392 strexd(al, rd, rt, rt2, operand); 3393 } 3394 3395 void strexh(Condition cond, 3396 Register rd, 3397 Register rt, 3398 const MemOperand& operand); 3399 void strexh(Register rd, Register rt, const MemOperand& operand) { 3400 strexh(al, rd, rt, operand); 3401 } 3402 3403 void strh(Condition cond, 3404 EncodingSize size, 3405 Register rt, 3406 const MemOperand& operand); 3407 void strh(Register rt, const MemOperand& operand) { 3408 strh(al, Best, rt, operand); 3409 } 3410 void strh(Condition cond, Register rt, const MemOperand& operand) { 3411 strh(cond, Best, rt, operand); 3412 } 3413 void strh(EncodingSize size, Register rt, const MemOperand& operand) { 3414 strh(al, size, rt, operand); 3415 } 3416 3417 void sub(Condition cond, 3418 EncodingSize size, 3419 Register rd, 3420 Register rn, 3421 const Operand& operand); 3422 void sub(Register rd, Register rn, const Operand& operand) { 3423 sub(al, Best, rd, rn, operand); 3424 } 3425 void sub(Condition cond, Register rd, Register rn, const Operand& operand) { 3426 sub(cond, Best, rd, rn, operand); 3427 } 3428 void sub(EncodingSize size, 3429 Register rd, 3430 Register rn, 3431 const Operand& operand) { 3432 sub(al, size, rd, rn, operand); 3433 } 3434 3435 void sub(Condition cond, Register rd, const Operand& operand); 3436 void sub(Register rd, const Operand& operand) { sub(al, rd, operand); } 3437 3438 void subs(Condition cond, 3439 EncodingSize size, 3440 Register rd, 3441 Register rn, 3442 const Operand& operand); 3443 void subs(Register rd, Register rn, const Operand& operand) { 3444 subs(al, Best, rd, rn, operand); 3445 } 3446 void subs(Condition cond, Register rd, Register rn, const Operand& operand) { 3447 subs(cond, Best, rd, rn, operand); 3448 } 3449 void subs(EncodingSize size, 3450 Register rd, 3451 Register rn, 3452 const Operand& operand) { 3453 subs(al, size, rd, rn, operand); 3454 } 3455 3456 void subs(Register rd, const Operand& operand); 3457 3458 void subw(Condition cond, Register rd, Register rn, const Operand& operand); 3459 void subw(Register rd, Register rn, const Operand& operand) { 3460 subw(al, rd, rn, operand); 3461 } 3462 3463 void svc(Condition cond, uint32_t imm); 3464 void svc(uint32_t imm) { svc(al, imm); } 3465 3466 void sxtab(Condition cond, Register rd, Register rn, const Operand& operand); 3467 void sxtab(Register rd, Register rn, const Operand& operand) { 3468 sxtab(al, rd, rn, operand); 3469 } 3470 3471 void sxtab16(Condition cond, 3472 Register rd, 3473 Register rn, 3474 const Operand& operand); 3475 void sxtab16(Register rd, Register rn, const Operand& operand) { 3476 sxtab16(al, rd, rn, operand); 3477 } 3478 3479 void sxtah(Condition cond, Register rd, Register rn, const Operand& operand); 3480 void sxtah(Register rd, Register rn, const Operand& operand) { 3481 sxtah(al, rd, rn, operand); 3482 } 3483 3484 void sxtb(Condition cond, 3485 EncodingSize size, 3486 Register rd, 3487 const Operand& operand); 3488 void sxtb(Register rd, const Operand& operand) { 3489 sxtb(al, Best, rd, operand); 3490 } 3491 void sxtb(Condition cond, Register rd, const Operand& operand) { 3492 sxtb(cond, Best, rd, operand); 3493 } 3494 void sxtb(EncodingSize size, Register rd, const Operand& operand) { 3495 sxtb(al, size, rd, operand); 3496 } 3497 3498 void sxtb16(Condition cond, Register rd, const Operand& operand); 3499 void sxtb16(Register rd, const Operand& operand) { sxtb16(al, rd, operand); } 3500 3501 void sxth(Condition cond, 3502 EncodingSize size, 3503 Register rd, 3504 const Operand& operand); 3505 void sxth(Register rd, const Operand& operand) { 3506 sxth(al, Best, rd, operand); 3507 } 3508 void sxth(Condition cond, Register rd, const Operand& operand) { 3509 sxth(cond, Best, rd, operand); 3510 } 3511 void sxth(EncodingSize size, Register rd, const Operand& operand) { 3512 sxth(al, size, rd, operand); 3513 } 3514 3515 void tbb(Condition cond, Register rn, Register rm); 3516 void tbb(Register rn, Register rm) { tbb(al, rn, rm); } 3517 3518 void tbh(Condition cond, Register rn, Register rm); 3519 void tbh(Register rn, Register rm) { tbh(al, rn, rm); } 3520 3521 void teq(Condition cond, Register rn, const Operand& operand); 3522 void teq(Register rn, const Operand& operand) { teq(al, rn, operand); } 3523 3524 void tst(Condition cond, 3525 EncodingSize size, 3526 Register rn, 3527 const Operand& operand); 3528 void tst(Register rn, const Operand& operand) { tst(al, Best, rn, operand); } 3529 void tst(Condition cond, Register rn, const Operand& operand) { 3530 tst(cond, Best, rn, operand); 3531 } 3532 void tst(EncodingSize size, Register rn, const Operand& operand) { 3533 tst(al, size, rn, operand); 3534 } 3535 3536 void uadd16(Condition cond, Register rd, Register rn, Register rm); 3537 void uadd16(Register rd, Register rn, Register rm) { uadd16(al, rd, rn, rm); } 3538 3539 void uadd8(Condition cond, Register rd, Register rn, Register rm); 3540 void uadd8(Register rd, Register rn, Register rm) { uadd8(al, rd, rn, rm); } 3541 3542 void uasx(Condition cond, Register rd, Register rn, Register rm); 3543 void uasx(Register rd, Register rn, Register rm) { uasx(al, rd, rn, rm); } 3544 3545 void ubfx(Condition cond, 3546 Register rd, 3547 Register rn, 3548 uint32_t lsb, 3549 const Operand& operand); 3550 void ubfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 3551 ubfx(al, rd, rn, lsb, operand); 3552 } 3553 3554 void udf(Condition cond, EncodingSize size, uint32_t imm); 3555 void udf(uint32_t imm) { udf(al, Best, imm); } 3556 void udf(Condition cond, uint32_t imm) { udf(cond, Best, imm); } 3557 void udf(EncodingSize size, uint32_t imm) { udf(al, size, imm); } 3558 3559 void udiv(Condition cond, Register rd, Register rn, Register rm); 3560 void udiv(Register rd, Register rn, Register rm) { udiv(al, rd, rn, rm); } 3561 3562 void uhadd16(Condition cond, Register rd, Register rn, Register rm); 3563 void uhadd16(Register rd, Register rn, Register rm) { 3564 uhadd16(al, rd, rn, rm); 3565 } 3566 3567 void uhadd8(Condition cond, Register rd, Register rn, Register rm); 3568 void uhadd8(Register rd, Register rn, Register rm) { uhadd8(al, rd, rn, rm); } 3569 3570 void uhasx(Condition cond, Register rd, Register rn, Register rm); 3571 void uhasx(Register rd, Register rn, Register rm) { uhasx(al, rd, rn, rm); } 3572 3573 void uhsax(Condition cond, Register rd, Register rn, Register rm); 3574 void uhsax(Register rd, Register rn, Register rm) { uhsax(al, rd, rn, rm); } 3575 3576 void uhsub16(Condition cond, Register rd, Register rn, Register rm); 3577 void uhsub16(Register rd, Register rn, Register rm) { 3578 uhsub16(al, rd, rn, rm); 3579 } 3580 3581 void uhsub8(Condition cond, Register rd, Register rn, Register rm); 3582 void uhsub8(Register rd, Register rn, Register rm) { uhsub8(al, rd, rn, rm); } 3583 3584 void umaal( 3585 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3586 void umaal(Register rdlo, Register rdhi, Register rn, Register rm) { 3587 umaal(al, rdlo, rdhi, rn, rm); 3588 } 3589 3590 void umlal( 3591 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3592 void umlal(Register rdlo, Register rdhi, Register rn, Register rm) { 3593 umlal(al, rdlo, rdhi, rn, rm); 3594 } 3595 3596 void umlals( 3597 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3598 void umlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3599 umlals(al, rdlo, rdhi, rn, rm); 3600 } 3601 3602 void umull( 3603 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3604 void umull(Register rdlo, Register rdhi, Register rn, Register rm) { 3605 umull(al, rdlo, rdhi, rn, rm); 3606 } 3607 3608 void umulls( 3609 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3610 void umulls(Register rdlo, Register rdhi, Register rn, Register rm) { 3611 umulls(al, rdlo, rdhi, rn, rm); 3612 } 3613 3614 void uqadd16(Condition cond, Register rd, Register rn, Register rm); 3615 void uqadd16(Register rd, Register rn, Register rm) { 3616 uqadd16(al, rd, rn, rm); 3617 } 3618 3619 void uqadd8(Condition cond, Register rd, Register rn, Register rm); 3620 void uqadd8(Register rd, Register rn, Register rm) { uqadd8(al, rd, rn, rm); } 3621 3622 void uqasx(Condition cond, Register rd, Register rn, Register rm); 3623 void uqasx(Register rd, Register rn, Register rm) { uqasx(al, rd, rn, rm); } 3624 3625 void uqsax(Condition cond, Register rd, Register rn, Register rm); 3626 void uqsax(Register rd, Register rn, Register rm) { uqsax(al, rd, rn, rm); } 3627 3628 void uqsub16(Condition cond, Register rd, Register rn, Register rm); 3629 void uqsub16(Register rd, Register rn, Register rm) { 3630 uqsub16(al, rd, rn, rm); 3631 } 3632 3633 void uqsub8(Condition cond, Register rd, Register rn, Register rm); 3634 void uqsub8(Register rd, Register rn, Register rm) { uqsub8(al, rd, rn, rm); } 3635 3636 void usad8(Condition cond, Register rd, Register rn, Register rm); 3637 void usad8(Register rd, Register rn, Register rm) { usad8(al, rd, rn, rm); } 3638 3639 void usada8( 3640 Condition cond, Register rd, Register rn, Register rm, Register ra); 3641 void usada8(Register rd, Register rn, Register rm, Register ra) { 3642 usada8(al, rd, rn, rm, ra); 3643 } 3644 3645 void usat(Condition cond, Register rd, uint32_t imm, const Operand& operand); 3646 void usat(Register rd, uint32_t imm, const Operand& operand) { 3647 usat(al, rd, imm, operand); 3648 } 3649 3650 void usat16(Condition cond, Register rd, uint32_t imm, Register rn); 3651 void usat16(Register rd, uint32_t imm, Register rn) { 3652 usat16(al, rd, imm, rn); 3653 } 3654 3655 void usax(Condition cond, Register rd, Register rn, Register rm); 3656 void usax(Register rd, Register rn, Register rm) { usax(al, rd, rn, rm); } 3657 3658 void usub16(Condition cond, Register rd, Register rn, Register rm); 3659 void usub16(Register rd, Register rn, Register rm) { usub16(al, rd, rn, rm); } 3660 3661 void usub8(Condition cond, Register rd, Register rn, Register rm); 3662 void usub8(Register rd, Register rn, Register rm) { usub8(al, rd, rn, rm); } 3663 3664 void uxtab(Condition cond, Register rd, Register rn, const Operand& operand); 3665 void uxtab(Register rd, Register rn, const Operand& operand) { 3666 uxtab(al, rd, rn, operand); 3667 } 3668 3669 void uxtab16(Condition cond, 3670 Register rd, 3671 Register rn, 3672 const Operand& operand); 3673 void uxtab16(Register rd, Register rn, const Operand& operand) { 3674 uxtab16(al, rd, rn, operand); 3675 } 3676 3677 void uxtah(Condition cond, Register rd, Register rn, const Operand& operand); 3678 void uxtah(Register rd, Register rn, const Operand& operand) { 3679 uxtah(al, rd, rn, operand); 3680 } 3681 3682 void uxtb(Condition cond, 3683 EncodingSize size, 3684 Register rd, 3685 const Operand& operand); 3686 void uxtb(Register rd, const Operand& operand) { 3687 uxtb(al, Best, rd, operand); 3688 } 3689 void uxtb(Condition cond, Register rd, const Operand& operand) { 3690 uxtb(cond, Best, rd, operand); 3691 } 3692 void uxtb(EncodingSize size, Register rd, const Operand& operand) { 3693 uxtb(al, size, rd, operand); 3694 } 3695 3696 void uxtb16(Condition cond, Register rd, const Operand& operand); 3697 void uxtb16(Register rd, const Operand& operand) { uxtb16(al, rd, operand); } 3698 3699 void uxth(Condition cond, 3700 EncodingSize size, 3701 Register rd, 3702 const Operand& operand); 3703 void uxth(Register rd, const Operand& operand) { 3704 uxth(al, Best, rd, operand); 3705 } 3706 void uxth(Condition cond, Register rd, const Operand& operand) { 3707 uxth(cond, Best, rd, operand); 3708 } 3709 void uxth(EncodingSize size, Register rd, const Operand& operand) { 3710 uxth(al, size, rd, operand); 3711 } 3712 3713 void vaba( 3714 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3715 void vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3716 vaba(al, dt, rd, rn, rm); 3717 } 3718 3719 void vaba( 3720 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3721 void vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3722 vaba(al, dt, rd, rn, rm); 3723 } 3724 3725 void vabal( 3726 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3727 void vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3728 vabal(al, dt, rd, rn, rm); 3729 } 3730 3731 void vabd( 3732 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3733 void vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3734 vabd(al, dt, rd, rn, rm); 3735 } 3736 3737 void vabd( 3738 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3739 void vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3740 vabd(al, dt, rd, rn, rm); 3741 } 3742 3743 void vabdl( 3744 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3745 void vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3746 vabdl(al, dt, rd, rn, rm); 3747 } 3748 3749 void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm); 3750 void vabs(DataType dt, DRegister rd, DRegister rm) { vabs(al, dt, rd, rm); } 3751 3752 void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm); 3753 void vabs(DataType dt, QRegister rd, QRegister rm) { vabs(al, dt, rd, rm); } 3754 3755 void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm); 3756 void vabs(DataType dt, SRegister rd, SRegister rm) { vabs(al, dt, rd, rm); } 3757 3758 void vacge( 3759 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3760 void vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3761 vacge(al, dt, rd, rn, rm); 3762 } 3763 3764 void vacge( 3765 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3766 void vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3767 vacge(al, dt, rd, rn, rm); 3768 } 3769 3770 void vacgt( 3771 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3772 void vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3773 vacgt(al, dt, rd, rn, rm); 3774 } 3775 3776 void vacgt( 3777 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3778 void vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3779 vacgt(al, dt, rd, rn, rm); 3780 } 3781 3782 void vacle( 3783 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3784 void vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3785 vacle(al, dt, rd, rn, rm); 3786 } 3787 3788 void vacle( 3789 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3790 void vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3791 vacle(al, dt, rd, rn, rm); 3792 } 3793 3794 void vaclt( 3795 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3796 void vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3797 vaclt(al, dt, rd, rn, rm); 3798 } 3799 3800 void vaclt( 3801 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3802 void vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3803 vaclt(al, dt, rd, rn, rm); 3804 } 3805 3806 void vadd( 3807 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3808 void vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3809 vadd(al, dt, rd, rn, rm); 3810 } 3811 3812 void vadd( 3813 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3814 void vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3815 vadd(al, dt, rd, rn, rm); 3816 } 3817 3818 void vadd( 3819 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 3820 void vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 3821 vadd(al, dt, rd, rn, rm); 3822 } 3823 3824 void vaddhn( 3825 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 3826 void vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 3827 vaddhn(al, dt, rd, rn, rm); 3828 } 3829 3830 void vaddl( 3831 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3832 void vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3833 vaddl(al, dt, rd, rn, rm); 3834 } 3835 3836 void vaddw( 3837 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 3838 void vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 3839 vaddw(al, dt, rd, rn, rm); 3840 } 3841 3842 void vand(Condition cond, 3843 DataType dt, 3844 DRegister rd, 3845 DRegister rn, 3846 const DOperand& operand); 3847 void vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 3848 vand(al, dt, rd, rn, operand); 3849 } 3850 3851 void vand(Condition cond, 3852 DataType dt, 3853 QRegister rd, 3854 QRegister rn, 3855 const QOperand& operand); 3856 void vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 3857 vand(al, dt, rd, rn, operand); 3858 } 3859 3860 void vbic(Condition cond, 3861 DataType dt, 3862 DRegister rd, 3863 DRegister rn, 3864 const DOperand& operand); 3865 void vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 3866 vbic(al, dt, rd, rn, operand); 3867 } 3868 3869 void vbic(Condition cond, 3870 DataType dt, 3871 QRegister rd, 3872 QRegister rn, 3873 const QOperand& operand); 3874 void vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 3875 vbic(al, dt, rd, rn, operand); 3876 } 3877 3878 void vbif( 3879 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3880 void vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3881 vbif(al, dt, rd, rn, rm); 3882 } 3883 void vbif(DRegister rd, DRegister rn, DRegister rm) { 3884 vbif(al, kDataTypeValueNone, rd, rn, rm); 3885 } 3886 void vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3887 vbif(cond, kDataTypeValueNone, rd, rn, rm); 3888 } 3889 3890 void vbif( 3891 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3892 void vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3893 vbif(al, dt, rd, rn, rm); 3894 } 3895 void vbif(QRegister rd, QRegister rn, QRegister rm) { 3896 vbif(al, kDataTypeValueNone, rd, rn, rm); 3897 } 3898 void vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3899 vbif(cond, kDataTypeValueNone, rd, rn, rm); 3900 } 3901 3902 void vbit( 3903 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3904 void vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3905 vbit(al, dt, rd, rn, rm); 3906 } 3907 void vbit(DRegister rd, DRegister rn, DRegister rm) { 3908 vbit(al, kDataTypeValueNone, rd, rn, rm); 3909 } 3910 void vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3911 vbit(cond, kDataTypeValueNone, rd, rn, rm); 3912 } 3913 3914 void vbit( 3915 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3916 void vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3917 vbit(al, dt, rd, rn, rm); 3918 } 3919 void vbit(QRegister rd, QRegister rn, QRegister rm) { 3920 vbit(al, kDataTypeValueNone, rd, rn, rm); 3921 } 3922 void vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3923 vbit(cond, kDataTypeValueNone, rd, rn, rm); 3924 } 3925 3926 void vbsl( 3927 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3928 void vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3929 vbsl(al, dt, rd, rn, rm); 3930 } 3931 void vbsl(DRegister rd, DRegister rn, DRegister rm) { 3932 vbsl(al, kDataTypeValueNone, rd, rn, rm); 3933 } 3934 void vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3935 vbsl(cond, kDataTypeValueNone, rd, rn, rm); 3936 } 3937 3938 void vbsl( 3939 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3940 void vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3941 vbsl(al, dt, rd, rn, rm); 3942 } 3943 void vbsl(QRegister rd, QRegister rn, QRegister rm) { 3944 vbsl(al, kDataTypeValueNone, rd, rn, rm); 3945 } 3946 void vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3947 vbsl(cond, kDataTypeValueNone, rd, rn, rm); 3948 } 3949 3950 void vceq(Condition cond, 3951 DataType dt, 3952 DRegister rd, 3953 DRegister rm, 3954 const DOperand& operand); 3955 void vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 3956 vceq(al, dt, rd, rm, operand); 3957 } 3958 3959 void vceq(Condition cond, 3960 DataType dt, 3961 QRegister rd, 3962 QRegister rm, 3963 const QOperand& operand); 3964 void vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 3965 vceq(al, dt, rd, rm, operand); 3966 } 3967 3968 void vceq( 3969 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3970 void vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3971 vceq(al, dt, rd, rn, rm); 3972 } 3973 3974 void vceq( 3975 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3976 void vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3977 vceq(al, dt, rd, rn, rm); 3978 } 3979 3980 void vcge(Condition cond, 3981 DataType dt, 3982 DRegister rd, 3983 DRegister rm, 3984 const DOperand& operand); 3985 void vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 3986 vcge(al, dt, rd, rm, operand); 3987 } 3988 3989 void vcge(Condition cond, 3990 DataType dt, 3991 QRegister rd, 3992 QRegister rm, 3993 const QOperand& operand); 3994 void vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 3995 vcge(al, dt, rd, rm, operand); 3996 } 3997 3998 void vcge( 3999 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4000 void vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4001 vcge(al, dt, rd, rn, rm); 4002 } 4003 4004 void vcge( 4005 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4006 void vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4007 vcge(al, dt, rd, rn, rm); 4008 } 4009 4010 void vcgt(Condition cond, 4011 DataType dt, 4012 DRegister rd, 4013 DRegister rm, 4014 const DOperand& operand); 4015 void vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4016 vcgt(al, dt, rd, rm, operand); 4017 } 4018 4019 void vcgt(Condition cond, 4020 DataType dt, 4021 QRegister rd, 4022 QRegister rm, 4023 const QOperand& operand); 4024 void vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4025 vcgt(al, dt, rd, rm, operand); 4026 } 4027 4028 void vcgt( 4029 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4030 void vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4031 vcgt(al, dt, rd, rn, rm); 4032 } 4033 4034 void vcgt( 4035 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4036 void vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4037 vcgt(al, dt, rd, rn, rm); 4038 } 4039 4040 void vcle(Condition cond, 4041 DataType dt, 4042 DRegister rd, 4043 DRegister rm, 4044 const DOperand& operand); 4045 void vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4046 vcle(al, dt, rd, rm, operand); 4047 } 4048 4049 void vcle(Condition cond, 4050 DataType dt, 4051 QRegister rd, 4052 QRegister rm, 4053 const QOperand& operand); 4054 void vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4055 vcle(al, dt, rd, rm, operand); 4056 } 4057 4058 void vcle( 4059 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4060 void vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4061 vcle(al, dt, rd, rn, rm); 4062 } 4063 4064 void vcle( 4065 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4066 void vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4067 vcle(al, dt, rd, rn, rm); 4068 } 4069 4070 void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm); 4071 void vcls(DataType dt, DRegister rd, DRegister rm) { vcls(al, dt, rd, rm); } 4072 4073 void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm); 4074 void vcls(DataType dt, QRegister rd, QRegister rm) { vcls(al, dt, rd, rm); } 4075 4076 void vclt(Condition cond, 4077 DataType dt, 4078 DRegister rd, 4079 DRegister rm, 4080 const DOperand& operand); 4081 void vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4082 vclt(al, dt, rd, rm, operand); 4083 } 4084 4085 void vclt(Condition cond, 4086 DataType dt, 4087 QRegister rd, 4088 QRegister rm, 4089 const QOperand& operand); 4090 void vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4091 vclt(al, dt, rd, rm, operand); 4092 } 4093 4094 void vclt( 4095 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4096 void vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4097 vclt(al, dt, rd, rn, rm); 4098 } 4099 4100 void vclt( 4101 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4102 void vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4103 vclt(al, dt, rd, rn, rm); 4104 } 4105 4106 void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm); 4107 void vclz(DataType dt, DRegister rd, DRegister rm) { vclz(al, dt, rd, rm); } 4108 4109 void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm); 4110 void vclz(DataType dt, QRegister rd, QRegister rm) { vclz(al, dt, rd, rm); } 4111 4112 void vcmp(Condition cond, DataType dt, SRegister rd, SRegister rm); 4113 void vcmp(DataType dt, SRegister rd, SRegister rm) { vcmp(al, dt, rd, rm); } 4114 4115 void vcmp(Condition cond, DataType dt, DRegister rd, DRegister rm); 4116 void vcmp(DataType dt, DRegister rd, DRegister rm) { vcmp(al, dt, rd, rm); } 4117 4118 void vcmp(Condition cond, DataType dt, SRegister rd, double imm); 4119 void vcmp(DataType dt, SRegister rd, double imm) { vcmp(al, dt, rd, imm); } 4120 4121 void vcmp(Condition cond, DataType dt, DRegister rd, double imm); 4122 void vcmp(DataType dt, DRegister rd, double imm) { vcmp(al, dt, rd, imm); } 4123 4124 void vcmpe(Condition cond, DataType dt, SRegister rd, SRegister rm); 4125 void vcmpe(DataType dt, SRegister rd, SRegister rm) { vcmpe(al, dt, rd, rm); } 4126 4127 void vcmpe(Condition cond, DataType dt, DRegister rd, DRegister rm); 4128 void vcmpe(DataType dt, DRegister rd, DRegister rm) { vcmpe(al, dt, rd, rm); } 4129 4130 void vcmpe(Condition cond, DataType dt, SRegister rd, double imm); 4131 void vcmpe(DataType dt, SRegister rd, double imm) { vcmpe(al, dt, rd, imm); } 4132 4133 void vcmpe(Condition cond, DataType dt, DRegister rd, double imm); 4134 void vcmpe(DataType dt, DRegister rd, double imm) { vcmpe(al, dt, rd, imm); } 4135 4136 void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm); 4137 void vcnt(DataType dt, DRegister rd, DRegister rm) { vcnt(al, dt, rd, rm); } 4138 4139 void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm); 4140 void vcnt(DataType dt, QRegister rd, QRegister rm) { vcnt(al, dt, rd, rm); } 4141 4142 void vcvt( 4143 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 4144 void vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 4145 vcvt(al, dt1, dt2, rd, rm); 4146 } 4147 4148 void vcvt( 4149 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4150 void vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 4151 vcvt(al, dt1, dt2, rd, rm); 4152 } 4153 4154 void vcvt(Condition cond, 4155 DataType dt1, 4156 DataType dt2, 4157 DRegister rd, 4158 DRegister rm, 4159 int32_t fbits); 4160 void vcvt( 4161 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { 4162 vcvt(al, dt1, dt2, rd, rm, fbits); 4163 } 4164 4165 void vcvt(Condition cond, 4166 DataType dt1, 4167 DataType dt2, 4168 QRegister rd, 4169 QRegister rm, 4170 int32_t fbits); 4171 void vcvt( 4172 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { 4173 vcvt(al, dt1, dt2, rd, rm, fbits); 4174 } 4175 4176 void vcvt(Condition cond, 4177 DataType dt1, 4178 DataType dt2, 4179 SRegister rd, 4180 SRegister rm, 4181 int32_t fbits); 4182 void vcvt( 4183 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { 4184 vcvt(al, dt1, dt2, rd, rm, fbits); 4185 } 4186 4187 void vcvt( 4188 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4189 void vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 4190 vcvt(al, dt1, dt2, rd, rm); 4191 } 4192 4193 void vcvt( 4194 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4195 void vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 4196 vcvt(al, dt1, dt2, rd, rm); 4197 } 4198 4199 void vcvt( 4200 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm); 4201 void vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 4202 vcvt(al, dt1, dt2, rd, rm); 4203 } 4204 4205 void vcvt( 4206 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm); 4207 void vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 4208 vcvt(al, dt1, dt2, rd, rm); 4209 } 4210 4211 void vcvt( 4212 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4213 void vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 4214 vcvt(al, dt1, dt2, rd, rm); 4215 } 4216 4217 void vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4218 4219 void vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4220 4221 void vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4222 4223 void vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4224 4225 void vcvtb( 4226 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4227 void vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 4228 vcvtb(al, dt1, dt2, rd, rm); 4229 } 4230 4231 void vcvtb( 4232 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 4233 void vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 4234 vcvtb(al, dt1, dt2, rd, rm); 4235 } 4236 4237 void vcvtb( 4238 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4239 void vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 4240 vcvtb(al, dt1, dt2, rd, rm); 4241 } 4242 4243 void vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4244 4245 void vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4246 4247 void vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4248 4249 void vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4250 4251 void vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4252 4253 void vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4254 4255 void vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4256 4257 void vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4258 4259 void vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4260 4261 void vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4262 4263 void vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4264 4265 void vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4266 4267 void vcvtr( 4268 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4269 void vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 4270 vcvtr(al, dt1, dt2, rd, rm); 4271 } 4272 4273 void vcvtr( 4274 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4275 void vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 4276 vcvtr(al, dt1, dt2, rd, rm); 4277 } 4278 4279 void vcvtt( 4280 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4281 void vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 4282 vcvtt(al, dt1, dt2, rd, rm); 4283 } 4284 4285 void vcvtt( 4286 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 4287 void vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 4288 vcvtt(al, dt1, dt2, rd, rm); 4289 } 4290 4291 void vcvtt( 4292 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4293 void vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 4294 vcvtt(al, dt1, dt2, rd, rm); 4295 } 4296 4297 void vdiv( 4298 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4299 void vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4300 vdiv(al, dt, rd, rn, rm); 4301 } 4302 4303 void vdiv( 4304 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4305 void vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4306 vdiv(al, dt, rd, rn, rm); 4307 } 4308 4309 void vdup(Condition cond, DataType dt, QRegister rd, Register rt); 4310 void vdup(DataType dt, QRegister rd, Register rt) { vdup(al, dt, rd, rt); } 4311 4312 void vdup(Condition cond, DataType dt, DRegister rd, Register rt); 4313 void vdup(DataType dt, DRegister rd, Register rt) { vdup(al, dt, rd, rt); } 4314 4315 void vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm); 4316 void vdup(DataType dt, DRegister rd, DRegisterLane rm) { 4317 vdup(al, dt, rd, rm); 4318 } 4319 4320 void vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm); 4321 void vdup(DataType dt, QRegister rd, DRegisterLane rm) { 4322 vdup(al, dt, rd, rm); 4323 } 4324 4325 void veor( 4326 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4327 void veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4328 veor(al, dt, rd, rn, rm); 4329 } 4330 void veor(DRegister rd, DRegister rn, DRegister rm) { 4331 veor(al, kDataTypeValueNone, rd, rn, rm); 4332 } 4333 void veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 4334 veor(cond, kDataTypeValueNone, rd, rn, rm); 4335 } 4336 4337 void veor( 4338 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4339 void veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4340 veor(al, dt, rd, rn, rm); 4341 } 4342 void veor(QRegister rd, QRegister rn, QRegister rm) { 4343 veor(al, kDataTypeValueNone, rd, rn, rm); 4344 } 4345 void veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 4346 veor(cond, kDataTypeValueNone, rd, rn, rm); 4347 } 4348 4349 void vext(Condition cond, 4350 DataType dt, 4351 DRegister rd, 4352 DRegister rn, 4353 DRegister rm, 4354 const DOperand& operand); 4355 void vext(DataType dt, 4356 DRegister rd, 4357 DRegister rn, 4358 DRegister rm, 4359 const DOperand& operand) { 4360 vext(al, dt, rd, rn, rm, operand); 4361 } 4362 4363 void vext(Condition cond, 4364 DataType dt, 4365 QRegister rd, 4366 QRegister rn, 4367 QRegister rm, 4368 const QOperand& operand); 4369 void vext(DataType dt, 4370 QRegister rd, 4371 QRegister rn, 4372 QRegister rm, 4373 const QOperand& operand) { 4374 vext(al, dt, rd, rn, rm, operand); 4375 } 4376 4377 void vfma( 4378 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4379 void vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4380 vfma(al, dt, rd, rn, rm); 4381 } 4382 4383 void vfma( 4384 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4385 void vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4386 vfma(al, dt, rd, rn, rm); 4387 } 4388 4389 void vfma( 4390 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4391 void vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4392 vfma(al, dt, rd, rn, rm); 4393 } 4394 4395 void vfms( 4396 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4397 void vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4398 vfms(al, dt, rd, rn, rm); 4399 } 4400 4401 void vfms( 4402 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4403 void vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4404 vfms(al, dt, rd, rn, rm); 4405 } 4406 4407 void vfms( 4408 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4409 void vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4410 vfms(al, dt, rd, rn, rm); 4411 } 4412 4413 void vfnma( 4414 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4415 void vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4416 vfnma(al, dt, rd, rn, rm); 4417 } 4418 4419 void vfnma( 4420 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4421 void vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4422 vfnma(al, dt, rd, rn, rm); 4423 } 4424 4425 void vfnms( 4426 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4427 void vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4428 vfnms(al, dt, rd, rn, rm); 4429 } 4430 4431 void vfnms( 4432 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4433 void vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4434 vfnms(al, dt, rd, rn, rm); 4435 } 4436 4437 void vhadd( 4438 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4439 void vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4440 vhadd(al, dt, rd, rn, rm); 4441 } 4442 4443 void vhadd( 4444 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4445 void vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4446 vhadd(al, dt, rd, rn, rm); 4447 } 4448 4449 void vhsub( 4450 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4451 void vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4452 vhsub(al, dt, rd, rn, rm); 4453 } 4454 4455 void vhsub( 4456 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4457 void vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4458 vhsub(al, dt, rd, rn, rm); 4459 } 4460 4461 void vld1(Condition cond, 4462 DataType dt, 4463 const NeonRegisterList& nreglist, 4464 const AlignedMemOperand& operand); 4465 void vld1(DataType dt, 4466 const NeonRegisterList& nreglist, 4467 const AlignedMemOperand& operand) { 4468 vld1(al, dt, nreglist, operand); 4469 } 4470 4471 void vld2(Condition cond, 4472 DataType dt, 4473 const NeonRegisterList& nreglist, 4474 const AlignedMemOperand& operand); 4475 void vld2(DataType dt, 4476 const NeonRegisterList& nreglist, 4477 const AlignedMemOperand& operand) { 4478 vld2(al, dt, nreglist, operand); 4479 } 4480 4481 void vld3(Condition cond, 4482 DataType dt, 4483 const NeonRegisterList& nreglist, 4484 const AlignedMemOperand& operand); 4485 void vld3(DataType dt, 4486 const NeonRegisterList& nreglist, 4487 const AlignedMemOperand& operand) { 4488 vld3(al, dt, nreglist, operand); 4489 } 4490 4491 void vld3(Condition cond, 4492 DataType dt, 4493 const NeonRegisterList& nreglist, 4494 const MemOperand& operand); 4495 void vld3(DataType dt, 4496 const NeonRegisterList& nreglist, 4497 const MemOperand& operand) { 4498 vld3(al, dt, nreglist, operand); 4499 } 4500 4501 void vld4(Condition cond, 4502 DataType dt, 4503 const NeonRegisterList& nreglist, 4504 const AlignedMemOperand& operand); 4505 void vld4(DataType dt, 4506 const NeonRegisterList& nreglist, 4507 const AlignedMemOperand& operand) { 4508 vld4(al, dt, nreglist, operand); 4509 } 4510 4511 void vldm(Condition cond, 4512 DataType dt, 4513 Register rn, 4514 WriteBack write_back, 4515 DRegisterList dreglist); 4516 void vldm(DataType dt, 4517 Register rn, 4518 WriteBack write_back, 4519 DRegisterList dreglist) { 4520 vldm(al, dt, rn, write_back, dreglist); 4521 } 4522 void vldm(Register rn, WriteBack write_back, DRegisterList dreglist) { 4523 vldm(al, kDataTypeValueNone, rn, write_back, dreglist); 4524 } 4525 void vldm(Condition cond, 4526 Register rn, 4527 WriteBack write_back, 4528 DRegisterList dreglist) { 4529 vldm(cond, kDataTypeValueNone, rn, write_back, dreglist); 4530 } 4531 4532 void vldm(Condition cond, 4533 DataType dt, 4534 Register rn, 4535 WriteBack write_back, 4536 SRegisterList sreglist); 4537 void vldm(DataType dt, 4538 Register rn, 4539 WriteBack write_back, 4540 SRegisterList sreglist) { 4541 vldm(al, dt, rn, write_back, sreglist); 4542 } 4543 void vldm(Register rn, WriteBack write_back, SRegisterList sreglist) { 4544 vldm(al, kDataTypeValueNone, rn, write_back, sreglist); 4545 } 4546 void vldm(Condition cond, 4547 Register rn, 4548 WriteBack write_back, 4549 SRegisterList sreglist) { 4550 vldm(cond, kDataTypeValueNone, rn, write_back, sreglist); 4551 } 4552 4553 void vldmdb(Condition cond, 4554 DataType dt, 4555 Register rn, 4556 WriteBack write_back, 4557 DRegisterList dreglist); 4558 void vldmdb(DataType dt, 4559 Register rn, 4560 WriteBack write_back, 4561 DRegisterList dreglist) { 4562 vldmdb(al, dt, rn, write_back, dreglist); 4563 } 4564 void vldmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 4565 vldmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 4566 } 4567 void vldmdb(Condition cond, 4568 Register rn, 4569 WriteBack write_back, 4570 DRegisterList dreglist) { 4571 vldmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 4572 } 4573 4574 void vldmdb(Condition cond, 4575 DataType dt, 4576 Register rn, 4577 WriteBack write_back, 4578 SRegisterList sreglist); 4579 void vldmdb(DataType dt, 4580 Register rn, 4581 WriteBack write_back, 4582 SRegisterList sreglist) { 4583 vldmdb(al, dt, rn, write_back, sreglist); 4584 } 4585 void vldmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 4586 vldmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 4587 } 4588 void vldmdb(Condition cond, 4589 Register rn, 4590 WriteBack write_back, 4591 SRegisterList sreglist) { 4592 vldmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 4593 } 4594 4595 void vldmia(Condition cond, 4596 DataType dt, 4597 Register rn, 4598 WriteBack write_back, 4599 DRegisterList dreglist); 4600 void vldmia(DataType dt, 4601 Register rn, 4602 WriteBack write_back, 4603 DRegisterList dreglist) { 4604 vldmia(al, dt, rn, write_back, dreglist); 4605 } 4606 void vldmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 4607 vldmia(al, kDataTypeValueNone, rn, write_back, dreglist); 4608 } 4609 void vldmia(Condition cond, 4610 Register rn, 4611 WriteBack write_back, 4612 DRegisterList dreglist) { 4613 vldmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 4614 } 4615 4616 void vldmia(Condition cond, 4617 DataType dt, 4618 Register rn, 4619 WriteBack write_back, 4620 SRegisterList sreglist); 4621 void vldmia(DataType dt, 4622 Register rn, 4623 WriteBack write_back, 4624 SRegisterList sreglist) { 4625 vldmia(al, dt, rn, write_back, sreglist); 4626 } 4627 void vldmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 4628 vldmia(al, kDataTypeValueNone, rn, write_back, sreglist); 4629 } 4630 void vldmia(Condition cond, 4631 Register rn, 4632 WriteBack write_back, 4633 SRegisterList sreglist) { 4634 vldmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 4635 } 4636 4637 void vldr(Condition cond, DataType dt, DRegister rd, Label* label); 4638 void vldr(DataType dt, DRegister rd, Label* label) { 4639 vldr(al, dt, rd, label); 4640 } 4641 void vldr(DRegister rd, Label* label) { vldr(al, Untyped64, rd, label); } 4642 void vldr(Condition cond, DRegister rd, Label* label) { 4643 vldr(cond, Untyped64, rd, label); 4644 } 4645 4646 void vldr(Condition cond, 4647 DataType dt, 4648 DRegister rd, 4649 const MemOperand& operand); 4650 void vldr(DataType dt, DRegister rd, const MemOperand& operand) { 4651 vldr(al, dt, rd, operand); 4652 } 4653 void vldr(DRegister rd, const MemOperand& operand) { 4654 vldr(al, Untyped64, rd, operand); 4655 } 4656 void vldr(Condition cond, DRegister rd, const MemOperand& operand) { 4657 vldr(cond, Untyped64, rd, operand); 4658 } 4659 4660 void vldr(Condition cond, DataType dt, SRegister rd, Label* label); 4661 void vldr(DataType dt, SRegister rd, Label* label) { 4662 vldr(al, dt, rd, label); 4663 } 4664 void vldr(SRegister rd, Label* label) { vldr(al, Untyped32, rd, label); } 4665 void vldr(Condition cond, SRegister rd, Label* label) { 4666 vldr(cond, Untyped32, rd, label); 4667 } 4668 4669 void vldr(Condition cond, 4670 DataType dt, 4671 SRegister rd, 4672 const MemOperand& operand); 4673 void vldr(DataType dt, SRegister rd, const MemOperand& operand) { 4674 vldr(al, dt, rd, operand); 4675 } 4676 void vldr(SRegister rd, const MemOperand& operand) { 4677 vldr(al, Untyped32, rd, operand); 4678 } 4679 void vldr(Condition cond, SRegister rd, const MemOperand& operand) { 4680 vldr(cond, Untyped32, rd, operand); 4681 } 4682 4683 void vmax( 4684 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4685 void vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4686 vmax(al, dt, rd, rn, rm); 4687 } 4688 4689 void vmax( 4690 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4691 void vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4692 vmax(al, dt, rd, rn, rm); 4693 } 4694 4695 void vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm); 4696 4697 void vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm); 4698 4699 void vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm); 4700 4701 void vmin( 4702 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4703 void vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4704 vmin(al, dt, rd, rn, rm); 4705 } 4706 4707 void vmin( 4708 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4709 void vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4710 vmin(al, dt, rd, rn, rm); 4711 } 4712 4713 void vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm); 4714 4715 void vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm); 4716 4717 void vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm); 4718 4719 void vmla(Condition cond, 4720 DataType dt, 4721 DRegister rd, 4722 DRegister rn, 4723 DRegisterLane rm); 4724 void vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 4725 vmla(al, dt, rd, rn, rm); 4726 } 4727 4728 void vmla(Condition cond, 4729 DataType dt, 4730 QRegister rd, 4731 QRegister rn, 4732 DRegisterLane rm); 4733 void vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 4734 vmla(al, dt, rd, rn, rm); 4735 } 4736 4737 void vmla( 4738 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4739 void vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4740 vmla(al, dt, rd, rn, rm); 4741 } 4742 4743 void vmla( 4744 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4745 void vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4746 vmla(al, dt, rd, rn, rm); 4747 } 4748 4749 void vmla( 4750 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4751 void vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4752 vmla(al, dt, rd, rn, rm); 4753 } 4754 4755 void vmlal(Condition cond, 4756 DataType dt, 4757 QRegister rd, 4758 DRegister rn, 4759 DRegisterLane rm); 4760 void vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 4761 vmlal(al, dt, rd, rn, rm); 4762 } 4763 4764 void vmlal( 4765 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4766 void vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4767 vmlal(al, dt, rd, rn, rm); 4768 } 4769 4770 void vmls(Condition cond, 4771 DataType dt, 4772 DRegister rd, 4773 DRegister rn, 4774 DRegisterLane rm); 4775 void vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 4776 vmls(al, dt, rd, rn, rm); 4777 } 4778 4779 void vmls(Condition cond, 4780 DataType dt, 4781 QRegister rd, 4782 QRegister rn, 4783 DRegisterLane rm); 4784 void vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 4785 vmls(al, dt, rd, rn, rm); 4786 } 4787 4788 void vmls( 4789 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4790 void vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4791 vmls(al, dt, rd, rn, rm); 4792 } 4793 4794 void vmls( 4795 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4796 void vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4797 vmls(al, dt, rd, rn, rm); 4798 } 4799 4800 void vmls( 4801 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4802 void vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4803 vmls(al, dt, rd, rn, rm); 4804 } 4805 4806 void vmlsl(Condition cond, 4807 DataType dt, 4808 QRegister rd, 4809 DRegister rn, 4810 DRegisterLane rm); 4811 void vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 4812 vmlsl(al, dt, rd, rn, rm); 4813 } 4814 4815 void vmlsl( 4816 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4817 void vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4818 vmlsl(al, dt, rd, rn, rm); 4819 } 4820 4821 void vmov(Condition cond, Register rt, SRegister rn); 4822 void vmov(Register rt, SRegister rn) { vmov(al, rt, rn); } 4823 4824 void vmov(Condition cond, SRegister rn, Register rt); 4825 void vmov(SRegister rn, Register rt) { vmov(al, rn, rt); } 4826 4827 void vmov(Condition cond, Register rt, Register rt2, DRegister rm); 4828 void vmov(Register rt, Register rt2, DRegister rm) { vmov(al, rt, rt2, rm); } 4829 4830 void vmov(Condition cond, DRegister rm, Register rt, Register rt2); 4831 void vmov(DRegister rm, Register rt, Register rt2) { vmov(al, rm, rt, rt2); } 4832 4833 void vmov( 4834 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1); 4835 void vmov(Register rt, Register rt2, SRegister rm, SRegister rm1) { 4836 vmov(al, rt, rt2, rm, rm1); 4837 } 4838 4839 void vmov( 4840 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2); 4841 void vmov(SRegister rm, SRegister rm1, Register rt, Register rt2) { 4842 vmov(al, rm, rm1, rt, rt2); 4843 } 4844 4845 void vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt); 4846 void vmov(DataType dt, DRegisterLane rd, Register rt) { 4847 vmov(al, dt, rd, rt); 4848 } 4849 void vmov(DRegisterLane rd, Register rt) { 4850 vmov(al, kDataTypeValueNone, rd, rt); 4851 } 4852 void vmov(Condition cond, DRegisterLane rd, Register rt) { 4853 vmov(cond, kDataTypeValueNone, rd, rt); 4854 } 4855 4856 void vmov(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 4857 void vmov(DataType dt, DRegister rd, const DOperand& operand) { 4858 vmov(al, dt, rd, operand); 4859 } 4860 4861 void vmov(Condition cond, DataType dt, QRegister rd, const QOperand& operand); 4862 void vmov(DataType dt, QRegister rd, const QOperand& operand) { 4863 vmov(al, dt, rd, operand); 4864 } 4865 4866 void vmov(Condition cond, DataType dt, SRegister rd, const SOperand& operand); 4867 void vmov(DataType dt, SRegister rd, const SOperand& operand) { 4868 vmov(al, dt, rd, operand); 4869 } 4870 4871 void vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn); 4872 void vmov(DataType dt, Register rt, DRegisterLane rn) { 4873 vmov(al, dt, rt, rn); 4874 } 4875 void vmov(Register rt, DRegisterLane rn) { 4876 vmov(al, kDataTypeValueNone, rt, rn); 4877 } 4878 void vmov(Condition cond, Register rt, DRegisterLane rn) { 4879 vmov(cond, kDataTypeValueNone, rt, rn); 4880 } 4881 4882 void vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm); 4883 void vmovl(DataType dt, QRegister rd, DRegister rm) { vmovl(al, dt, rd, rm); } 4884 4885 void vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm); 4886 void vmovn(DataType dt, DRegister rd, QRegister rm) { vmovn(al, dt, rd, rm); } 4887 4888 void vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg); 4889 void vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) { 4890 vmrs(al, rt, spec_reg); 4891 } 4892 4893 void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt); 4894 void vmsr(SpecialFPRegister spec_reg, Register rt) { vmsr(al, spec_reg, rt); } 4895 4896 void vmul(Condition cond, 4897 DataType dt, 4898 DRegister rd, 4899 DRegister rn, 4900 DRegister dm, 4901 unsigned index); 4902 void vmul( 4903 DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) { 4904 vmul(al, dt, rd, rn, dm, index); 4905 } 4906 4907 void vmul(Condition cond, 4908 DataType dt, 4909 QRegister rd, 4910 QRegister rn, 4911 DRegister dm, 4912 unsigned index); 4913 void vmul( 4914 DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) { 4915 vmul(al, dt, rd, rn, dm, index); 4916 } 4917 4918 void vmul( 4919 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4920 void vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4921 vmul(al, dt, rd, rn, rm); 4922 } 4923 4924 void vmul( 4925 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4926 void vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4927 vmul(al, dt, rd, rn, rm); 4928 } 4929 4930 void vmul( 4931 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4932 void vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4933 vmul(al, dt, rd, rn, rm); 4934 } 4935 4936 void vmull(Condition cond, 4937 DataType dt, 4938 QRegister rd, 4939 DRegister rn, 4940 DRegister dm, 4941 unsigned index); 4942 void vmull( 4943 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 4944 vmull(al, dt, rd, rn, dm, index); 4945 } 4946 4947 void vmull( 4948 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4949 void vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4950 vmull(al, dt, rd, rn, rm); 4951 } 4952 4953 void vmvn(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 4954 void vmvn(DataType dt, DRegister rd, const DOperand& operand) { 4955 vmvn(al, dt, rd, operand); 4956 } 4957 4958 void vmvn(Condition cond, DataType dt, QRegister rd, const QOperand& operand); 4959 void vmvn(DataType dt, QRegister rd, const QOperand& operand) { 4960 vmvn(al, dt, rd, operand); 4961 } 4962 4963 void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm); 4964 void vneg(DataType dt, DRegister rd, DRegister rm) { vneg(al, dt, rd, rm); } 4965 4966 void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm); 4967 void vneg(DataType dt, QRegister rd, QRegister rm) { vneg(al, dt, rd, rm); } 4968 4969 void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm); 4970 void vneg(DataType dt, SRegister rd, SRegister rm) { vneg(al, dt, rd, rm); } 4971 4972 void vnmla( 4973 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4974 void vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4975 vnmla(al, dt, rd, rn, rm); 4976 } 4977 4978 void vnmla( 4979 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4980 void vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4981 vnmla(al, dt, rd, rn, rm); 4982 } 4983 4984 void vnmls( 4985 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4986 void vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4987 vnmls(al, dt, rd, rn, rm); 4988 } 4989 4990 void vnmls( 4991 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4992 void vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4993 vnmls(al, dt, rd, rn, rm); 4994 } 4995 4996 void vnmul( 4997 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4998 void vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4999 vnmul(al, dt, rd, rn, rm); 5000 } 5001 5002 void vnmul( 5003 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5004 void vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5005 vnmul(al, dt, rd, rn, rm); 5006 } 5007 5008 void vorn(Condition cond, 5009 DataType dt, 5010 DRegister rd, 5011 DRegister rn, 5012 const DOperand& operand); 5013 void vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 5014 vorn(al, dt, rd, rn, operand); 5015 } 5016 5017 void vorn(Condition cond, 5018 DataType dt, 5019 QRegister rd, 5020 QRegister rn, 5021 const QOperand& operand); 5022 void vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 5023 vorn(al, dt, rd, rn, operand); 5024 } 5025 5026 void vorr(Condition cond, 5027 DataType dt, 5028 DRegister rd, 5029 DRegister rn, 5030 const DOperand& operand); 5031 void vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 5032 vorr(al, dt, rd, rn, operand); 5033 } 5034 void vorr(DRegister rd, DRegister rn, const DOperand& operand) { 5035 vorr(al, kDataTypeValueNone, rd, rn, operand); 5036 } 5037 void vorr(Condition cond, 5038 DRegister rd, 5039 DRegister rn, 5040 const DOperand& operand) { 5041 vorr(cond, kDataTypeValueNone, rd, rn, operand); 5042 } 5043 5044 void vorr(Condition cond, 5045 DataType dt, 5046 QRegister rd, 5047 QRegister rn, 5048 const QOperand& operand); 5049 void vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 5050 vorr(al, dt, rd, rn, operand); 5051 } 5052 void vorr(QRegister rd, QRegister rn, const QOperand& operand) { 5053 vorr(al, kDataTypeValueNone, rd, rn, operand); 5054 } 5055 void vorr(Condition cond, 5056 QRegister rd, 5057 QRegister rn, 5058 const QOperand& operand) { 5059 vorr(cond, kDataTypeValueNone, rd, rn, operand); 5060 } 5061 5062 void vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm); 5063 void vpadal(DataType dt, DRegister rd, DRegister rm) { 5064 vpadal(al, dt, rd, rm); 5065 } 5066 5067 void vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm); 5068 void vpadal(DataType dt, QRegister rd, QRegister rm) { 5069 vpadal(al, dt, rd, rm); 5070 } 5071 5072 void vpadd( 5073 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5074 void vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5075 vpadd(al, dt, rd, rn, rm); 5076 } 5077 5078 void vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm); 5079 void vpaddl(DataType dt, DRegister rd, DRegister rm) { 5080 vpaddl(al, dt, rd, rm); 5081 } 5082 5083 void vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm); 5084 void vpaddl(DataType dt, QRegister rd, QRegister rm) { 5085 vpaddl(al, dt, rd, rm); 5086 } 5087 5088 void vpmax( 5089 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5090 void vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5091 vpmax(al, dt, rd, rn, rm); 5092 } 5093 5094 void vpmin( 5095 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5096 void vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5097 vpmin(al, dt, rd, rn, rm); 5098 } 5099 5100 void vpop(Condition cond, DataType dt, DRegisterList dreglist); 5101 void vpop(DataType dt, DRegisterList dreglist) { vpop(al, dt, dreglist); } 5102 void vpop(DRegisterList dreglist) { vpop(al, kDataTypeValueNone, dreglist); } 5103 void vpop(Condition cond, DRegisterList dreglist) { 5104 vpop(cond, kDataTypeValueNone, dreglist); 5105 } 5106 5107 void vpop(Condition cond, DataType dt, SRegisterList sreglist); 5108 void vpop(DataType dt, SRegisterList sreglist) { vpop(al, dt, sreglist); } 5109 void vpop(SRegisterList sreglist) { vpop(al, kDataTypeValueNone, sreglist); } 5110 void vpop(Condition cond, SRegisterList sreglist) { 5111 vpop(cond, kDataTypeValueNone, sreglist); 5112 } 5113 5114 void vpush(Condition cond, DataType dt, DRegisterList dreglist); 5115 void vpush(DataType dt, DRegisterList dreglist) { vpush(al, dt, dreglist); } 5116 void vpush(DRegisterList dreglist) { 5117 vpush(al, kDataTypeValueNone, dreglist); 5118 } 5119 void vpush(Condition cond, DRegisterList dreglist) { 5120 vpush(cond, kDataTypeValueNone, dreglist); 5121 } 5122 5123 void vpush(Condition cond, DataType dt, SRegisterList sreglist); 5124 void vpush(DataType dt, SRegisterList sreglist) { vpush(al, dt, sreglist); } 5125 void vpush(SRegisterList sreglist) { 5126 vpush(al, kDataTypeValueNone, sreglist); 5127 } 5128 void vpush(Condition cond, SRegisterList sreglist) { 5129 vpush(cond, kDataTypeValueNone, sreglist); 5130 } 5131 5132 void vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm); 5133 void vqabs(DataType dt, DRegister rd, DRegister rm) { vqabs(al, dt, rd, rm); } 5134 5135 void vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm); 5136 void vqabs(DataType dt, QRegister rd, QRegister rm) { vqabs(al, dt, rd, rm); } 5137 5138 void vqadd( 5139 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5140 void vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5141 vqadd(al, dt, rd, rn, rm); 5142 } 5143 5144 void vqadd( 5145 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5146 void vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5147 vqadd(al, dt, rd, rn, rm); 5148 } 5149 5150 void vqdmlal( 5151 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5152 void vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5153 vqdmlal(al, dt, rd, rn, rm); 5154 } 5155 5156 void vqdmlal(Condition cond, 5157 DataType dt, 5158 QRegister rd, 5159 DRegister rn, 5160 DRegister dm, 5161 unsigned index); 5162 void vqdmlal( 5163 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 5164 vqdmlal(al, dt, rd, rn, dm, index); 5165 } 5166 5167 void vqdmlsl( 5168 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5169 void vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5170 vqdmlsl(al, dt, rd, rn, rm); 5171 } 5172 5173 void vqdmlsl(Condition cond, 5174 DataType dt, 5175 QRegister rd, 5176 DRegister rn, 5177 DRegister dm, 5178 unsigned index); 5179 void vqdmlsl( 5180 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 5181 vqdmlsl(al, dt, rd, rn, dm, index); 5182 } 5183 5184 void vqdmulh( 5185 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5186 void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5187 vqdmulh(al, dt, rd, rn, rm); 5188 } 5189 5190 void vqdmulh( 5191 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5192 void vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5193 vqdmulh(al, dt, rd, rn, rm); 5194 } 5195 5196 void vqdmulh(Condition cond, 5197 DataType dt, 5198 DRegister rd, 5199 DRegister rn, 5200 DRegisterLane rm); 5201 void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 5202 vqdmulh(al, dt, rd, rn, rm); 5203 } 5204 5205 void vqdmulh(Condition cond, 5206 DataType dt, 5207 QRegister rd, 5208 QRegister rn, 5209 DRegisterLane rm); 5210 void vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 5211 vqdmulh(al, dt, rd, rn, rm); 5212 } 5213 5214 void vqdmull( 5215 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5216 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5217 vqdmull(al, dt, rd, rn, rm); 5218 } 5219 5220 void vqdmull(Condition cond, 5221 DataType dt, 5222 QRegister rd, 5223 DRegister rn, 5224 DRegisterLane rm); 5225 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 5226 vqdmull(al, dt, rd, rn, rm); 5227 } 5228 5229 void vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm); 5230 void vqmovn(DataType dt, DRegister rd, QRegister rm) { 5231 vqmovn(al, dt, rd, rm); 5232 } 5233 5234 void vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm); 5235 void vqmovun(DataType dt, DRegister rd, QRegister rm) { 5236 vqmovun(al, dt, rd, rm); 5237 } 5238 5239 void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm); 5240 void vqneg(DataType dt, DRegister rd, DRegister rm) { vqneg(al, dt, rd, rm); } 5241 5242 void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm); 5243 void vqneg(DataType dt, QRegister rd, QRegister rm) { vqneg(al, dt, rd, rm); } 5244 5245 void vqrdmulh( 5246 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5247 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5248 vqrdmulh(al, dt, rd, rn, rm); 5249 } 5250 5251 void vqrdmulh( 5252 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5253 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5254 vqrdmulh(al, dt, rd, rn, rm); 5255 } 5256 5257 void vqrdmulh(Condition cond, 5258 DataType dt, 5259 DRegister rd, 5260 DRegister rn, 5261 DRegisterLane rm); 5262 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 5263 vqrdmulh(al, dt, rd, rn, rm); 5264 } 5265 5266 void vqrdmulh(Condition cond, 5267 DataType dt, 5268 QRegister rd, 5269 QRegister rn, 5270 DRegisterLane rm); 5271 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 5272 vqrdmulh(al, dt, rd, rn, rm); 5273 } 5274 5275 void vqrshl( 5276 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn); 5277 void vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 5278 vqrshl(al, dt, rd, rm, rn); 5279 } 5280 5281 void vqrshl( 5282 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn); 5283 void vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 5284 vqrshl(al, dt, rd, rm, rn); 5285 } 5286 5287 void vqrshrn(Condition cond, 5288 DataType dt, 5289 DRegister rd, 5290 QRegister rm, 5291 const QOperand& operand); 5292 void vqrshrn(DataType dt, 5293 DRegister rd, 5294 QRegister rm, 5295 const QOperand& operand) { 5296 vqrshrn(al, dt, rd, rm, operand); 5297 } 5298 5299 void vqrshrun(Condition cond, 5300 DataType dt, 5301 DRegister rd, 5302 QRegister rm, 5303 const QOperand& operand); 5304 void vqrshrun(DataType dt, 5305 DRegister rd, 5306 QRegister rm, 5307 const QOperand& operand) { 5308 vqrshrun(al, dt, rd, rm, operand); 5309 } 5310 5311 void vqshl(Condition cond, 5312 DataType dt, 5313 DRegister rd, 5314 DRegister rm, 5315 const DOperand& operand); 5316 void vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5317 vqshl(al, dt, rd, rm, operand); 5318 } 5319 5320 void vqshl(Condition cond, 5321 DataType dt, 5322 QRegister rd, 5323 QRegister rm, 5324 const QOperand& operand); 5325 void vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5326 vqshl(al, dt, rd, rm, operand); 5327 } 5328 5329 void vqshlu(Condition cond, 5330 DataType dt, 5331 DRegister rd, 5332 DRegister rm, 5333 const DOperand& operand); 5334 void vqshlu(DataType dt, 5335 DRegister rd, 5336 DRegister rm, 5337 const DOperand& operand) { 5338 vqshlu(al, dt, rd, rm, operand); 5339 } 5340 5341 void vqshlu(Condition cond, 5342 DataType dt, 5343 QRegister rd, 5344 QRegister rm, 5345 const QOperand& operand); 5346 void vqshlu(DataType dt, 5347 QRegister rd, 5348 QRegister rm, 5349 const QOperand& operand) { 5350 vqshlu(al, dt, rd, rm, operand); 5351 } 5352 5353 void vqshrn(Condition cond, 5354 DataType dt, 5355 DRegister rd, 5356 QRegister rm, 5357 const QOperand& operand); 5358 void vqshrn(DataType dt, 5359 DRegister rd, 5360 QRegister rm, 5361 const QOperand& operand) { 5362 vqshrn(al, dt, rd, rm, operand); 5363 } 5364 5365 void vqshrun(Condition cond, 5366 DataType dt, 5367 DRegister rd, 5368 QRegister rm, 5369 const QOperand& operand); 5370 void vqshrun(DataType dt, 5371 DRegister rd, 5372 QRegister rm, 5373 const QOperand& operand) { 5374 vqshrun(al, dt, rd, rm, operand); 5375 } 5376 5377 void vqsub( 5378 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5379 void vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5380 vqsub(al, dt, rd, rn, rm); 5381 } 5382 5383 void vqsub( 5384 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5385 void vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5386 vqsub(al, dt, rd, rn, rm); 5387 } 5388 5389 void vraddhn( 5390 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 5391 void vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5392 vraddhn(al, dt, rd, rn, rm); 5393 } 5394 5395 void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm); 5396 void vrecpe(DataType dt, DRegister rd, DRegister rm) { 5397 vrecpe(al, dt, rd, rm); 5398 } 5399 5400 void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm); 5401 void vrecpe(DataType dt, QRegister rd, QRegister rm) { 5402 vrecpe(al, dt, rd, rm); 5403 } 5404 5405 void vrecps( 5406 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5407 void vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5408 vrecps(al, dt, rd, rn, rm); 5409 } 5410 5411 void vrecps( 5412 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5413 void vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5414 vrecps(al, dt, rd, rn, rm); 5415 } 5416 5417 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm); 5418 void vrev16(DataType dt, DRegister rd, DRegister rm) { 5419 vrev16(al, dt, rd, rm); 5420 } 5421 5422 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm); 5423 void vrev16(DataType dt, QRegister rd, QRegister rm) { 5424 vrev16(al, dt, rd, rm); 5425 } 5426 5427 void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm); 5428 void vrev32(DataType dt, DRegister rd, DRegister rm) { 5429 vrev32(al, dt, rd, rm); 5430 } 5431 5432 void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm); 5433 void vrev32(DataType dt, QRegister rd, QRegister rm) { 5434 vrev32(al, dt, rd, rm); 5435 } 5436 5437 void vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm); 5438 void vrev64(DataType dt, DRegister rd, DRegister rm) { 5439 vrev64(al, dt, rd, rm); 5440 } 5441 5442 void vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm); 5443 void vrev64(DataType dt, QRegister rd, QRegister rm) { 5444 vrev64(al, dt, rd, rm); 5445 } 5446 5447 void vrhadd( 5448 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5449 void vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5450 vrhadd(al, dt, rd, rn, rm); 5451 } 5452 5453 void vrhadd( 5454 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5455 void vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5456 vrhadd(al, dt, rd, rn, rm); 5457 } 5458 5459 void vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5460 5461 void vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5462 5463 void vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5464 5465 void vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5466 5467 void vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5468 5469 void vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5470 5471 void vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5472 5473 void vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5474 5475 void vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5476 5477 void vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5478 5479 void vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5480 5481 void vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5482 5483 void vrintr( 5484 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5485 void vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5486 vrintr(al, dt1, dt2, rd, rm); 5487 } 5488 5489 void vrintr( 5490 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5491 void vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5492 vrintr(al, dt1, dt2, rd, rm); 5493 } 5494 5495 void vrintx( 5496 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5497 void vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5498 vrintx(al, dt1, dt2, rd, rm); 5499 } 5500 5501 void vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5502 5503 void vrintx( 5504 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5505 void vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5506 vrintx(al, dt1, dt2, rd, rm); 5507 } 5508 5509 void vrintz( 5510 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5511 void vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5512 vrintz(al, dt1, dt2, rd, rm); 5513 } 5514 5515 void vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5516 5517 void vrintz( 5518 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5519 void vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5520 vrintz(al, dt1, dt2, rd, rm); 5521 } 5522 5523 void vrshl( 5524 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn); 5525 void vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 5526 vrshl(al, dt, rd, rm, rn); 5527 } 5528 5529 void vrshl( 5530 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn); 5531 void vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 5532 vrshl(al, dt, rd, rm, rn); 5533 } 5534 5535 void vrshr(Condition cond, 5536 DataType dt, 5537 DRegister rd, 5538 DRegister rm, 5539 const DOperand& operand); 5540 void vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5541 vrshr(al, dt, rd, rm, operand); 5542 } 5543 5544 void vrshr(Condition cond, 5545 DataType dt, 5546 QRegister rd, 5547 QRegister rm, 5548 const QOperand& operand); 5549 void vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5550 vrshr(al, dt, rd, rm, operand); 5551 } 5552 5553 void vrshrn(Condition cond, 5554 DataType dt, 5555 DRegister rd, 5556 QRegister rm, 5557 const QOperand& operand); 5558 void vrshrn(DataType dt, 5559 DRegister rd, 5560 QRegister rm, 5561 const QOperand& operand) { 5562 vrshrn(al, dt, rd, rm, operand); 5563 } 5564 5565 void vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm); 5566 void vrsqrte(DataType dt, DRegister rd, DRegister rm) { 5567 vrsqrte(al, dt, rd, rm); 5568 } 5569 5570 void vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm); 5571 void vrsqrte(DataType dt, QRegister rd, QRegister rm) { 5572 vrsqrte(al, dt, rd, rm); 5573 } 5574 5575 void vrsqrts( 5576 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5577 void vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5578 vrsqrts(al, dt, rd, rn, rm); 5579 } 5580 5581 void vrsqrts( 5582 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5583 void vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5584 vrsqrts(al, dt, rd, rn, rm); 5585 } 5586 5587 void vrsra(Condition cond, 5588 DataType dt, 5589 DRegister rd, 5590 DRegister rm, 5591 const DOperand& operand); 5592 void vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5593 vrsra(al, dt, rd, rm, operand); 5594 } 5595 5596 void vrsra(Condition cond, 5597 DataType dt, 5598 QRegister rd, 5599 QRegister rm, 5600 const QOperand& operand); 5601 void vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5602 vrsra(al, dt, rd, rm, operand); 5603 } 5604 5605 void vrsubhn( 5606 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 5607 void vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5608 vrsubhn(al, dt, rd, rn, rm); 5609 } 5610 5611 void vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5612 5613 void vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5614 5615 void vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5616 5617 void vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5618 5619 void vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5620 5621 void vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5622 5623 void vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5624 5625 void vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5626 5627 void vshl(Condition cond, 5628 DataType dt, 5629 DRegister rd, 5630 DRegister rm, 5631 const DOperand& operand); 5632 void vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5633 vshl(al, dt, rd, rm, operand); 5634 } 5635 5636 void vshl(Condition cond, 5637 DataType dt, 5638 QRegister rd, 5639 QRegister rm, 5640 const QOperand& operand); 5641 void vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5642 vshl(al, dt, rd, rm, operand); 5643 } 5644 5645 void vshll(Condition cond, 5646 DataType dt, 5647 QRegister rd, 5648 DRegister rm, 5649 const DOperand& operand); 5650 void vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) { 5651 vshll(al, dt, rd, rm, operand); 5652 } 5653 5654 void vshr(Condition cond, 5655 DataType dt, 5656 DRegister rd, 5657 DRegister rm, 5658 const DOperand& operand); 5659 void vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5660 vshr(al, dt, rd, rm, operand); 5661 } 5662 5663 void vshr(Condition cond, 5664 DataType dt, 5665 QRegister rd, 5666 QRegister rm, 5667 const QOperand& operand); 5668 void vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5669 vshr(al, dt, rd, rm, operand); 5670 } 5671 5672 void vshrn(Condition cond, 5673 DataType dt, 5674 DRegister rd, 5675 QRegister rm, 5676 const QOperand& operand); 5677 void vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) { 5678 vshrn(al, dt, rd, rm, operand); 5679 } 5680 5681 void vsli(Condition cond, 5682 DataType dt, 5683 DRegister rd, 5684 DRegister rm, 5685 const DOperand& operand); 5686 void vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5687 vsli(al, dt, rd, rm, operand); 5688 } 5689 5690 void vsli(Condition cond, 5691 DataType dt, 5692 QRegister rd, 5693 QRegister rm, 5694 const QOperand& operand); 5695 void vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5696 vsli(al, dt, rd, rm, operand); 5697 } 5698 5699 void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm); 5700 void vsqrt(DataType dt, SRegister rd, SRegister rm) { vsqrt(al, dt, rd, rm); } 5701 5702 void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm); 5703 void vsqrt(DataType dt, DRegister rd, DRegister rm) { vsqrt(al, dt, rd, rm); } 5704 5705 void vsra(Condition cond, 5706 DataType dt, 5707 DRegister rd, 5708 DRegister rm, 5709 const DOperand& operand); 5710 void vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5711 vsra(al, dt, rd, rm, operand); 5712 } 5713 5714 void vsra(Condition cond, 5715 DataType dt, 5716 QRegister rd, 5717 QRegister rm, 5718 const QOperand& operand); 5719 void vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5720 vsra(al, dt, rd, rm, operand); 5721 } 5722 5723 void vsri(Condition cond, 5724 DataType dt, 5725 DRegister rd, 5726 DRegister rm, 5727 const DOperand& operand); 5728 void vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5729 vsri(al, dt, rd, rm, operand); 5730 } 5731 5732 void vsri(Condition cond, 5733 DataType dt, 5734 QRegister rd, 5735 QRegister rm, 5736 const QOperand& operand); 5737 void vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5738 vsri(al, dt, rd, rm, operand); 5739 } 5740 5741 void vst1(Condition cond, 5742 DataType dt, 5743 const NeonRegisterList& nreglist, 5744 const AlignedMemOperand& operand); 5745 void vst1(DataType dt, 5746 const NeonRegisterList& nreglist, 5747 const AlignedMemOperand& operand) { 5748 vst1(al, dt, nreglist, operand); 5749 } 5750 5751 void vst2(Condition cond, 5752 DataType dt, 5753 const NeonRegisterList& nreglist, 5754 const AlignedMemOperand& operand); 5755 void vst2(DataType dt, 5756 const NeonRegisterList& nreglist, 5757 const AlignedMemOperand& operand) { 5758 vst2(al, dt, nreglist, operand); 5759 } 5760 5761 void vst3(Condition cond, 5762 DataType dt, 5763 const NeonRegisterList& nreglist, 5764 const AlignedMemOperand& operand); 5765 void vst3(DataType dt, 5766 const NeonRegisterList& nreglist, 5767 const AlignedMemOperand& operand) { 5768 vst3(al, dt, nreglist, operand); 5769 } 5770 5771 void vst3(Condition cond, 5772 DataType dt, 5773 const NeonRegisterList& nreglist, 5774 const MemOperand& operand); 5775 void vst3(DataType dt, 5776 const NeonRegisterList& nreglist, 5777 const MemOperand& operand) { 5778 vst3(al, dt, nreglist, operand); 5779 } 5780 5781 void vst4(Condition cond, 5782 DataType dt, 5783 const NeonRegisterList& nreglist, 5784 const AlignedMemOperand& operand); 5785 void vst4(DataType dt, 5786 const NeonRegisterList& nreglist, 5787 const AlignedMemOperand& operand) { 5788 vst4(al, dt, nreglist, operand); 5789 } 5790 5791 void vstm(Condition cond, 5792 DataType dt, 5793 Register rn, 5794 WriteBack write_back, 5795 DRegisterList dreglist); 5796 void vstm(DataType dt, 5797 Register rn, 5798 WriteBack write_back, 5799 DRegisterList dreglist) { 5800 vstm(al, dt, rn, write_back, dreglist); 5801 } 5802 void vstm(Register rn, WriteBack write_back, DRegisterList dreglist) { 5803 vstm(al, kDataTypeValueNone, rn, write_back, dreglist); 5804 } 5805 void vstm(Condition cond, 5806 Register rn, 5807 WriteBack write_back, 5808 DRegisterList dreglist) { 5809 vstm(cond, kDataTypeValueNone, rn, write_back, dreglist); 5810 } 5811 5812 void vstm(Condition cond, 5813 DataType dt, 5814 Register rn, 5815 WriteBack write_back, 5816 SRegisterList sreglist); 5817 void vstm(DataType dt, 5818 Register rn, 5819 WriteBack write_back, 5820 SRegisterList sreglist) { 5821 vstm(al, dt, rn, write_back, sreglist); 5822 } 5823 void vstm(Register rn, WriteBack write_back, SRegisterList sreglist) { 5824 vstm(al, kDataTypeValueNone, rn, write_back, sreglist); 5825 } 5826 void vstm(Condition cond, 5827 Register rn, 5828 WriteBack write_back, 5829 SRegisterList sreglist) { 5830 vstm(cond, kDataTypeValueNone, rn, write_back, sreglist); 5831 } 5832 5833 void vstmdb(Condition cond, 5834 DataType dt, 5835 Register rn, 5836 WriteBack write_back, 5837 DRegisterList dreglist); 5838 void vstmdb(DataType dt, 5839 Register rn, 5840 WriteBack write_back, 5841 DRegisterList dreglist) { 5842 vstmdb(al, dt, rn, write_back, dreglist); 5843 } 5844 void vstmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 5845 vstmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 5846 } 5847 void vstmdb(Condition cond, 5848 Register rn, 5849 WriteBack write_back, 5850 DRegisterList dreglist) { 5851 vstmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 5852 } 5853 5854 void vstmdb(Condition cond, 5855 DataType dt, 5856 Register rn, 5857 WriteBack write_back, 5858 SRegisterList sreglist); 5859 void vstmdb(DataType dt, 5860 Register rn, 5861 WriteBack write_back, 5862 SRegisterList sreglist) { 5863 vstmdb(al, dt, rn, write_back, sreglist); 5864 } 5865 void vstmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 5866 vstmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 5867 } 5868 void vstmdb(Condition cond, 5869 Register rn, 5870 WriteBack write_back, 5871 SRegisterList sreglist) { 5872 vstmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 5873 } 5874 5875 void vstmia(Condition cond, 5876 DataType dt, 5877 Register rn, 5878 WriteBack write_back, 5879 DRegisterList dreglist); 5880 void vstmia(DataType dt, 5881 Register rn, 5882 WriteBack write_back, 5883 DRegisterList dreglist) { 5884 vstmia(al, dt, rn, write_back, dreglist); 5885 } 5886 void vstmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 5887 vstmia(al, kDataTypeValueNone, rn, write_back, dreglist); 5888 } 5889 void vstmia(Condition cond, 5890 Register rn, 5891 WriteBack write_back, 5892 DRegisterList dreglist) { 5893 vstmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 5894 } 5895 5896 void vstmia(Condition cond, 5897 DataType dt, 5898 Register rn, 5899 WriteBack write_back, 5900 SRegisterList sreglist); 5901 void vstmia(DataType dt, 5902 Register rn, 5903 WriteBack write_back, 5904 SRegisterList sreglist) { 5905 vstmia(al, dt, rn, write_back, sreglist); 5906 } 5907 void vstmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 5908 vstmia(al, kDataTypeValueNone, rn, write_back, sreglist); 5909 } 5910 void vstmia(Condition cond, 5911 Register rn, 5912 WriteBack write_back, 5913 SRegisterList sreglist) { 5914 vstmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 5915 } 5916 5917 void vstr(Condition cond, 5918 DataType dt, 5919 DRegister rd, 5920 const MemOperand& operand); 5921 void vstr(DataType dt, DRegister rd, const MemOperand& operand) { 5922 vstr(al, dt, rd, operand); 5923 } 5924 void vstr(DRegister rd, const MemOperand& operand) { 5925 vstr(al, Untyped64, rd, operand); 5926 } 5927 void vstr(Condition cond, DRegister rd, const MemOperand& operand) { 5928 vstr(cond, Untyped64, rd, operand); 5929 } 5930 5931 void vstr(Condition cond, 5932 DataType dt, 5933 SRegister rd, 5934 const MemOperand& operand); 5935 void vstr(DataType dt, SRegister rd, const MemOperand& operand) { 5936 vstr(al, dt, rd, operand); 5937 } 5938 void vstr(SRegister rd, const MemOperand& operand) { 5939 vstr(al, Untyped32, rd, operand); 5940 } 5941 void vstr(Condition cond, SRegister rd, const MemOperand& operand) { 5942 vstr(cond, Untyped32, rd, operand); 5943 } 5944 5945 void vsub( 5946 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5947 void vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5948 vsub(al, dt, rd, rn, rm); 5949 } 5950 5951 void vsub( 5952 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5953 void vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5954 vsub(al, dt, rd, rn, rm); 5955 } 5956 5957 void vsub( 5958 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 5959 void vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5960 vsub(al, dt, rd, rn, rm); 5961 } 5962 5963 void vsubhn( 5964 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 5965 void vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5966 vsubhn(al, dt, rd, rn, rm); 5967 } 5968 5969 void vsubl( 5970 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5971 void vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5972 vsubl(al, dt, rd, rn, rm); 5973 } 5974 5975 void vsubw( 5976 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 5977 void vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 5978 vsubw(al, dt, rd, rn, rm); 5979 } 5980 5981 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm); 5982 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } 5983 void vswp(DRegister rd, DRegister rm) { 5984 vswp(al, kDataTypeValueNone, rd, rm); 5985 } 5986 void vswp(Condition cond, DRegister rd, DRegister rm) { 5987 vswp(cond, kDataTypeValueNone, rd, rm); 5988 } 5989 5990 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm); 5991 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); } 5992 void vswp(QRegister rd, QRegister rm) { 5993 vswp(al, kDataTypeValueNone, rd, rm); 5994 } 5995 void vswp(Condition cond, QRegister rd, QRegister rm) { 5996 vswp(cond, kDataTypeValueNone, rd, rm); 5997 } 5998 5999 void vtbl(Condition cond, 6000 DataType dt, 6001 DRegister rd, 6002 const NeonRegisterList& nreglist, 6003 DRegister rm); 6004 void vtbl(DataType dt, 6005 DRegister rd, 6006 const NeonRegisterList& nreglist, 6007 DRegister rm) { 6008 vtbl(al, dt, rd, nreglist, rm); 6009 } 6010 6011 void vtbx(Condition cond, 6012 DataType dt, 6013 DRegister rd, 6014 const NeonRegisterList& nreglist, 6015 DRegister rm); 6016 void vtbx(DataType dt, 6017 DRegister rd, 6018 const NeonRegisterList& nreglist, 6019 DRegister rm) { 6020 vtbx(al, dt, rd, nreglist, rm); 6021 } 6022 6023 void vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm); 6024 void vtrn(DataType dt, DRegister rd, DRegister rm) { vtrn(al, dt, rd, rm); } 6025 6026 void vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm); 6027 void vtrn(DataType dt, QRegister rd, QRegister rm) { vtrn(al, dt, rd, rm); } 6028 6029 void vtst( 6030 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 6031 void vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6032 vtst(al, dt, rd, rn, rm); 6033 } 6034 6035 void vtst( 6036 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 6037 void vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6038 vtst(al, dt, rd, rn, rm); 6039 } 6040 6041 void vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm); 6042 void vuzp(DataType dt, DRegister rd, DRegister rm) { vuzp(al, dt, rd, rm); } 6043 6044 void vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm); 6045 void vuzp(DataType dt, QRegister rd, QRegister rm) { vuzp(al, dt, rd, rm); } 6046 6047 void vzip(Condition cond, DataType dt, DRegister rd, DRegister rm); 6048 void vzip(DataType dt, DRegister rd, DRegister rm) { vzip(al, dt, rd, rm); } 6049 6050 void vzip(Condition cond, DataType dt, QRegister rd, QRegister rm); 6051 void vzip(DataType dt, QRegister rd, QRegister rm) { vzip(al, dt, rd, rm); } 6052 6053 void yield(Condition cond, EncodingSize size); 6054 void yield() { yield(al, Best); } 6055 void yield(Condition cond) { yield(cond, Best); } 6056 void yield(EncodingSize size) { yield(al, size); } 6057 // End of generated code. 6058 virtual void UnimplementedDelegate(InstructionType type) { 6059 std::string error_message(std::string("Ill-formed '") + 6060 std::string(ToCString(type)) + 6061 std::string("' instruction.\n")); 6062 VIXL_ABORT_WITH_MSG(error_message.c_str()); 6063 } 6064 virtual bool AllowUnpredictable() { return allow_unpredictable_; } 6065 virtual bool AllowStronglyDiscouraged() { 6066 return allow_strongly_discouraged_; 6067 } 6068}; 6069 6070} // namespace aarch32 6071} // namespace vixl 6072 6073#endif // VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 6074