Searched refs:RC (Results 126 - 150 of 458) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
H A DBlackfinISelDAGToDAG.cpp119 static inline bool isCC(const TargetRegisterClass *RC) { argument
120 return BF::AnyCCRegClass.hasSubClassEq(RC);
123 static inline bool isDCC(const TargetRegisterClass *RC) { argument
124 return BF::DRegClass.hasSubClassEq(RC) || isCC(RC);
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp372 const TargetRegisterClass *RC = local
374 if (!RC)
382 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
383 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
396 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
397 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
492 const TargetRegisterClass *RC = nullptr; local
495 RC = &AArch64::GPR64RegClass;
499 RC = &AArch64::GPR32RegClass;
503 RC
2177 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
2281 loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
3280 genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind = FMAInstKind::Default) argument
3345 genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC) argument
3392 const TargetRegisterClass *RC; local
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H A DAArch64RegisterInfo.h70 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
96 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
/external/llvm/lib/Target/Hexagon/
H A DBitTracker.cpp50 // RegisterCell RC = BT.get(Reg);
51 // if (RC[3].is(1))
106 raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { argument
107 unsigned n = RC.Bits.size();
117 for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) {
118 const BT::BitValue &V = RC[i];
119 const BT::BitValue &SV = RC[Start];
156 OS << "]:" << RC[Start]; local
159 const BT::BitValue &SV = RC[Start];
186 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigne argument
200 insert(const BT::RegisterCell &RC, const BitMask &M) argument
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H A DHexagonRegisterInfo.h65 const TargetRegisterClass *RC) const;
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp787 // Returns true if RC is a strict subclass.
788 // RC is a sub-class of this class if it is a valid replacement for any
792 // 1. All RC registers are also in this.
793 // 2. The RC spill size must not be smaller than our spill size.
794 // 3. RC spill alignment must be compatible with ours.
855 CodeGenRegisterClass &RC = *I; local
856 RC.SubClasses.resize(RegClasses.size());
857 RC.SubClasses.set(RC.EnumValue);
859 // Normally, all subclasses have IDs >= rci, unless RC i
1036 addToMaps(CodeGenRegisterClass *RC) argument
1048 getOrCreateSubClass(const CodeGenRegisterClass *RC, const CodeGenRegister::Vec *Members, StringRef Name) argument
1867 inferCommonSubClass(CodeGenRegisterClass *RC) argument
1908 inferSubClassWithSubReg(CodeGenRegisterClass *RC) argument
1952 inferMatchingSuperRegClass(CodeGenRegisterClass *RC, std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) argument
2029 CodeGenRegisterClass *RC = &*I; local
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H A DCodeGenRegisters.h290 // R:SubRegIndex in this RC for all R in SuperRC.
333 // Returns true if RC is a subclass.
334 // RC is a sub-class of this class if it is a valid replacement for any
338 // 1. All RC registers are also in this.
339 // 2. The RC spill size must not be smaller than our spill size.
340 // 3. RC spill alignment must be compatible with ours.
342 bool hasSubClass(const CodeGenRegisterClass *RC) const {
343 return SubClasses.test(RC->EnumValue);
413 Key(const CodeGenRegisterClass &RC) argument
414 : Members(&RC
535 inferMatchingSuperRegClass(CodeGenRegisterClass *RC) argument
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/external/llvm/lib/CodeGen/
H A DRegisterScavenging.cpp257 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
258 for (unsigned Reg : *RC) {
268 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { argument
270 for (unsigned Reg : *RC)
349 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
355 BitVector Candidates = TRI->getAllocatableSet(MF, RC);
366 BitVector Available = getRegsAvailable(RC);
382 // the requirements of the class RC.
384 unsigned NeedSize = RC->getSize();
385 unsigned NeedAlign = RC
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/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); local
155 unsigned VR = MRI.createVirtualRegister(RC);
158 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
169 const TargetRegisterClass *RC = RegInfo.intRegClass(4); local
170 unsigned VR = MRI.createVirtualRegister(RC);
175 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); local
188 unsigned VR0 = MRI.createVirtualRegister(RC);
189 unsigned VR1 = MRI.createVirtualRegister(RC);
196 TII.loadRegFromStack(MBB, I, VR0, FI, RC,
212 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); local
244 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); local
293 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
356 const TargetRegisterClass *RC = local
395 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? local
695 const TargetRegisterClass *RC = local
812 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
869 const TargetRegisterClass *RC = STI.hasMips64() ? local
883 const TargetRegisterClass *RC = local
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H A DMipsSEInstrInfo.h53 const TargetRegisterClass *RC,
60 const TargetRegisterClass *RC,
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp46 const TargetRegisterClass *RC,
52 if (RC == &SystemZ::GR32RegClass ||
53 RC == &SystemZ::ADDR32RegClass)
55 else if (RC == &SystemZ::GR64RegClass ||
56 RC == &SystemZ::ADDR64RegClass) {
58 } else if (RC == &SystemZ::FP32RegClass) {
60 } else if (RC == &SystemZ::FP64RegClass) {
62 } else if (RC == &SystemZ::GR64PRegClass) {
64 } else if (RC == &SystemZ::GR128RegClass) {
76 const TargetRegisterClass *RC,
43 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
73 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/clang/test/CodeGenCXX/
H A Ddevirtualize-virtual-function-calls-final.cpp187 struct RC final : public RA {
202 A *f(RC *x) {
215 A *fop(RC *x) {
/external/ltp/testcases/network/stress/route/
H A Droute6-change-if317 RC=0
319 test_body 1 || RC=`expr $RC + 1` # Case of route command
320 test_body 2 || RC=`expr $RC + 1` # Case of ip command
323 exit $RC
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
H A DXCoreFrameLowering.cpp296 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
298 it->getFrameIdx(), RC, TRI);
322 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
324 RC, TRI);
345 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass; local
354 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
356 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
364 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
365 RC
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/external/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegisterBank.h70 /// Check whether this register bank covers \p RC.
72 /// the registers that \p RC contains.
74 bool covers(const TargetRegisterClass &RC) const;
/external/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h37 getLargestLegalSuperClass(const TargetRegisterClass *RC,
H A DAVRInstrInfo.h81 const TargetRegisterClass *RC,
85 int FrameIndex, const TargetRegisterClass *RC,
/external/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp48 const TargetRegisterClass *RC,
54 if (RC == &BPF::GPRRegClass)
66 const TargetRegisterClass *RC,
72 if (RC == &BPF::GPRRegClass)
45 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
63 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp116 const TargetRegisterClass *RC,
120 const TargetRegisterClass *RC,
123 const TargetRegisterClass *RC,
158 const TargetRegisterClass *RC, bool IsZExt = true,
171 const TargetRegisterClass *RC);
173 const TargetRegisterClass *RC);
463 const TargetRegisterClass *RC,
469 // Otherwise, RC is the register class to use. If the result of the
477 (RC ? RC
462 PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, const TargetRegisterClass *RC, bool IsZExt, unsigned FP64LoadOpc) argument
609 const TargetRegisterClass *RC = local
625 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); local
988 const TargetRegisterClass *RC = &PPC::F8RCRegClass; local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; local
1095 const TargetRegisterClass *RC = local
1184 const TargetRegisterClass *RC = local
1346 const TargetRegisterClass *RC = local
1358 const TargetRegisterClass *RC = local
1675 const TargetRegisterClass *RC = local
1684 const TargetRegisterClass *RC = local
1837 const TargetRegisterClass *RC = local
1954 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass; local
2006 PPCMaterialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
2038 PPCMaterialize64BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
2109 const TargetRegisterClass *RC = local
2283 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : local
2302 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
2322 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill) argument
2335 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
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/external/ltp/testcases/kernel/controllers/memctl/
H A Drun_memctl_test.sh51 RC=0;
251 RC=$?; # Return status of the task being waited
254 if [ $RC -ne 0 ]
256 echo "Task $i exited abnormaly with return value: $RC";
/external/ltp/testcases/kernel/hotplug/cpu_hotplug/include/
H A Dcpuhotplug_hotplug.sh79 RC=$?
81 return $RC
100 RC=$?
102 return $RC
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp116 const TargetRegisterClass *RC = 0; local
118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
120 UseRC = RC;
121 else if (RC) {
123 TRI->getCommonSubClass(UseRC, RC);
199 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI); local
218 if (RegRC == RC) {
230 assert(RC && "Isn't a register operand!");
231 VRBase = MRI->createVirtualRegister(RC);
255 const TargetRegisterClass *RC local
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/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenIntrinsics.h86 std::vector<CodeGenIntrinsic> LoadIntrinsics(const RecordKeeper &RC,
/external/pcre/dist2/src/sljit/
H A DsljitNativePPC_32.c87 return push_inst(compiler, NOR | RC(flags) | S(src2) | A(dst) | B(src2));
95 return push_inst(compiler, CNTLZW | RC(flags) | S(src2) | A(dst));
180 return push_inst(compiler, AND | RC(flags) | S(src1) | A(dst) | B(src2));
196 return push_inst(compiler, OR | RC(flags) | S(src1) | A(dst) | B(src2));
212 return push_inst(compiler, XOR | RC(flags) | S(src1) | A(dst) | B(src2));
218 return push_inst(compiler, RLWINM | RC(flags) | S(src1) | A(dst) | (compiler->imm << 11) | ((31 - compiler->imm) << 1));
220 return push_inst(compiler, SLW | RC(flags) | S(src1) | A(dst) | B(src2));
226 return push_inst(compiler, RLWINM | RC(flags) | S(src1) | A(dst) | (((32 - compiler->imm) & 0x1f) << 11) | (compiler->imm << 6) | (31 << 1));
228 return push_inst(compiler, SRW | RC(flags) | S(src1) | A(dst) | B(src2));
236 FAIL_IF(push_inst(compiler, SRAWI | RC(flag
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/external/clang/lib/AST/
H A DRawCommentList.cpp272 void RawCommentList::addComment(const RawComment &RC, argument
274 if (RC.isInvalid())
280 RC.getLocStart())) {
287 if (RC.isOrdinary())
293 Comments.push_back(new (Allocator) RawComment(RC));
298 const RawComment &C2 = RC;
321 RC.isParseAllComments());
323 Comments.push_back(new (Allocator) RawComment(RC));

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