/external/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 56 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument 59 return RC->hasSubClassEq(MRI.getRegClass(Reg)); 60 } else if (RC->contains(Reg)) {
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/external/llvm/lib/Target/X86/ |
H A D | X86FixupSetCC.cpp | 160 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() local 163 unsigned ZeroReg = MRI->createVirtualRegister(RC); 164 unsigned InsertReg = MRI->createVirtualRegister(RC);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 126 const TargetRegisterClass *RC, 135 const TargetRegisterClass *RC, 233 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | AMDGPUInstrInfo.h | 81 const TargetRegisterClass *RC, 86 const TargetRegisterClass *RC, 122 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
H A D | BlackfinFrameLowering.cpp | 122 const TargetRegisterClass *RC = BF::DPRegisterClass; local 126 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 127 RC->getAlignment(),
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 168 const TargetRegisterClass *RC, 174 if (RC == Mips::CPURegsRegisterClass) 176 else if (RC == Mips::CPU64RegsRegisterClass) 178 else if (RC == Mips::FGR32RegisterClass) 180 else if (RC == Mips::AFGR64RegisterClass) 182 else if (RC == Mips::FGR64RegisterClass) 193 const TargetRegisterClass *RC, 200 if (RC == Mips::CPURegsRegisterClass) 202 else if (RC == Mips::CPU64RegsRegisterClass) 204 else if (RC 166 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 191 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | MipsInstrInfo.h | 165 const TargetRegisterClass *RC, 171 const TargetRegisterClass *RC,
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 40 const TargetRegisterClass *RC, 52 if (RC == &MSP430::GR16RegClass) 56 else if (RC == &MSP430::GR8RegClass) 67 const TargetRegisterClass *RC, 79 if (RC == &MSP430::GR16RegClass) 83 else if (RC == &MSP430::GR8RegClass) 37 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 64 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 38 const TargetRegisterClass *RC, 52 if (RC == &MSP430::GR16RegClass) 56 else if (RC == &MSP430::GR8RegClass) 67 const TargetRegisterClass *RC, 81 if (RC == &MSP430::GR16RegClass) 84 else if (RC == &MSP430::GR8RegClass) 35 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 64 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument 40 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 41 VRegInfo[Reg].first = RC; 51 const TargetRegisterClass *RC, 54 if (OldRC == RC) 55 return RC; 57 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 50 constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
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H A D | ExecutionDepsFix.cpp | 136 const TargetRegisterClass *const RC; 162 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 529 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr 735 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); 738 << TRI->getRegClassName(RC) << " **********\n"); 744 for (unsigned Reg : *RC) { 754 // Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and 757 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) 758 for (MCRegAliasIterator AI(RC 809 createExecutionDependencyFixPass(const TargetRegisterClass *RC) argument [all...] |
H A D | TargetInstrInfo.cpp | 344 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, argument 349 Size = RC->getSize(); 367 assert(RC->getSize() >= (Offset + Size) && "bad subregister range"); 370 Offset = RC->getSize() - (Offset + Size); 419 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); local 422 return RC->contains(LiveOp.getReg()) ? RC : nullptr; 424 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) 425 return RC; 474 const TargetRegisterClass *RC local 547 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); local 674 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); local [all...] |
/external/llvm/lib/MC/ |
H A D | MCRegisterInfo.cpp | 19 const MCRegisterClass *RC) const { 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.h | 53 const TargetRegisterClass *RC, 60 const TargetRegisterClass *RC,
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H A D | MipsSEISelLowering.h | 28 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 32 const TargetRegisterClass *RC);
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/external/ltp/testcases/commands/cron/ |
H A D | cron_pos_tests.sh | 27 RC=$? 29 exit $RC
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/external/ltp/testcases/kernel/controllers/cpuctl/ |
H A D | run_cpuctl_test.sh | 51 RC=0; # return code from functions 292 RC=$?; # Return status of the task being waited 295 if [ $RC -ne 0 ] 297 echo "Task $i exited abnormaly with return value: $RC";
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaInstrInfo.cpp | 146 const TargetRegisterClass *RC, 155 if (RC == Alpha::F4RCRegisterClass) 159 else if (RC == Alpha::F8RCRegisterClass) 163 else if (RC == Alpha::GPRCRegisterClass) 175 const TargetRegisterClass *RC, 182 if (RC == Alpha::F4RCRegisterClass) 185 else if (RC == Alpha::F8RCRegisterClass) 188 else if (RC == Alpha::GPRCRegisterClass) 143 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 172 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXInstrInfo.h | 105 const TargetRegisterClass* RC, 110 const TargetRegisterClass *RC,
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 289 const TargetRegisterClass *RC, 295 if (RC == SP::IntRegsRegisterClass) 298 else if (RC == SP::FPRegsRegisterClass) 301 else if (RC == SP::DFPRegsRegisterClass) 311 const TargetRegisterClass *RC, 316 if (RC == SP::IntRegsRegisterClass) 318 else if (RC == SP::FPRegsRegisterClass) 320 else if (RC == SP::DFPRegsRegisterClass) 287 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 309 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/webrtc/webrtc/modules/audio_coding/codecs/isac/main/source/ |
H A D | entropy_coding.h | 166 /* Decode & dequantize RC */ 169 /* Quantize & code RC */ 198 void WebRtcIsac_Poly2Rc(double* a, int N, double* RC); 201 void WebRtcIsac_Rc2Poly(double* RC, int N, double* a);
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/external/llvm/include/llvm/IR/ |
H A D | IRBuilder.h | 781 if (Constant *RC = dyn_cast<Constant>(RHS)) 782 return Insert(Folder.CreateAdd(LC, RC, HasNUW, HasNSW), Name); 795 if (Constant *RC = dyn_cast<Constant>(RHS)) 796 return Insert(Folder.CreateFAdd(LC, RC), Name); 803 if (Constant *RC = dyn_cast<Constant>(RHS)) 804 return Insert(Folder.CreateSub(LC, RC, HasNUW, HasNSW), Name); 817 if (Constant *RC = dyn_cast<Constant>(RHS)) 818 return Insert(Folder.CreateFSub(LC, RC), Name); 825 if (Constant *RC = dyn_cast<Constant>(RHS)) 826 return Insert(Folder.CreateMul(LC, RC, HasNU [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/Support/ |
H A D | IRBuilder.h | 503 if (Constant *RC = dyn_cast<Constant>(RHS)) 504 return Insert(Folder.CreateAdd(LC, RC, HasNUW, HasNSW), Name); 516 if (Constant *RC = dyn_cast<Constant>(RHS)) 517 return Insert(Folder.CreateFAdd(LC, RC), Name); 523 if (Constant *RC = dyn_cast<Constant>(RHS)) 524 return Insert(Folder.CreateSub(LC, RC), Name); 536 if (Constant *RC = dyn_cast<Constant>(RHS)) 537 return Insert(Folder.CreateFSub(LC, RC), Name); 543 if (Constant *RC = dyn_cast<Constant>(RHS)) 544 return Insert(Folder.CreateMul(LC, RC), Nam [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86FastISel.cpp | 180 const TargetRegisterClass *RC = NULL; local 186 RC = X86::GR8RegisterClass; 190 RC = X86::GR16RegisterClass; 194 RC = X86::GR32RegisterClass; 199 RC = X86::GR64RegisterClass; 204 RC = X86::FR32RegisterClass; 207 RC = X86::RFP32RegisterClass; 213 RC = X86::FR64RegisterClass; 216 RC = X86::RFP64RegisterClass; 224 ResultReg = createResultReg(RC); 527 const TargetRegisterClass *RC = NULL; local 1128 const TargetRegisterClass *RC = NULL; local 1204 const TargetRegisterClass *RC = NULL; local 1976 const TargetRegisterClass *RC = NULL; local 2084 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); local 2098 const TargetRegisterClass *RC = NULL; local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 110 const TargetRegisterClass *RC); 112 const TargetRegisterClass *RC, 115 const TargetRegisterClass *RC, 119 const TargetRegisterClass *RC, 124 const TargetRegisterClass *RC, 128 const TargetRegisterClass *RC, 132 const TargetRegisterClass *RC, 137 const TargetRegisterClass *RC, 140 const TargetRegisterClass *RC, 279 const TargetRegisterClass* RC) { 278 FastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass* RC) argument 287 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 306 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 328 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 353 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 375 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument 397 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 422 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument 441 FastEmitInst_ii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm1, uint64_t Imm2) argument 672 TargetRegisterClass* RC = TLI.getRegClassFor(VT); local 857 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass : local 921 TargetRegisterClass *RC; local 1272 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass local 1398 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local [all...] |