1//===- PTXInstrInfo.h - PTX Instruction Information -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PTX implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef PTX_INSTR_INFO_H
15#define PTX_INSTR_INFO_H
16
17#include "PTXRegisterInfo.h"
18#include "llvm/Target/TargetInstrInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "PTXGenInstrInfo.inc"
22
23namespace llvm {
24class PTXTargetMachine;
25
26class MachineSDNode;
27class SDValue;
28class SelectionDAG;
29
30class PTXInstrInfo : public PTXGenInstrInfo {
31private:
32  const PTXRegisterInfo RI;
33  PTXTargetMachine &TM;
34
35public:
36  explicit PTXInstrInfo(PTXTargetMachine &_TM);
37
38  virtual const PTXRegisterInfo &getRegisterInfo() const { return RI; }
39
40  virtual void copyPhysReg(MachineBasicBlock &MBB,
41                           MachineBasicBlock::iterator I, DebugLoc DL,
42                           unsigned DstReg, unsigned SrcReg,
43                           bool KillSrc) const;
44
45  virtual bool copyRegToReg(MachineBasicBlock &MBB,
46                            MachineBasicBlock::iterator I,
47                            unsigned DstReg, unsigned SrcReg,
48                            const TargetRegisterClass *DstRC,
49                            const TargetRegisterClass *SrcRC,
50                            DebugLoc DL) const;
51
52  virtual bool isMoveInstr(const MachineInstr& MI,
53                           unsigned &SrcReg, unsigned &DstReg,
54                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
55
56  // predicate support
57
58  virtual bool isPredicated(const MachineInstr *MI) const;
59
60  virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
61
62  virtual
63  bool PredicateInstruction(MachineInstr *MI,
64                            const SmallVectorImpl<MachineOperand> &Pred) const;
65
66  virtual
67  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
68                         const SmallVectorImpl<MachineOperand> &Pred2) const;
69
70  virtual bool DefinesPredicate(MachineInstr *MI,
71                                std::vector<MachineOperand> &Pred) const;
72
73  // PTX is fully-predicable
74  virtual bool isPredicable(MachineInstr *MI) const { return true; }
75
76  // branch support
77
78  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
79                             MachineBasicBlock *&FBB,
80                             SmallVectorImpl<MachineOperand> &Cond,
81                             bool AllowModify = false) const;
82
83  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
84
85  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
86                                MachineBasicBlock *FBB,
87                                const SmallVectorImpl<MachineOperand> &Cond,
88                                DebugLoc DL) const;
89
90  // Memory operand folding for spills
91  // TODO: Implement this eventually and get rid of storeRegToStackSlot and
92  //       loadRegFromStackSlot.  Doing so will get rid of the "stack" registers
93  //       we currently use to spill, though I doubt the overall effect on ptxas
94  //       output will be large.  I have yet to see a case where ptxas is unable
95  //       to see through the "stack" register usage and hence generates
96  //       efficient code anyway.
97  // virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
98  //                                             MachineInstr* MI,
99  //                                       const SmallVectorImpl<unsigned> &Ops,
100  //                                             int FrameIndex) const;
101
102  virtual void storeRegToStackSlot(MachineBasicBlock& MBB,
103                                   MachineBasicBlock::iterator MII,
104                                   unsigned SrcReg, bool isKill, int FrameIndex,
105                                   const TargetRegisterClass* RC,
106                                   const TargetRegisterInfo* TRI) const;
107  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
108                                    MachineBasicBlock::iterator MII,
109                                    unsigned DestReg, int FrameIdx,
110                                    const TargetRegisterClass *RC,
111                                    const TargetRegisterInfo *TRI) const;
112
113  // static helper routines
114
115  static MachineSDNode *GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
116                                          DebugLoc dl, EVT VT,
117                                          SDValue Op1);
118
119  static MachineSDNode *GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
120                                          DebugLoc dl, EVT VT,
121                                          SDValue Op1, SDValue Op2);
122
123  static void AddDefaultPredicate(MachineInstr *MI);
124
125  static bool IsAnyKindOfBranch(const MachineInstr& inst);
126
127  static bool IsAnySuccessorAlsoLayoutSuccessor(const MachineBasicBlock& MBB);
128
129  static MachineBasicBlock *GetBranchTarget(const MachineInstr& inst);
130}; // class PTXInstrInfo
131} // namespace llvm
132
133#endif // PTX_INSTR_INFO_H
134