/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonInstPrinter.cpp | 93 MCOperand const &MO = MI->getOperand(OpNo); local 94 if (MO.isReg()) { 95 O << getRegisterName(MO.getReg()); 96 } else if (MO.isExpr()) { 98 if (MO.getExpr()->evaluateAsAbsolute(Value)) 101 O << *MO.getExpr(); 215 MCOperand const &MO = MI->getOperand(OpNo); local 216 assert (MO.isExpr()); 217 MCExpr const &Expr = *MO.getExpr();
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H A D | HexagonMCCodeEmitter.h | 36 unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO, 63 unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUCodeEmitter.h | 23 const MachineOperand &MO) const { return 0; }
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 219 const MachineOperand &MO = Def->getOperand(i); local 220 if (!MO.isReg() || MO.isUndef() || MO.isUse()) 222 unsigned Reg = MO.getReg(); 229 const MachineOperand &MO = Use->getOperand(i); local 230 if (!MO.isReg() || MO.isUndef() || MO.isDef()) 232 unsigned Reg = MO 292 const MachineOperand &MO = MI->getOperand(i); local 689 const MachineOperand &MO = MI->getOperand(i); local 760 const MachineOperand &MO = MI->getOperand(i); local 783 const MachineOperand &MO = MI.getOperand(i); local 799 const MachineOperand &MO = MI.getOperand(i); local [all...] |
H A D | ARMCodeEmitter.cpp | 100 const MachineOperand &MO, 151 const MachineOperand &MO) const; 249 const MachineOperand &MO = MI.getOperand(Op); local 251 if (!MO.isReg()) { 252 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 255 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 291 const MachineOperand &MO = MI.getOperand(Op); local 293 if (!MO.isReg()) { 294 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 297 unsigned Reg = getARMRegisterNumbering(MO 414 getMovi32Value(const MachineInstr &MI, const MachineOperand &MO, unsigned Reloc) argument 919 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument 992 const MachineOperand &MO = MI.getOperand(i-1); local 1078 const MachineOperand &MO = MI.getOperand(OpIdx); local 1290 const MachineOperand &MO = MI.getOperand(i); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
H A D | MBlazeMCCodeEmitter.cpp | 50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; 55 static unsigned GetMBlazeRegNum(const MCOperand &MO) { argument 109 const MCOperand &MO) const { 110 if (MO.isReg()) 111 return getMBlazeRegisterNumbering(MO.getReg()); 112 else if (MO.isImm()) 113 return static_cast<unsigned>(MO.getImm()); 114 else if (MO.isExpr()) 118 errs() << MO;
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/external/llvm/lib/CodeGen/ |
H A D | MachineSink.cpp | 224 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { 225 MachineInstr *UseInst = MO.getParent(); 226 unsigned OpNo = &MO - &UseInst->getOperand(0); 237 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { 239 MachineInstr *UseInst = MO.getParent(); 240 unsigned OpNo = &MO - &UseInst->getOperand(0); 376 const MachineOperand &MO = MI.getOperand(i); local 377 if (!MO.isReg() || !MO.isUse()) 379 unsigned Reg = MO 596 const MachineOperand &MO = MI.getOperand(i); local 760 const MachineOperand &MO = MI.getOperand(I); local [all...] |
H A D | CriticalAntiDepBreaker.cpp | 172 MachineOperand &MO = MI.getOperand(i); local 173 if (!MO.isReg()) continue; 174 unsigned Reg = MO.getReg(); 202 RegRefs.insert(std::make_pair(Reg, &MO)); 226 if (MO.isUse() && Special) { 246 MachineOperand &MO = MI.getOperand(i); local 248 if (MO.isRegMask()) 250 if (MO.clobbersPhysReg(i)) { 258 if (!MO.isReg()) continue; 259 unsigned Reg = MO 288 MachineOperand &MO = MI.getOperand(i); local 599 MachineOperand &MO = MI.getOperand(i); local [all...] |
H A D | LiveVariables.cpp | 215 MachineOperand &MO = LastDef->getOperand(i); local 216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 218 unsigned DefReg = MO.getReg(); 376 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg); local 377 if (MO) { 379 assert(!MO->isDead()); 403 MachineOperand *MO = local 405 bool NeedEC = MO 422 HandleRegMask(const MachineOperand &MO) argument 516 MachineOperand &MO = MI.getOperand(i); local 693 MachineOperand &MO = MI.getOperand(i); local [all...] |
H A D | PatchableFunction.cpp | 77 for (auto &MO : FirstActualI->operands()) 78 MIB.addOperand(MO);
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H A D | XRayInstrumentation.cpp | 79 for (auto &MO : T.operands()) 80 MIB.addOperand(MO);
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H A D | AggressiveAntiDepBreaker.cpp | 218 MachineOperand &MO) { 219 if (!MO.isReg() || !MO.isImplicit()) 222 unsigned Reg = MO.getReg(); 227 if (MO.isDef()) 238 MachineOperand &MO = MI.getOperand(i); 239 if (!MO.isReg()) continue; 240 if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) || 241 IsImplicitDefUse(MI, MO)) { 242 const unsigned Reg = MO [all...] |
/external/llvm/include/llvm/MC/MCParser/ |
H A D | MCParsedAsmOperand.h | 91 inline raw_ostream& operator<<(raw_ostream &OS, const MCParsedAsmOperand &MO) { argument 92 MO.print(OS);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 89 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) { argument 90 MCOp = MCInstLowering.LowerOperand(MO); 442 const MachineOperand &MO = MI->getOperand(OpNum); local 448 if ((MO.getType()) != MachineOperand::MO_Immediate) 450 O << "0x" << Twine::utohexstr(MO.getImm()); 453 if ((MO.getType()) != MachineOperand::MO_Immediate) 455 O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff); 458 if ((MO.getType()) != MachineOperand::MO_Immediate) 460 O << MO.getImm(); 463 if ((MO 514 const MachineOperand &MO = MI->getOperand(RegOp); local 562 const MachineOperand &MO = MI->getOperand(opNum); local 659 const MachineOperand &MO = MI->getOperand(opNum); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCTOCRegDeps.cpp | 106 for (const MachineOperand &MO : MI.operands()) { 107 if ((MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) == PPCII::MO_TOC_LO)
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 61 void getFullAddress(SmallVectorImpl<MachineOperand> &MO) { argument 65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, 69 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex)); 72 MO.push_back(MachineOperand::CreateImm(Scale)); 73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, 77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); 79 MO.push_back(MachineOperand::CreateImm(Disp)); 81 MO.push_back(MachineOperand::CreateReg(0, false, false,
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/external/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 255 const MachineOperand &MO = candidate->getOperand(i); local 256 if (!MO.isReg()) 259 unsigned Reg = MO.getReg(); 261 if (MO.isDef()) { 266 if (MO.isUse()) { 326 const MachineOperand &MO = MI->getOperand(i); local 327 if (!MO.isReg()) 330 unsigned Reg = MO.getReg(); 333 if (MO.isDef()) 335 if (MO 370 const MachineOperand &MO = I->getOperand(structSizeOpNum); local [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | ScheduleDAGInstrs.h | 78 const MachineOperand &MO = MI->getOperand(i); local 79 if (!MO.isReg() || !MO.isUse()) 81 unsigned MOReg = MO.getReg(); 83 Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
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H A D | AggressiveAntiDepBreaker.cpp | 241 MachineOperand& MO) 243 if (!MO.isReg() || !MO.isImplicit()) 246 unsigned Reg = MO.getReg(); 251 if (MO.isDef()) 262 MachineOperand &MO = MI->getOperand(i); 263 if (!MO.isReg()) continue; 264 if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) || 265 IsImplicitDefUse(MI, MO)) { 266 const unsigned Reg = MO [all...] |
H A D | PeepholeOptimizer.cpp | 277 const MachineOperand &MO = MI->getOperand(i); local 278 if (!MO.isReg()) 280 unsigned Reg = MO.getReg(); 283 if (MO.isDef()) 304 const MachineOperand &MO = DefMI->getOperand(i); local 305 if (!MO.isReg() || MO.isDef()) 307 unsigned Reg = MO.getReg(); 310 if (!MO.isDef()) { 377 MachineOperand &MO local [all...] |
/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 51 // MO in MI. Fixups is the list of fixups against MI. 52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 137 getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument 140 if (MO.isReg()) 141 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 142 if (MO.isImm()) 143 return static_cast<uint64_t>(MO.getImm()); 217 const MCOperand &MO = MI.getOperand(OpNum); local 219 if (MO.isImm()) 220 Expr = MCConstantExpr::create(MO [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
H A D | XCoreAsmPrinter.cpp | 225 const MachineOperand &MO = MI->getOperand(opNum); local 226 switch (MO.getType()) { 228 O << getRegisterName(MO.getReg()); 231 O << MO.getImm(); 234 O << *MO.getMBB()->getSymbol(); 237 O << *Mang->getSymbol(MO.getGlobal()); 240 O << MO.getSymbolName(); 244 << '_' << MO.getIndex(); 248 << '_' << MO.getIndex(); 251 O << *GetBlockAddressSymbol(MO [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 100 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC); 135 bool A15SDOptimizer::usesRegClass(MachineOperand &MO, argument 137 if (!MO.isReg()) 139 unsigned Reg = MO.getReg(); 162 MachineOperand *MO = MI->findRegisterDefOperand(SReg); 164 assert(MO->isReg() && "Non-register operand found!"); 165 if (!MO) return ARM::ssub_0; 173 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1; 195 MachineOperand &MO = MI->getOperand(i); local 196 if ((!MO 411 MachineOperand &MO = MI->getOperand(i); local [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyCFGStackify.cpp | 291 for (MachineOperand &MO : MI.explicit_operands()) 292 if (MO.isMBB() && MO.getMBB() == MBB) 302 const MachineOperand &MO = MI.getOperand(0); local 303 if (!MO.isReg() || MO.isImplicit() || !MO.isDef()) 305 unsigned Reg = MO.getReg(); 503 for (auto MO : Ops) { 504 if (MO [all...] |