/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | ScheduleDAG.h | 61 /// Reg - For Data, Anti, and Output dependencies, the associated 64 unsigned Reg; member in union:llvm::SDep::__anon18343 95 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 102 assert(Reg != 0 && 103 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 108 Contents.Reg = Reg; 111 assert(Reg == 0 && "Reg given for non-register dependence!"); 125 return Contents.Reg 213 setReg(unsigned Reg) argument [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineScheduler.cpp | 288 static bool isDefBetween(unsigned Reg, argument 293 UI = MRI->def_instr_begin(Reg), 336 // 1) Reg is not input to any instruction in the block, but is output of one 339 // 4) Reg is input of an instruction but another block will read it too 340 // 5) Reg is input of an instruction and then rewritten in the block. 342 // 6) Reg is input of an instruction and then rewritten in the block. 344 // 7) Reg is input of an instruction and then rewritten in the block. 358 unsigned Reg = RegMaskPair.RegUnit; local 359 if (TargetRegisterInfo::isVirtualRegister(Reg) && 360 isDefBetween(Reg, LI 1767 unsigned Reg = *RegI; local [all...] |
H A D | SIFixSGPRCopies.cpp | 275 unsigned Reg = MI.getOperand(0).getReg(); local 276 if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) 318 unsigned Reg = MI.getOperand(i).getReg(); local 319 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) { 323 MachineInstr *DefInstr = MRI.getUniqueVRegDef(Reg);
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H A D | SILowerControlFlow.cpp | 251 unsigned Reg = MI.getOperand(0).getReg(); local 254 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) 257 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) 259 .addReg(Reg); 266 .addReg(Reg); 366 unsigned Reg = MI.getOperand(0).getReg(); local 371 .addReg(Reg); 430 for (unsigned Reg : RemainderLiveRegs) { 431 if (MRI.isAllocatable(Reg)) 432 RemainderBB.addLiveIn(Reg); 623 unsigned Reg = RC->getRegister(RegIdx); local 635 unsigned Reg; local 663 unsigned Reg; local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 121 unsigned Reg = MO.getReg(); local 122 if (!Reg) 124 for (const unsigned *AsI = TRI.getOverlaps(Reg); *AsI; ++AsI) 158 unsigned Reg = isSub 161 if (Reg) { 166 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); 276 unsigned Reg = II->first; 278 if (Reg == X86::EAX || Reg == X86::AX || 279 Reg [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | ScheduleDAGInstrs.cpp | 167 unsigned Reg = MO.getReg(); local 168 if (Reg == 0) continue; 170 assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!"); 171 Uses[Reg].push_back(&ExitSU); 181 unsigned Reg = *I; local 182 if (Seen.insert(Reg)) 183 Uses[Reg].push_back(&ExitSU); 259 unsigned Reg = MO.getReg(); local 260 if (Reg == 0) continue; 262 assert(TRI->isPhysicalRegister(Reg) 595 const unsigned Reg = dep.getReg(); local [all...] |
H A D | VirtRegMap.h | 489 void setRegisterUsed(unsigned Reg) { argument 490 UnusedRegs.reset(Reg); 495 bool isRegisterUnused(unsigned Reg) const { 496 return UnusedRegs[Reg]; 502 int Reg = UnusedRegs.find_first(); local 503 while (Reg != -1) { 504 if (allocatableRCRegs[RC][Reg]) 505 return (unsigned)Reg; 506 Reg = UnusedRegs.find_next(Reg); [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 168 } Reg; member in union:llvm::MachineOperand::__anon12242 345 void setReg(unsigned Reg); 354 /// subregister Reg:SubReg. Take any existing SubReg index into account, 356 /// Reg must be a virtual register, SubIdx can be 0. 358 void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&); 361 /// Reg, taking any existing SubReg into account. For instance, 364 void substPhysReg(unsigned Reg, const TargetRegisterInfo&); 580 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 606 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, 625 Op.SmallContents.RegNo = Reg; [all...] |
H A D | RegisterPressure.h | 261 unsigned getSparseIndexFromReg(unsigned Reg) const { 262 if (TargetRegisterInfo::isVirtualRegister(Reg)) 263 return TargetRegisterInfo::virtReg2Index(Reg) + NumRegUnits; 264 assert(Reg < NumRegUnits); 265 return Reg; 277 LaneBitmask contains(unsigned Reg) const { 278 unsigned SparseIndex = getSparseIndexFromReg(Reg); 285 /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live. 286 /// Returns the previously live lanes of \p Pair.Reg. 298 /// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mar [all...] |
/external/llvm/lib/CodeGen/ |
H A D | ImplicitNullChecks.cpp | 234 unsigned Reg = RegDef.first; local 236 if (!TRI.regsOverlap(Reg, MO.getReg())) 256 // MI is the only instruction that defines Reg, but we need to be sure 283 for (unsigned Reg : RegUses) 284 if (TRI.regsOverlap(Reg, MO.getReg())) 309 // Return true if any register aliasing \p Reg is live-in into \p MBB. 311 MachineBasicBlock *MBB, unsigned Reg) { 312 for (MCRegAliasIterator AR(Reg, TRI, /*IncludeSelf*/ true); AR.isValid(); 544 unsigned Reg = MO.getReg(); local 545 if (!Reg || MB 310 AnyAliasLiveIn(const TargetRegisterInfo *TRI, MachineBasicBlock *MBB, unsigned Reg) argument [all...] |
H A D | TailDuplicator.cpp | 253 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB, argument 255 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { 346 unsigned Reg = MO.getReg(); local 347 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 350 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 353 LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0))); 354 if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg)) 355 addSSAUpdateEntry(Reg, NewReg, PredBB); 357 auto VI = LocalVRMap.find(Reg); 444 unsigned Reg = MO0.getReg(); local [all...] |
H A D | RegAllocGreedy.cpp | 225 unsigned Reg = *Begin; local 226 if (ExtraRegInfo[Reg].Stage == RS_New) 227 ExtraRegInfo[Reg].Stage = NewStage; 275 void reset(InterferenceCache &Cache, unsigned Reg) { argument 276 PhysReg = Reg; 278 Intf.setPhysReg(Cache, Reg); 408 unsigned Reg; member in struct:__anon12608::RAGreedy::HintInfo 410 /// In case of a physical register Reg == PhysReg. 412 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg) argument 413 : Freq(Freq), Reg(Re 542 const unsigned Reg = LI->reg; local 1224 unsigned Reg = SA->getParent().reg; local 1320 LiveInterval &Reg = LIS->getInterval(LREdit.get(i)); local 1516 unsigned Reg = VirtReg.reg; local 1559 getNumAllocatableRegsForConstraints( const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI) argument [all...] |
H A D | MachineBasicBlock.cpp | 325 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) { argument 328 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; }); 337 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const { argument 340 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; }); 756 unsigned Reg = OI->getReg(); local 757 if (TargetRegisterInfo::isPhysicalRegister(Reg) || 758 LV->getVarInfo(Reg).removeKill(*MI)) { 759 KilledRegs.push_back(Reg); 777 unsigned Reg = OI->getReg(); local 846 unsigned Reg = KilledRegs.pop_back_val(); local 883 unsigned Reg = MO.getReg(); local 899 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local [all...] |
H A D | ShrinkWrap.cpp | 145 for (int Reg = SavedRegs.find_first(); Reg != -1; 146 Reg = SavedRegs.find_next(Reg)) 147 CurrentCSRs.insert((unsigned)Reg); 241 for (unsigned Reg : getCurrentCSRs(RS)) { 242 if (MO.clobbersPhysReg(Reg)) {
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenMux.cpp | 86 bool isRegPair(unsigned Reg) const { 87 return Hexagon::DoubleRegsRegClass.contains(Reg); 89 void getSubRegs(unsigned Reg, BitVector &SRs) const; 90 void expandReg(unsigned Reg, BitVector &Set) const; 108 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { argument 109 for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I) 114 void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const { argument 115 if (isRegPair(Reg)) 116 getSubRegs(Reg, Set); 118 Set[Reg] [all...] |
H A D | HexagonBlockRanges.h | 36 unsigned Reg, Sub; member in struct:llvm::HexagonBlockRanges::RegisterRef 38 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 152 unsigned Reg = lookUpRegForValue(V); local 153 if (Reg && !MRI.use_empty(Reg)) 189 unsigned Reg = lookUpRegForValue(V); local 190 if (Reg) 191 return Reg; 204 Reg = materializeRegForValue(V, VT); 208 return Reg; 212 unsigned Reg = 0; local 215 Reg 268 unsigned Reg = 0; local 298 updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) argument 593 unsigned Reg = getRegForValue(Val); local 804 unsigned Reg = getRegForValue(I->getArgOperand(i)); local 1281 unsigned Reg = getRegForValue(I->getOperand(0)); local 1659 unsigned Reg = getRegForValue(I->getOperand(0)); local 2074 unsigned Reg = getRegForValue(PHIOp); local [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 115 bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; } argument 149 void AddBusyReg(unsigned Reg) { argument 150 if (Reg != X86::NoRegister) 151 BusyRegs.push_back(convReg(Reg, 64)); 163 for (unsigned Reg : Candidates) { 164 if (!std::count(BusyRegs.begin(), BusyRegs.end(), Reg)) 165 return convReg(Reg, Size); 171 unsigned convReg(unsigned Reg, unsigne argument 236 EmitLEA(X86Operand &Op, unsigned Size, unsigned Reg, MCStreamer &Out) argument 431 ComputeMemOperandAddress(X86Operand &Op, unsigned Size, unsigned Reg, MCContext &Ctx, MCStreamer &Out) argument 510 SpillReg(MCStreamer &Out, unsigned Reg) argument 515 RestoreReg(MCStreamer &Out, unsigned Reg) argument 768 SpillReg(MCStreamer &Out, unsigned Reg) argument 773 RestoreReg(MCStreamer &Out, unsigned Reg) argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXSwapRemoval.cpp | 164 bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) { argument 165 if (TargetRegisterInfo::isVirtualRegister(Reg)) 166 return RC->hasSubClassEq(MRI->getRegClass(Reg)); 167 return RC->contains(Reg); 171 bool isVecReg(unsigned Reg) { argument 172 return (isRegInClass(Reg, &PPC::VSRCRegClass) || 173 isRegInClass(Reg, &PPC::VRRCRegClass)); 177 bool isScalarVecReg(unsigned Reg) { argument 178 return (isRegInClass(Reg, &PPC::VSFRCRegClass) || 179 isRegInClass(Reg, 185 isAnyVecReg(unsigned Reg, bool &Partial) argument 258 unsigned Reg = MO.getReg(); local 601 unsigned Reg = MO.getReg(); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 43 SDValue Reg; member in struct:__anon18824::SystemZRRIAddressMode::__anon18826 58 errs() << "Base.Reg "; 59 if (Base.Reg.getNode() != 0) 60 Base.Reg.getNode()->dump(); 210 AM.Base.Reg.getNode() == 0) { 240 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) { 281 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) { 282 AM.Base.Reg = N.getNode()->getOperand(0); 320 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 521 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) 522 Mask[Reg / 32] &= ~(1U << (Reg % 32)); 568 unsigned Reg, int &FrameIdx) const { 671 unsigned llvm::get512BitSuperRegister(unsigned Reg) { argument 672 if (Reg >= X86::XMM0 && Reg <= X86::XMM31) 673 return X86::ZMM0 + (Reg - X86::XMM0); 674 if (Reg >= X86::YMM0 && Reg < 567 hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 218 unsigned Reg = Info.getReg(); local 221 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 264 for (unsigned Reg : AArch64::GPR64RegClass) { 265 if (LiveRegs.available(MRI, Reg)) 266 return Reg; 623 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true); local 625 MCCFIInstruction::createDefCfa(nullptr, Reg, 2 * StackGrowth)); 854 static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) { argument 860 bool IsLiveIn = MF.getRegInfo().isLiveIn(Reg); 1108 const unsigned Reg local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 488 unsigned Reg = CSI[I].getReg(); local 489 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 493 if (PPC::CRBITRCRegisterClass->contains(Reg)) 497 MachineLocation CSSrc(Reg); 816 unsigned Reg = CSI[i].getReg(); local 817 if (PPC::GPRCRegisterClass->contains(Reg)) { 822 if (Reg < MinGPR) { 823 MinGPR = Reg; 929 unsigned Reg = CSI[i].getReg(); local 947 unsigned Reg = CSI[i].getReg(); local [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 43 SDValue Reg; member in struct:__anon13053::MSP430ISelAddressMode::__anon13055 66 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) { 67 errs() << "Base.Reg "; 68 Base.Reg.getNode()->dump(); 168 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) { 175 AM.Base.Reg = N; 197 && AM.Base.Reg.getNode() == nullptr) { 252 if (!AM.Base.Reg.getNode()) 253 AM.Base.Reg = CurDAG->getRegister(0, VT); 260 : AM.Base.Reg; [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 42 SDValue Reg; member in struct:__anon18784::MSP430ISelAddressMode::__anon18786 65 if (BaseType == RegBase && Base.Reg.getNode() != 0) { 66 errs() << "Base.Reg "; 67 Base.Reg.getNode()->dump(); 173 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) { 180 AM.Base.Reg = N; 202 && AM.Base.Reg.getNode() == 0) { 257 if (!AM.Base.Reg.getNode()) 258 AM.Base.Reg = CurDAG->getRegister(0, VT); 263 AM.Base.Reg; [all...] |