Searched defs:src (Results 226 - 250 of 2580) sorted by last modified time

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/external/vixl/src/aarch32/
H A Doperands-aarch32.h277 NeonImmediate(const NeonImmediate& src) argument
278 : imm_(src.imm_), immediate_type_(src.immediate_type_) {}
/external/vixl/src/aarch64/
H A Dassembler-aarch64.cc948 const MemOperand& src) {
949 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2));
962 const MemOperand& src) {
964 LoadStorePair(xt, xt2, src, LDPSW_x);
999 const MemOperand& src) {
1000 LoadStorePairNonTemporal(rt, rt2, src, LoadPairNonTemporalOpFor(rt, rt2));
1030 const MemOperand& src,
1034 LoadStore(rt, src, LDRB_w, option);
1048 const MemOperand& src,
1052 LoadStore(rt, src, r
946 ldp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& src) argument
960 ldpsw(const Register& xt, const Register& xt2, const MemOperand& src) argument
997 ldnp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& src) argument
1029 ldrb(const Register& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1047 ldrsb(const Register& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1056 ldrh(const Register& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1074 ldrsh(const Register& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1083 ldr(const CPURegister& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1101 ldrsw(const Register& xt, const MemOperand& src, LoadStoreScalingOption option) argument
1111 ldurb(const Register& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1129 ldursb(const Register& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1138 ldurh(const Register& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1156 ldursh(const Register& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1165 ldur(const CPURegister& rt, const MemOperand& src, LoadStoreScalingOption option) argument
1183 ldursw(const Register& xt, const MemOperand& src, LoadStoreScalingOption option) argument
1248 ldxrb(const Register& rt, const MemOperand& src) argument
1254 ldxrh(const Register& rt, const MemOperand& src) argument
1260 ldxr(const Register& rt, const MemOperand& src) argument
1278 ldxp(const Register& rt, const Register& rt2, const MemOperand& src) argument
1313 ldaxrb(const Register& rt, const MemOperand& src) argument
1319 ldaxrh(const Register& rt, const MemOperand& src) argument
1325 ldaxr(const Register& rt, const MemOperand& src) argument
1343 ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) argument
1372 ldarb(const Register& rt, const MemOperand& src) argument
1378 ldarh(const Register& rt, const MemOperand& src) argument
1384 ldar(const Register& rt, const MemOperand& src) argument
1549 ld1(const VRegister& vt, const MemOperand& src) argument
1554 ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) argument
1564 ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) argument
1575 ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) argument
1587 ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) argument
1597 ld2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& src) argument
1608 ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src) argument
1618 ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) argument
1629 ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) argument
1641 ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) argument
1652 ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) argument
1664 ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) argument
1677 ld4r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) argument
1689 st1(const VRegister& vt, const MemOperand& src) argument
1694 st1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) argument
1704 st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) argument
1715 st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) argument
[all...]
H A Dinstructions-aarch64.h485 static Instruction* Cast(T src) { argument
486 return reinterpret_cast<Instruction*>(src);
490 static const Instruction* CastConst(T src) { argument
491 return reinterpret_cast<const Instruction*>(src);
H A Dlogic-aarch64.cc86 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { argument
87 if (src >= 0) {
88 return UFixedToDouble(src, fbits, round);
89 } else if (src == INT64_MIN) {
90 return -UFixedToDouble(src, fbits, round);
92 return -UFixedToDouble(-src, fbits, round);
97 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { argument
100 if (src == 0) {
106 const int highest_significant_bit = 63 - CountLeadingZeros(src);
109 return FPRoundToDouble(0, exponent, src, roun
113 FixedToFloat(int64_t src, int fbits, FPRounding round) argument
124 UFixedToFloat(uint64_t src, int fbits, FPRounding round) argument
598 st1(VectorFormat vform, LogicVRegister src, uint64_t addr) argument
606 st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr) argument
1277 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, uint64_t imm) argument
1386 const LogicVRegister* src = &src1; local
1423 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1435 addv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1453 saddlv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1470 uaddlv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1487 sminmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool max) argument
1506 smaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1514 sminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1566 const LogicVRegister* src = &src1; local
1603 uminmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool max) argument
1622 umaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1630 uminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1638 shl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1649 sshll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1661 sshll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1673 shll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1681 shll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1689 ushll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1701 ushll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1713 sli(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1730 sqshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1741 uqshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1752 sqshlu(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1763 sri(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1789 ushr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1800 sshr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1811 ssra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1821 usra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1831 srsra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1841 ursra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1851 cls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1869 clz(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1887 cnt(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2009 neg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2025 suqadd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2046 usqadd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2067 abs(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2087 extractnarrow(VectorFormat dstform, LogicVRegister dst, bool dstIsSigned, const LogicVRegister& src, bool srcIsSigned) argument
2189 xtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2196 sqxtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2203 sqxtun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2210 uqxtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2262 not_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2273 rbit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2299 rev(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int revSize) argument
2320 rev16(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2327 rev32(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2334 rev64(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2341 addlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool is_signed, bool do_accumulate) argument
2373 saddlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2380 uaddlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2387 sadalp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2394 uadalp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2422 dup_element(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int src_index) argument
2449 ins_element(VectorFormat vform, LogicVRegister dst, int dst_index, const LogicVRegister& src, int src_index) argument
2493 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, uint64_t imm) argument
2510 uxtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2523 sxtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2536 uxtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2550 sxtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2564 shrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2576 shrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2588 rshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2600 rshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2715 uqshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2723 uqshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2731 uqrshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2739 uqrshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2747 sqshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2759 sqshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2771 sqrshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2783 sqrshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2795 sqshrun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2807 sqshrun2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2819 sqrshrun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2831 sqrshrun2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
4092 fcmp_zero(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, Condition cond) argument
4192 fneg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4205 fneg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4219 fabs_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4234 fabs_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4258 fsqrt(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4308 fminmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPMinMaxOp Op) argument
4323 fmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4330 fminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4337 fmaxnmv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4344 fminnmv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4431 frint(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, bool inexact_exception) argument
4461 fcvts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, int fbits) argument
4483 fcvtu(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, int fbits) argument
4505 fcvtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4522 fcvtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4540 fcvtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4557 fcvtn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4575 fcvtxn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4587 fcvtxn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4682 frsqrte(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4803 frecpe(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding round) argument
4824 ursqrte(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4857 urecpe(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4879 frecpx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4909 frecpx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4921 scvtf(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int fbits, FPRounding round) argument
4940 ucvtf(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int fbits, FPRounding round) argument
[all...]
H A Dmacro-assembler-aarch64.cc1558 const GenericOperand& src) {
1559 if (dst.Equals(src)) {
1563 VIXL_ASSERT(dst.IsValid() && src.IsValid());
1566 VIXL_ASSERT(dst.GetSizeInBits() == src.GetSizeInBits());
1570 if (dst.IsCPURegister() && src.IsCPURegister()) {
1572 CPURegister src_reg = src.GetCPURegister();
1587 if (dst.IsMemOperand() && src.IsMemOperand()) {
1590 Ldr(temp, src.GetMemOperand());
1596 Ldr(dst.GetCPURegister(), src.GetMemOperand());
1598 Str(src
1557 Move(const GenericOperand& dst, const GenericOperand& src) argument
1986 PushMultipleTimes(int count, Register src) argument
2124 Poke(const Register& src, const Operand& offset) argument
2233 LoadCPURegList(CPURegList registers, const MemOperand& src) argument
[all...]
H A Dmacro-assembler-aarch64.h685 void Move(const GenericOperand& dst, const GenericOperand& src);
828 void PushMultipleTimes(int count, Register src);
830 // Poke 'src' onto the stack. The offset is in bytes.
834 void Poke(const Register& src, const Operand& offset);
928 void LoadCPURegList(CPURegList registers, const MemOperand& src);
1421 void Ldar(const Register& rt, const MemOperand& src) { argument
1424 ldar(rt, src);
1426 void Ldarb(const Register& rt, const MemOperand& src) { argument
1429 ldarb(rt, src);
1431 void Ldarh(const Register& rt, const MemOperand& src) { argument
1436 Ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) argument
1442 Ldaxr(const Register& rt, const MemOperand& src) argument
1447 Ldaxrb(const Register& rt, const MemOperand& src) argument
1452 Ldaxrh(const Register& rt, const MemOperand& src) argument
1457 Ldnp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& src) argument
1545 Ldxp(const Register& rt, const Register& rt2, const MemOperand& src) argument
1551 Ldxr(const Register& rt, const MemOperand& src) argument
1556 Ldxrb(const Register& rt, const MemOperand& src) argument
1561 Ldxrh(const Register& rt, const MemOperand& src) argument
2511 Ld1(const VRegister& vt, const MemOperand& src) argument
2516 Ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) argument
2521 Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) argument
2529 Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) argument
2538 Ld1(const VRegister& vt, int lane, const MemOperand& src) argument
2543 Ld1r(const VRegister& vt, const MemOperand& src) argument
2548 Ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) argument
2553 Ld2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& src) argument
2561 Ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src) argument
2566 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) argument
2574 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) argument
2583 Ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const MemOperand& src) argument
2591 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) argument
2600 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) argument
2610 Ld4r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, const MemOperand& src) argument
[all...]
H A Dsimulator-aarch64.cc1864 unsigned src = instr->GetRn(); local
1868 WriteWRegister(dst, ReverseBits(ReadWRegister(src)));
1871 WriteXRegister(dst, ReverseBits(ReadXRegister(src)));
1874 WriteWRegister(dst, ReverseBytes(ReadWRegister(src), 1));
1877 WriteXRegister(dst, ReverseBytes(ReadXRegister(src), 1));
1880 WriteWRegister(dst, ReverseBytes(ReadWRegister(src), 2));
1883 WriteXRegister(dst, ReverseBytes(ReadXRegister(src), 2));
1886 WriteXRegister(dst, ReverseBytes(ReadXRegister(src), 3));
1889 WriteWRegister(dst, CountLeadingZeros(ReadWRegister(src)));
1892 WriteXRegister(dst, CountLeadingZeros(ReadXRegister(src)));
2197 uint64_t src = ReadRegister(reg_size, instr->GetRn()); local
2244 unsigned src = instr->GetRn(); local
2434 unsigned src = instr->GetRn(); local
[all...]
/external/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc5061 const uint32_t src[4] = {0x12345678, 0x09abcdef, 0xc001c0de, 0xdeadbeef}; local
5065 __ Mov(r0, reinterpret_cast<uintptr_t>(src));
5110 const uint32_t src[4] = {0x12345678, 0x09abcdef, 0xc001c0de, 0xdeadbeef}; local
5120 __ Mov(r0, reinterpret_cast<uintptr_t>(src));
5134 ASSERT_EQUAL_32(reinterpret_cast<uintptr_t>(src + 4), r0);
5221 const uint32_t src[6] = local
5227 __ Mov(r11, reinterpret_cast<uintptr_t>(src + 6));
5241 ASSERT_EQUAL_32(reinterpret_cast<uintptr_t>(src + 2), r11);
/external/valgrind/helgrind/
H A Dhg_main.c1012 Addr src, Addr dst, SizeT len )
1016 libhb_copy_shadow_state( hbthr, src, dst, len );
1570 void evh__copy_mem ( Addr src, Addr dst, SizeT len ) { argument
1572 VG_(printf)("evh__copy_mem(%p, %p, %lu)\n", (void*)src, (void*)dst, len );
1575 shadow_mem_scopy_range( thr , src, dst, len );
3494 Addr dst_ga; /* src/dst of the edge */
3631 static void laog__add_edge ( Lock* src, Lock* dst ) { argument
3635 if (0) VG_(printf)("laog__add_edge %p %p\n", src, dst);
3638 presentF if there is already a src->dst mapping in this node's
3639 forwards links, and presentR if there is already a src
1011 shadow_mem_scopy_range( Thread* thr, Addr src, Addr dst, SizeT len ) argument
3714 laog__del_edge( Lock* src, Lock* dst ) argument
3833 laog__do_dfs_from_to( Lock* src, WordSetID dsts ) argument
[all...]
H A Dlibhb_core.c1407 Word nDst, CacheLine* src )
1415 UShort descr = src->descrs[tno];
1416 SVal* tree = &src->svals[cloff];
5649 static void zsm_scopy08 ( Addr src, Addr dst, Bool uu_normalise ) { argument
5652 sv = zsm_sread08( src );
5661 static void zsm_scopy_range ( Addr src, Addr dst, SizeT len ) argument
5668 tl_assert(src+len <= dst || dst+len <= src);
5679 zsm_scopy08( src+i, dst+i, normalise );
7044 void libhb_copy_shadow_state ( Thr* thr, Addr src, Add argument
[all...]
/external/valgrind/memcheck/
H A Dmc_errors.c166 Addr src; // Source block member in struct:_MC_Error::__anon23549::__anon23560
284 const HChar* src = NULL; local
288 case MC_OKIND_STACK: src = " by a stack allocation"; break;
289 case MC_OKIND_HEAP: src = " by a heap allocation"; break;
290 case MC_OKIND_USER: src = " by a client request"; break;
291 case MC_OKIND_UNKNOWN: src = ""; break;
293 tl_assert(src); /* guards against invalid 'okind' */
297 src);
300 emit( " Uninitialised value was created%s\n", src);
639 extra->Err.Overlap.dst, extra->Err.Overlap.src );
864 record_overlap_error( ThreadId tid, const HChar* function, Addr src, Addr dst, SizeT szB ) argument
[all...]
H A Dmc_main.c1894 void MC_(copy_address_range_state) ( Addr src, Addr dst, SizeT len ) argument
1903 if (len == 0 || src == dst)
1906 aligned = VG_IS_4_ALIGNED(src) && VG_IS_4_ALIGNED(dst);
1907 nooverlap = src+len <= dst || dst+len <= src;
1915 vabits8 = get_vabits8_for_aligned_word32( src+i );
1923 if (VA_BITS2_PARTDEFINED == get_vabits2( src+i+0 ))
1924 set_sec_vbits8( dst+i+0, get_sec_vbits8( src+i+0 ) );
1925 if (VA_BITS2_PARTDEFINED == get_vabits2( src+i+1 ))
1926 set_sec_vbits8( dst+i+1, get_sec_vbits8( src
6336 const HChar* src; local
6759 Addr src = (Addr) arg[3]; local
[all...]
H A Dmc_translate.c5287 IRAtom *src, *here, *curr; local
5357 src = assignNew('V', mce, tySrc,
5360 here = mkPCastTo( mce, Ity_I32, src );
/external/valgrind/memcheck/tests/amd64/
H A Dxsave-avx.c47 void* my_memcpy(void *dest, const void *src, size_t n) argument
51 ((unsigned char*)dest)[i] = ((unsigned char*)src)[i];
/external/valgrind/memcheck/tests/common/
H A Dsh-mem-vec128.tmpl.c239 // the src or dst to be aligned. Once every 64, force both to be
255 void* src = &buf[si]; local
257 if (0 == (((UWord)src) & (VECTOR_BYTES-1))) n_s_aligned++;
259 if (0 == (((UWord)src) & (VECTOR_BYTES-1)) && 0 == (((UWord)dst) & (VECTOR_BYTES-1)))
262 vector_copy(dst, src);
/external/valgrind/memcheck/tests/
H A Dcond_ld_st.c43 // Returns either |*src| or |alt|.
45 UInt do_conditional_load32 ( UInt* src, UInt alt, Bool b ) argument
53 "ldrne r5, [%1]" "\n\t" // src
56 : /*IN*/"r"(src), "r"(alt), "r"(b)
61 res = b ? *src : alt;
H A Doverlap.c116 and used 'n' for the length, even when the src was shorter than 'n' */
119 char src [16]; local
120 strcpy( src, "short" );
121 strncpy( dest, src, 20 );
H A Dsh-mem-random.c131 U4 ty, src, dst; local
134 src = (randomU4() >> 1) % N_BYTES;
138 *(U1*)(arr+dst) = *(U1*)(arr+src);
143 if (src+2 >= N_BYTES || dst+2 >= N_BYTES)
145 *(U2*)(arr+dst) = *(U2*)(arr+src);
150 if (src+4 >= N_BYTES || dst+4 >= N_BYTES)
152 *(U4*)(arr+dst) = *(U4*)(arr+src);
157 if (src+8 >= N_BYTES || dst+8 >= N_BYTES)
159 *(U8*)(arr+dst) = *(U8*)(arr+src);
167 if (src
[all...]
H A Dstr_tester.c178 { const void *src = "frobozz"; local
180 check (strcpy (dst, src) == dst, 1);
/external/valgrind/memcheck/tests/s390x/
H A Dcu21.c39 do_cu21(uint8_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len) argument
42 register uint16_t *source asm("4") = src;
H A Dcu42.c25 do_cu42(uint16_t *dst, uint64_t dst_len, uint32_t *src, uint64_t src_len) argument
28 register uint32_t *source asm("4") = src;
/external/valgrind/memcheck/tests/solaris/
H A Dstrlcpy.c11 char *src = malloc(100); local
12 if (src == NULL) {
16 strcpy(src, "Hey, dude!");
25 copied = strlcpy(dst, src, 10);
30 copied = strlcpy(dst, src, strlen(src) + 1);
34 /* This is just a fancy way how to write strlen(src).
36 copied = strlcpy(NULL, src, 0);
41 strlcpy(src + 9, src, strle
[all...]
/external/valgrind/none/tests/amd64/
H A DredundantRexW.c61 void xor_UWord128( UWord128* src, UWord128* dst ) { argument
64 dst->b[i] ^= src->b[i];
66 void xor_XMMRegs ( XMMRegs* src, XMMRegs* dst ) { argument
69 xor_UWord128( &src->reg[i], &dst->reg[i] );
72 void xor_Mem ( Mem* src, Mem* dst ) { argument
75 xor_UWord128( &src->dqw[i], &dst->dqw[i] );
H A Dsse4-64.c395 V128 src, dst; local
398 randV128(&src);
400 DO_imm_mandr_r("blendpd", 0, src, dst);
401 DO_imm_mandr_r("blendpd", 1, src, dst);
402 DO_imm_mandr_r("blendpd", 2, src, dst);
403 DO_imm_mandr_r("blendpd", 3, src, dst);
409 V128 src, dst; local
412 randV128(&src);
414 DO_imm_mandr_r("blendps", 0, src, dst);
415 DO_imm_mandr_r("blendps", 1, src, ds
435 V128 src, dst; local
702 V128 src, dst; local
973 V128 src, dst; local
1244 V128 src, dst; local
1262 V128 src, dst; local
1286 V128 src, dst; local
1552 V128 src, dst; local
1572 V128 src; local
1594 ULong src; local
1632 V128 src; local
1646 ULong src; local
1668 V128 src; local
1678 ULong src; local
1692 V128 src; local
1700 ULong src; local
1710 V128 src; local
1721 V128 src, dst; local
1735 V128 src, dst; local
1746 V128 src, dst; local
1757 V128 src, dst; local
1768 V128 src, dst; local
1779 V128 src, dst; local
1790 V128 src, dst; local
1801 V128 src, dst; local
1812 V128 src, dst; local
1823 V128 src, dst; local
1834 V128 src, dst; local
1845 V128 src, dst; local
1856 V128 src, dst; local
1867 V128 src, dst; local
1878 V128 src, dst; local
1889 V128 src, dst; local
1900 V128 src, dst; local
1911 V128 src, dst; local
1922 V128 src, dst; local
1933 V128 src, dst; local
1944 V128 src, dst; local
1955 V128 src, dst; local
1967 V128 src, dst; local
2156 V128 src, dst; local
2174 do_ROUNDSD_000( Bool mem, V128* src, V128* dst ) argument
2198 do_ROUNDSD_001( Bool mem, V128* src, V128* dst ) argument
2222 do_ROUNDSD_010( Bool mem, V128* src, V128* dst ) argument
2246 do_ROUNDSD_011( Bool mem, V128* src, V128* dst ) argument
2270 do_ROUNDSD_1XX( Bool mem, V128* src, V128* dst ) argument
2323 V128 src, dst; local
2451 V128 src, dst; local
2490 do_ROUNDSS_000( Bool mem, V128* src, V128* dst ) argument
2514 do_ROUNDSS_001( Bool mem, V128* src, V128* dst ) argument
2538 do_ROUNDSS_010( Bool mem, V128* src, V128* dst ) argument
2562 do_ROUNDSS_011( Bool mem, V128* src, V128* dst ) argument
2586 do_ROUNDSS_1XX( Bool mem, V128* src, V128* dst ) argument
2639 V128 src, dst; local
2767 V128 src, dst; local
2805 do_ROUNDPD_000( Bool mem, V128* src, V128* dst ) argument
2829 do_ROUNDPD_001( Bool mem, V128* src, V128* dst ) argument
2853 do_ROUNDPD_010( Bool mem, V128* src, V128* dst ) argument
2877 do_ROUNDPD_011( Bool mem, V128* src, V128* dst ) argument
2901 do_ROUNDPD_1XX( Bool mem, V128* src, V128* dst ) argument
2954 V128 src, dst; local
3098 V128 src, dst; local
3140 do_ROUNDPS_000( Bool mem, V128* src, V128* dst ) argument
3164 do_ROUNDPS_001( Bool mem, V128* src, V128* dst ) argument
3188 do_ROUNDPS_010( Bool mem, V128* src, V128* dst ) argument
3212 do_ROUNDPS_011( Bool mem, V128* src, V128* dst ) argument
3236 do_ROUNDPS_1XX( Bool mem, V128* src, V128* dst ) argument
3289 V128 src, dst; local
3465 V128 src, dst; local
3555 do_PBLENDVB( Bool mem, V128* xmm0, V128* src, V128* dst ) argument
3583 V128 xmm0, src, dst, t_xmm0, t_src, t_dst; local
3622 do_BLENDVPD( Bool mem, V128* xmm0, V128* src, V128* dst ) argument
3650 V128 xmm0, src, dst, t_xmm0, t_src, t_dst; local
3689 do_BLENDVPS( Bool mem, V128* xmm0, V128* src, V128* dst ) argument
3717 V128 xmm0, src, dst, t_xmm0, t_src, t_dst; local
3756 V128 src, dst; local
[all...]
/external/valgrind/none/tests/linux/
H A Dmremap2.c41 // | pre | src | FREE | post |
93 char* src = NULL; variable
100 if (p == src) return "src";
131 src = setup( tidythis, tidylen );
136 printf(" src = %p\n", src);
146 syscall(__NR_mremap, src, 20*PAGE, newsize, flags, dst, 0 );
160 if (r != src && r != try_dst && r != dst_impossible) {

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