Searched refs:AlignedAddr (Results 1 - 6 of 6) sorted by relevance
/external/clang/test/CodeGen/ |
H A D | arm-vector-align.c | 14 typedef float AlignedAddr __attribute__ ((aligned (16))); typedef 15 void t1(AlignedAddr *addr1, AlignedAddr *addr2) {
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/external/llvm/include/llvm/Support/ |
H A D | Allocator.h | 240 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); local 241 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); 242 char *AlignedPtr = (char*)AlignedAddr; 250 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); local 251 assert(AlignedAddr + Size <= (uintptr_t)End && 253 char *AlignedPtr = (char*)AlignedAddr;
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/external/llvm/lib/CodeGen/ |
H A D | AtomicExpandPass.cpp | 567 Value *AlignedAddr; member in struct:__anon12529::PartwordMaskValues 580 /// AlignedAddr: Addr rounded down to a multiple of WordSize 614 Ret.AlignedAddr = Builder.CreateIntToPtr( 616 "AlignedAddr"); 719 insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr, MemOpOrder, 746 // %NewCI = cmpxchg i32* %PMV.AlignedAddr, i32 %FullWord_Cmp, 796 LoadInst *InitLoaded = Builder.CreateLoad(PMV.WordType, PMV.AlignedAddr); 810 PMV.AlignedAddr, FullWord_Cmp, FullWord_NewVal, CI->getSuccessOrdering(),
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 963 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); local 1017 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1049 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1073 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1184 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); local 1245 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1268 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1285 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1245 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); local 1307 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1346 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1370 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1500 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); local 1570 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1601 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1618 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 3233 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, 3262 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, 3337 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, 3353 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
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