1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/CallingConv.h" 26#include "InstPrinter/MipsInstPrinter.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/CodeGen/ValueTypes.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36using namespace llvm; 37 38// If I is a shifted mask, set the size (Size) and the first bit of the 39// mask (Pos), and return true. 40// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 41static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 42 if (!isUInt<32>(I) || !isShiftedMask_32(I)) 43 return false; 44 45 Size = CountPopulation_32(I); 46 Pos = CountTrailingZeros_32(I); 47 return true; 48} 49 50const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 51 switch (Opcode) { 52 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 53 case MipsISD::Hi: return "MipsISD::Hi"; 54 case MipsISD::Lo: return "MipsISD::Lo"; 55 case MipsISD::GPRel: return "MipsISD::GPRel"; 56 case MipsISD::TlsGd: return "MipsISD::TlsGd"; 57 case MipsISD::TprelHi: return "MipsISD::TprelHi"; 58 case MipsISD::TprelLo: return "MipsISD::TprelLo"; 59 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 60 case MipsISD::Ret: return "MipsISD::Ret"; 61 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 62 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 63 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 64 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 65 case MipsISD::FPRound: return "MipsISD::FPRound"; 66 case MipsISD::MAdd: return "MipsISD::MAdd"; 67 case MipsISD::MAddu: return "MipsISD::MAddu"; 68 case MipsISD::MSub: return "MipsISD::MSub"; 69 case MipsISD::MSubu: return "MipsISD::MSubu"; 70 case MipsISD::DivRem: return "MipsISD::DivRem"; 71 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 72 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 73 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 74 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; 75 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 76 case MipsISD::Sync: return "MipsISD::Sync"; 77 case MipsISD::Ext: return "MipsISD::Ext"; 78 case MipsISD::Ins: return "MipsISD::Ins"; 79 default: return NULL; 80 } 81} 82 83MipsTargetLowering:: 84MipsTargetLowering(MipsTargetMachine &TM) 85 : TargetLowering(TM, new MipsTargetObjectFile()), 86 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 87 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()) { 88 89 // Mips does not have i1 type, so use i32 for 90 // setcc operations results (slt, sgt, ...). 91 setBooleanContents(ZeroOrOneBooleanContent); 92 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 93 94 // Set up the register classes 95 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 96 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 97 98 if (HasMips64) 99 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); 100 101 // When dealing with single precision only, use libcalls 102 if (!Subtarget->isSingleFloat()) { 103 if (HasMips64) 104 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); 105 else 106 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 107 } 108 109 // Load extented operations for i1 types must be promoted 110 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 112 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 113 114 // MIPS doesn't have extending float->double load/store 115 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 116 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 117 118 // Used by legalize types to correctly generate the setcc result. 119 // Without this, every float setcc comes with a AND/OR with the result, 120 // we don't want this, since the fpcmp result goes to a flag register, 121 // which is used implicitly by brcond and select operations. 122 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 123 124 // Mips Custom Operations 125 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 127 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 128 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 129 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 130 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 131 setOperationAction(ISD::SELECT, MVT::f32, Custom); 132 setOperationAction(ISD::SELECT, MVT::f64, Custom); 133 setOperationAction(ISD::SELECT, MVT::i32, Custom); 134 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 135 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 136 setOperationAction(ISD::VASTART, MVT::Other, Custom); 137 138 setOperationAction(ISD::SDIV, MVT::i32, Expand); 139 setOperationAction(ISD::SREM, MVT::i32, Expand); 140 setOperationAction(ISD::UDIV, MVT::i32, Expand); 141 setOperationAction(ISD::UREM, MVT::i32, Expand); 142 setOperationAction(ISD::SDIV, MVT::i64, Expand); 143 setOperationAction(ISD::SREM, MVT::i64, Expand); 144 setOperationAction(ISD::UDIV, MVT::i64, Expand); 145 setOperationAction(ISD::UREM, MVT::i64, Expand); 146 147 // Operations not directly supported by Mips. 148 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 149 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 150 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 151 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 152 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 154 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 155 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 156 setOperationAction(ISD::ROTL, MVT::i32, Expand); 157 setOperationAction(ISD::ROTL, MVT::i64, Expand); 158 159 if (!Subtarget->hasMips32r2()) 160 setOperationAction(ISD::ROTR, MVT::i32, Expand); 161 162 if (!Subtarget->hasMips64r2()) 163 setOperationAction(ISD::ROTR, MVT::i64, Expand); 164 165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 168 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 169 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 170 setOperationAction(ISD::FSIN, MVT::f32, Expand); 171 setOperationAction(ISD::FSIN, MVT::f64, Expand); 172 setOperationAction(ISD::FCOS, MVT::f32, Expand); 173 setOperationAction(ISD::FCOS, MVT::f64, Expand); 174 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 175 setOperationAction(ISD::FPOW, MVT::f32, Expand); 176 setOperationAction(ISD::FPOW, MVT::f64, Expand); 177 setOperationAction(ISD::FLOG, MVT::f32, Expand); 178 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 179 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 180 setOperationAction(ISD::FEXP, MVT::f32, Expand); 181 setOperationAction(ISD::FMA, MVT::f32, Expand); 182 setOperationAction(ISD::FMA, MVT::f64, Expand); 183 184 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 185 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 186 187 setOperationAction(ISD::VAARG, MVT::Other, Expand); 188 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 189 setOperationAction(ISD::VAEND, MVT::Other, Expand); 190 191 // Use the default for now 192 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 193 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 194 195 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 196 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 197 198 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 199 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 200 201 setInsertFencesForAtomic(true); 202 203 if (Subtarget->isSingleFloat()) 204 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 205 206 if (!Subtarget->hasSEInReg()) { 207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 209 } 210 211 if (!Subtarget->hasBitCount()) 212 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 213 214 if (!Subtarget->hasSwap()) 215 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 216 217 setTargetDAGCombine(ISD::ADDE); 218 setTargetDAGCombine(ISD::SUBE); 219 setTargetDAGCombine(ISD::SDIVREM); 220 setTargetDAGCombine(ISD::UDIVREM); 221 setTargetDAGCombine(ISD::SETCC); 222 setTargetDAGCombine(ISD::AND); 223 setTargetDAGCombine(ISD::OR); 224 225 setMinFunctionAlignment(2); 226 227 setStackPointerRegisterToSaveRestore(Mips::SP); 228 computeRegisterProperties(); 229 230 setExceptionPointerRegister(Mips::A0); 231 setExceptionSelectorRegister(Mips::A1); 232} 233 234bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 235 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 236 return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16; 237} 238 239EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 240 return MVT::i32; 241} 242 243// SelectMadd - 244// Transforms a subgraph in CurDAG if the following pattern is found: 245// (addc multLo, Lo0), (adde multHi, Hi0), 246// where, 247// multHi/Lo: product of multiplication 248// Lo0: initial value of Lo register 249// Hi0: initial value of Hi register 250// Return true if pattern matching was successful. 251static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 252 // ADDENode's second operand must be a flag output of an ADDC node in order 253 // for the matching to be successful. 254 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 255 256 if (ADDCNode->getOpcode() != ISD::ADDC) 257 return false; 258 259 SDValue MultHi = ADDENode->getOperand(0); 260 SDValue MultLo = ADDCNode->getOperand(0); 261 SDNode* MultNode = MultHi.getNode(); 262 unsigned MultOpc = MultHi.getOpcode(); 263 264 // MultHi and MultLo must be generated by the same node, 265 if (MultLo.getNode() != MultNode) 266 return false; 267 268 // and it must be a multiplication. 269 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 270 return false; 271 272 // MultLo amd MultHi must be the first and second output of MultNode 273 // respectively. 274 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 275 return false; 276 277 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 278 // of the values of MultNode, in which case MultNode will be removed in later 279 // phases. 280 // If there exist users other than ADDENode or ADDCNode, this function returns 281 // here, which will result in MultNode being mapped to a single MULT 282 // instruction node rather than a pair of MULT and MADD instructions being 283 // produced. 284 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 285 return false; 286 287 SDValue Chain = CurDAG->getEntryNode(); 288 DebugLoc dl = ADDENode->getDebugLoc(); 289 290 // create MipsMAdd(u) node 291 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 292 293 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 294 MVT::Glue, 295 MultNode->getOperand(0),// Factor 0 296 MultNode->getOperand(1),// Factor 1 297 ADDCNode->getOperand(1),// Lo0 298 ADDENode->getOperand(1));// Hi0 299 300 // create CopyFromReg nodes 301 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 302 MAdd); 303 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 304 Mips::HI, MVT::i32, 305 CopyFromLo.getValue(2)); 306 307 // replace uses of adde and addc here 308 if (!SDValue(ADDCNode, 0).use_empty()) 309 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 310 311 if (!SDValue(ADDENode, 0).use_empty()) 312 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 313 314 return true; 315} 316 317// SelectMsub - 318// Transforms a subgraph in CurDAG if the following pattern is found: 319// (addc Lo0, multLo), (sube Hi0, multHi), 320// where, 321// multHi/Lo: product of multiplication 322// Lo0: initial value of Lo register 323// Hi0: initial value of Hi register 324// Return true if pattern matching was successful. 325static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 326 // SUBENode's second operand must be a flag output of an SUBC node in order 327 // for the matching to be successful. 328 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 329 330 if (SUBCNode->getOpcode() != ISD::SUBC) 331 return false; 332 333 SDValue MultHi = SUBENode->getOperand(1); 334 SDValue MultLo = SUBCNode->getOperand(1); 335 SDNode* MultNode = MultHi.getNode(); 336 unsigned MultOpc = MultHi.getOpcode(); 337 338 // MultHi and MultLo must be generated by the same node, 339 if (MultLo.getNode() != MultNode) 340 return false; 341 342 // and it must be a multiplication. 343 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 344 return false; 345 346 // MultLo amd MultHi must be the first and second output of MultNode 347 // respectively. 348 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 349 return false; 350 351 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 352 // of the values of MultNode, in which case MultNode will be removed in later 353 // phases. 354 // If there exist users other than SUBENode or SUBCNode, this function returns 355 // here, which will result in MultNode being mapped to a single MULT 356 // instruction node rather than a pair of MULT and MSUB instructions being 357 // produced. 358 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 359 return false; 360 361 SDValue Chain = CurDAG->getEntryNode(); 362 DebugLoc dl = SUBENode->getDebugLoc(); 363 364 // create MipsSub(u) node 365 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 366 367 SDValue MSub = CurDAG->getNode(MultOpc, dl, 368 MVT::Glue, 369 MultNode->getOperand(0),// Factor 0 370 MultNode->getOperand(1),// Factor 1 371 SUBCNode->getOperand(0),// Lo0 372 SUBENode->getOperand(0));// Hi0 373 374 // create CopyFromReg nodes 375 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 376 MSub); 377 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 378 Mips::HI, MVT::i32, 379 CopyFromLo.getValue(2)); 380 381 // replace uses of sube and subc here 382 if (!SDValue(SUBCNode, 0).use_empty()) 383 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 384 385 if (!SDValue(SUBENode, 0).use_empty()) 386 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 387 388 return true; 389} 390 391static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 392 TargetLowering::DAGCombinerInfo &DCI, 393 const MipsSubtarget* Subtarget) { 394 if (DCI.isBeforeLegalize()) 395 return SDValue(); 396 397 if (Subtarget->hasMips32() && SelectMadd(N, &DAG)) 398 return SDValue(N, 0); 399 400 return SDValue(); 401} 402 403static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 404 TargetLowering::DAGCombinerInfo &DCI, 405 const MipsSubtarget* Subtarget) { 406 if (DCI.isBeforeLegalize()) 407 return SDValue(); 408 409 if (Subtarget->hasMips32() && SelectMsub(N, &DAG)) 410 return SDValue(N, 0); 411 412 return SDValue(); 413} 414 415static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 416 TargetLowering::DAGCombinerInfo &DCI, 417 const MipsSubtarget* Subtarget) { 418 if (DCI.isBeforeLegalizeOps()) 419 return SDValue(); 420 421 EVT Ty = N->getValueType(0); 422 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 423 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 424 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 425 MipsISD::DivRemU; 426 DebugLoc dl = N->getDebugLoc(); 427 428 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 429 N->getOperand(0), N->getOperand(1)); 430 SDValue InChain = DAG.getEntryNode(); 431 SDValue InGlue = DivRem; 432 433 // insert MFLO 434 if (N->hasAnyUseOfValue(0)) { 435 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 436 InGlue); 437 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 438 InChain = CopyFromLo.getValue(1); 439 InGlue = CopyFromLo.getValue(2); 440 } 441 442 // insert MFHI 443 if (N->hasAnyUseOfValue(1)) { 444 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 445 HI, Ty, InGlue); 446 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 447 } 448 449 return SDValue(); 450} 451 452static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 453 switch (CC) { 454 default: llvm_unreachable("Unknown fp condition code!"); 455 case ISD::SETEQ: 456 case ISD::SETOEQ: return Mips::FCOND_OEQ; 457 case ISD::SETUNE: return Mips::FCOND_UNE; 458 case ISD::SETLT: 459 case ISD::SETOLT: return Mips::FCOND_OLT; 460 case ISD::SETGT: 461 case ISD::SETOGT: return Mips::FCOND_OGT; 462 case ISD::SETLE: 463 case ISD::SETOLE: return Mips::FCOND_OLE; 464 case ISD::SETGE: 465 case ISD::SETOGE: return Mips::FCOND_OGE; 466 case ISD::SETULT: return Mips::FCOND_ULT; 467 case ISD::SETULE: return Mips::FCOND_ULE; 468 case ISD::SETUGT: return Mips::FCOND_UGT; 469 case ISD::SETUGE: return Mips::FCOND_UGE; 470 case ISD::SETUO: return Mips::FCOND_UN; 471 case ISD::SETO: return Mips::FCOND_OR; 472 case ISD::SETNE: 473 case ISD::SETONE: return Mips::FCOND_ONE; 474 case ISD::SETUEQ: return Mips::FCOND_UEQ; 475 } 476} 477 478 479// Returns true if condition code has to be inverted. 480static bool InvertFPCondCode(Mips::CondCode CC) { 481 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 482 return false; 483 484 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 485 return true; 486 487 assert(false && "Illegal Condition Code"); 488 return false; 489} 490 491// Creates and returns an FPCmp node from a setcc node. 492// Returns Op if setcc is not a floating point comparison. 493static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 494 // must be a SETCC node 495 if (Op.getOpcode() != ISD::SETCC) 496 return Op; 497 498 SDValue LHS = Op.getOperand(0); 499 500 if (!LHS.getValueType().isFloatingPoint()) 501 return Op; 502 503 SDValue RHS = Op.getOperand(1); 504 DebugLoc dl = Op.getDebugLoc(); 505 506 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 507 // node if necessary. 508 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 509 510 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 511 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 512} 513 514// Creates and returns a CMovFPT/F node. 515static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 516 SDValue False, DebugLoc DL) { 517 bool invert = InvertFPCondCode((Mips::CondCode) 518 cast<ConstantSDNode>(Cond.getOperand(2)) 519 ->getSExtValue()); 520 521 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 522 True.getValueType(), True, False, Cond); 523} 524 525static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 526 TargetLowering::DAGCombinerInfo &DCI, 527 const MipsSubtarget* Subtarget) { 528 if (DCI.isBeforeLegalizeOps()) 529 return SDValue(); 530 531 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 532 533 if (Cond.getOpcode() != MipsISD::FPCmp) 534 return SDValue(); 535 536 SDValue True = DAG.getConstant(1, MVT::i32); 537 SDValue False = DAG.getConstant(0, MVT::i32); 538 539 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 540} 541 542static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG, 543 TargetLowering::DAGCombinerInfo &DCI, 544 const MipsSubtarget* Subtarget) { 545 // Pattern match EXT. 546 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 547 // => ext $dst, $src, size, pos 548 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 549 return SDValue(); 550 551 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 552 553 // Op's first operand must be a shift right. 554 if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL) 555 return SDValue(); 556 557 // The second operand of the shift must be an immediate. 558 uint64_t Pos; 559 ConstantSDNode *CN; 560 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 561 return SDValue(); 562 563 Pos = CN->getZExtValue(); 564 565 uint64_t SMPos, SMSize; 566 // Op's second operand must be a shifted mask. 567 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 568 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 569 return SDValue(); 570 571 // Return if the shifted mask does not start at bit 0 or the sum of its size 572 // and Pos exceeds the word's size. 573 if (SMPos != 0 || Pos + SMSize > 32) 574 return SDValue(); 575 576 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32, 577 ShiftRight.getOperand(0), 578 DAG.getConstant(Pos, MVT::i32), 579 DAG.getConstant(SMSize, MVT::i32)); 580} 581 582static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG, 583 TargetLowering::DAGCombinerInfo &DCI, 584 const MipsSubtarget* Subtarget) { 585 // Pattern match INS. 586 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 587 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 588 // => ins $dst, $src, size, pos, $src1 589 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 590 return SDValue(); 591 592 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 593 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 594 ConstantSDNode *CN; 595 596 // See if Op's first operand matches (and $src1 , mask0). 597 if (And0.getOpcode() != ISD::AND) 598 return SDValue(); 599 600 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 601 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 602 return SDValue(); 603 604 // See if Op's second operand matches (and (shl $src, pos), mask1). 605 if (And1.getOpcode() != ISD::AND) 606 return SDValue(); 607 608 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 609 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 610 return SDValue(); 611 612 // The shift masks must have the same position and size. 613 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 614 return SDValue(); 615 616 SDValue Shl = And1.getOperand(0); 617 if (Shl.getOpcode() != ISD::SHL) 618 return SDValue(); 619 620 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 621 return SDValue(); 622 623 unsigned Shamt = CN->getZExtValue(); 624 625 // Return if the shift amount and the first bit position of mask are not the 626 // same. 627 if (Shamt != SMPos0) 628 return SDValue(); 629 630 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32, 631 Shl.getOperand(0), 632 DAG.getConstant(SMPos0, MVT::i32), 633 DAG.getConstant(SMSize0, MVT::i32), 634 And0.getOperand(0)); 635} 636 637SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 638 const { 639 SelectionDAG &DAG = DCI.DAG; 640 unsigned opc = N->getOpcode(); 641 642 switch (opc) { 643 default: break; 644 case ISD::ADDE: 645 return PerformADDECombine(N, DAG, DCI, Subtarget); 646 case ISD::SUBE: 647 return PerformSUBECombine(N, DAG, DCI, Subtarget); 648 case ISD::SDIVREM: 649 case ISD::UDIVREM: 650 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 651 case ISD::SETCC: 652 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 653 case ISD::AND: 654 return PerformANDCombine(N, DAG, DCI, Subtarget); 655 case ISD::OR: 656 return PerformORCombine(N, DAG, DCI, Subtarget); 657 } 658 659 return SDValue(); 660} 661 662SDValue MipsTargetLowering:: 663LowerOperation(SDValue Op, SelectionDAG &DAG) const 664{ 665 switch (Op.getOpcode()) 666 { 667 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 668 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 669 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 670 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 671 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 672 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 673 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 674 case ISD::SELECT: return LowerSELECT(Op, DAG); 675 case ISD::VASTART: return LowerVASTART(Op, DAG); 676 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 677 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 678 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 679 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 680 } 681 return SDValue(); 682} 683 684//===----------------------------------------------------------------------===// 685// Lower helper functions 686//===----------------------------------------------------------------------===// 687 688// AddLiveIn - This helper function adds the specified physical register to the 689// MachineFunction as a live in value. It also creates a corresponding 690// virtual register for it. 691static unsigned 692AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 693{ 694 assert(RC->contains(PReg) && "Not the correct regclass!"); 695 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 696 MF.getRegInfo().addLiveIn(PReg, VReg); 697 return VReg; 698} 699 700// Get fp branch code (not opcode) from condition code. 701static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 702 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 703 return Mips::BRANCH_T; 704 705 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 706 return Mips::BRANCH_F; 707 708 return Mips::BRANCH_INVALID; 709} 710 711static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 712 DebugLoc dl, 713 const MipsSubtarget* Subtarget, 714 const TargetInstrInfo *TII, 715 bool isFPCmp, unsigned Opc) { 716 // There is no need to expand CMov instructions if target has 717 // conditional moves. 718 if (Subtarget->hasCondMov()) 719 return BB; 720 721 // To "insert" a SELECT_CC instruction, we actually have to insert the 722 // diamond control-flow pattern. The incoming instruction knows the 723 // destination vreg to set, the condition code register to branch on, the 724 // true/false values to select between, and a branch opcode to use. 725 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 726 MachineFunction::iterator It = BB; 727 ++It; 728 729 // thisMBB: 730 // ... 731 // TrueVal = ... 732 // setcc r1, r2, r3 733 // bNE r1, r0, copy1MBB 734 // fallthrough --> copy0MBB 735 MachineBasicBlock *thisMBB = BB; 736 MachineFunction *F = BB->getParent(); 737 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 738 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 739 F->insert(It, copy0MBB); 740 F->insert(It, sinkMBB); 741 742 // Transfer the remainder of BB and its successor edges to sinkMBB. 743 sinkMBB->splice(sinkMBB->begin(), BB, 744 llvm::next(MachineBasicBlock::iterator(MI)), 745 BB->end()); 746 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 747 748 // Next, add the true and fallthrough blocks as its successors. 749 BB->addSuccessor(copy0MBB); 750 BB->addSuccessor(sinkMBB); 751 752 // Emit the right instruction according to the type of the operands compared 753 if (isFPCmp) 754 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 755 else 756 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 757 .addReg(Mips::ZERO).addMBB(sinkMBB); 758 759 // copy0MBB: 760 // %FalseValue = ... 761 // # fallthrough to sinkMBB 762 BB = copy0MBB; 763 764 // Update machine-CFG edges 765 BB->addSuccessor(sinkMBB); 766 767 // sinkMBB: 768 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 769 // ... 770 BB = sinkMBB; 771 772 if (isFPCmp) 773 BuildMI(*BB, BB->begin(), dl, 774 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 775 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 776 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 777 else 778 BuildMI(*BB, BB->begin(), dl, 779 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 780 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 781 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 782 783 MI->eraseFromParent(); // The pseudo instruction is gone now. 784 return BB; 785} 786 787MachineBasicBlock * 788MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 789 MachineBasicBlock *BB) const { 790 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 791 DebugLoc dl = MI->getDebugLoc(); 792 793 switch (MI->getOpcode()) { 794 default: 795 assert(false && "Unexpected instr type to insert"); 796 return NULL; 797 case Mips::MOVT: 798 case Mips::MOVT_S: 799 case Mips::MOVT_D: 800 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F); 801 case Mips::MOVF: 802 case Mips::MOVF_S: 803 case Mips::MOVF_D: 804 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T); 805 case Mips::MOVZ_I: 806 case Mips::MOVZ_S: 807 case Mips::MOVZ_D: 808 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE); 809 case Mips::MOVN_I: 810 case Mips::MOVN_S: 811 case Mips::MOVN_D: 812 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ); 813 814 case Mips::ATOMIC_LOAD_ADD_I8: 815 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 816 case Mips::ATOMIC_LOAD_ADD_I16: 817 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 818 case Mips::ATOMIC_LOAD_ADD_I32: 819 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 820 821 case Mips::ATOMIC_LOAD_AND_I8: 822 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 823 case Mips::ATOMIC_LOAD_AND_I16: 824 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 825 case Mips::ATOMIC_LOAD_AND_I32: 826 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 827 828 case Mips::ATOMIC_LOAD_OR_I8: 829 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 830 case Mips::ATOMIC_LOAD_OR_I16: 831 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 832 case Mips::ATOMIC_LOAD_OR_I32: 833 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 834 835 case Mips::ATOMIC_LOAD_XOR_I8: 836 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 837 case Mips::ATOMIC_LOAD_XOR_I16: 838 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 839 case Mips::ATOMIC_LOAD_XOR_I32: 840 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 841 842 case Mips::ATOMIC_LOAD_NAND_I8: 843 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 844 case Mips::ATOMIC_LOAD_NAND_I16: 845 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 846 case Mips::ATOMIC_LOAD_NAND_I32: 847 return EmitAtomicBinary(MI, BB, 4, 0, true); 848 849 case Mips::ATOMIC_LOAD_SUB_I8: 850 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 851 case Mips::ATOMIC_LOAD_SUB_I16: 852 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 853 case Mips::ATOMIC_LOAD_SUB_I32: 854 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 855 856 case Mips::ATOMIC_SWAP_I8: 857 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 858 case Mips::ATOMIC_SWAP_I16: 859 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 860 case Mips::ATOMIC_SWAP_I32: 861 return EmitAtomicBinary(MI, BB, 4, 0); 862 863 case Mips::ATOMIC_CMP_SWAP_I8: 864 return EmitAtomicCmpSwapPartword(MI, BB, 1); 865 case Mips::ATOMIC_CMP_SWAP_I16: 866 return EmitAtomicCmpSwapPartword(MI, BB, 2); 867 case Mips::ATOMIC_CMP_SWAP_I32: 868 return EmitAtomicCmpSwap(MI, BB, 4); 869 } 870} 871 872// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 873// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 874MachineBasicBlock * 875MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 876 unsigned Size, unsigned BinOpcode, 877 bool Nand) const { 878 assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); 879 880 MachineFunction *MF = BB->getParent(); 881 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 882 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 883 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 884 DebugLoc dl = MI->getDebugLoc(); 885 886 unsigned OldVal = MI->getOperand(0).getReg(); 887 unsigned Ptr = MI->getOperand(1).getReg(); 888 unsigned Incr = MI->getOperand(2).getReg(); 889 890 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 891 unsigned AndRes = RegInfo.createVirtualRegister(RC); 892 unsigned Success = RegInfo.createVirtualRegister(RC); 893 894 // insert new blocks after the current block 895 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 896 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 897 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 898 MachineFunction::iterator It = BB; 899 ++It; 900 MF->insert(It, loopMBB); 901 MF->insert(It, exitMBB); 902 903 // Transfer the remainder of BB and its successor edges to exitMBB. 904 exitMBB->splice(exitMBB->begin(), BB, 905 llvm::next(MachineBasicBlock::iterator(MI)), 906 BB->end()); 907 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 908 909 // thisMBB: 910 // ... 911 // fallthrough --> loopMBB 912 BB->addSuccessor(loopMBB); 913 loopMBB->addSuccessor(loopMBB); 914 loopMBB->addSuccessor(exitMBB); 915 916 // loopMBB: 917 // ll oldval, 0(ptr) 918 // <binop> storeval, oldval, incr 919 // sc success, storeval, 0(ptr) 920 // beq success, $0, loopMBB 921 BB = loopMBB; 922 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0); 923 if (Nand) { 924 // and andres, oldval, incr 925 // nor storeval, $0, andres 926 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr); 927 BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal) 928 .addReg(Mips::ZERO).addReg(AndRes); 929 } else if (BinOpcode) { 930 // <binop> storeval, oldval, incr 931 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 932 } else { 933 StoreVal = Incr; 934 } 935 BuildMI(BB, dl, TII->get(Mips::SC), Success) 936 .addReg(StoreVal).addReg(Ptr).addImm(0); 937 BuildMI(BB, dl, TII->get(Mips::BEQ)) 938 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 939 940 MI->eraseFromParent(); // The instruction is gone now. 941 942 return exitMBB; 943} 944 945MachineBasicBlock * 946MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 947 MachineBasicBlock *BB, 948 unsigned Size, unsigned BinOpcode, 949 bool Nand) const { 950 assert((Size == 1 || Size == 2) && 951 "Unsupported size for EmitAtomicBinaryPartial."); 952 953 MachineFunction *MF = BB->getParent(); 954 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 955 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 956 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 957 DebugLoc dl = MI->getDebugLoc(); 958 959 unsigned Dest = MI->getOperand(0).getReg(); 960 unsigned Ptr = MI->getOperand(1).getReg(); 961 unsigned Incr = MI->getOperand(2).getReg(); 962 963 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 964 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 965 unsigned Mask = RegInfo.createVirtualRegister(RC); 966 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 967 unsigned NewVal = RegInfo.createVirtualRegister(RC); 968 unsigned OldVal = RegInfo.createVirtualRegister(RC); 969 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 970 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 971 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 972 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 973 unsigned AndRes = RegInfo.createVirtualRegister(RC); 974 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 975 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 976 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 977 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 978 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 979 unsigned SllRes = RegInfo.createVirtualRegister(RC); 980 unsigned Success = RegInfo.createVirtualRegister(RC); 981 982 // insert new blocks after the current block 983 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 984 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 985 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 986 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 987 MachineFunction::iterator It = BB; 988 ++It; 989 MF->insert(It, loopMBB); 990 MF->insert(It, sinkMBB); 991 MF->insert(It, exitMBB); 992 993 // Transfer the remainder of BB and its successor edges to exitMBB. 994 exitMBB->splice(exitMBB->begin(), BB, 995 llvm::next(MachineBasicBlock::iterator(MI)), 996 BB->end()); 997 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 998 999 BB->addSuccessor(loopMBB); 1000 loopMBB->addSuccessor(loopMBB); 1001 loopMBB->addSuccessor(sinkMBB); 1002 sinkMBB->addSuccessor(exitMBB); 1003 1004 // thisMBB: 1005 // addiu masklsb2,$0,-4 # 0xfffffffc 1006 // and alignedaddr,ptr,masklsb2 1007 // andi ptrlsb2,ptr,3 1008 // sll shiftamt,ptrlsb2,3 1009 // ori maskupper,$0,255 # 0xff 1010 // sll mask,maskupper,shiftamt 1011 // nor mask2,$0,mask 1012 // sll incr2,incr,shiftamt 1013 1014 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1015 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1016 .addReg(Mips::ZERO).addImm(-4); 1017 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1018 .addReg(Ptr).addReg(MaskLSB2); 1019 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1020 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1021 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1022 .addReg(Mips::ZERO).addImm(MaskImm); 1023 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1024 .addReg(ShiftAmt).addReg(MaskUpper); 1025 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1026 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1027 1028 1029 // atomic.load.binop 1030 // loopMBB: 1031 // ll oldval,0(alignedaddr) 1032 // binop binopres,oldval,incr2 1033 // and newval,binopres,mask 1034 // and maskedoldval0,oldval,mask2 1035 // or storeval,maskedoldval0,newval 1036 // sc success,storeval,0(alignedaddr) 1037 // beq success,$0,loopMBB 1038 1039 // atomic.swap 1040 // loopMBB: 1041 // ll oldval,0(alignedaddr) 1042 // and newval,incr2,mask 1043 // and maskedoldval0,oldval,mask2 1044 // or storeval,maskedoldval0,newval 1045 // sc success,storeval,0(alignedaddr) 1046 // beq success,$0,loopMBB 1047 1048 BB = loopMBB; 1049 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1050 if (Nand) { 1051 // and andres, oldval, incr2 1052 // nor binopres, $0, andres 1053 // and newval, binopres, mask 1054 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1055 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1056 .addReg(Mips::ZERO).addReg(AndRes); 1057 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1058 } else if (BinOpcode) { 1059 // <binop> binopres, oldval, incr2 1060 // and newval, binopres, mask 1061 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1062 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1063 } else {// atomic.swap 1064 // and newval, incr2, mask 1065 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1066 } 1067 1068 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1069 .addReg(OldVal).addReg(Mask2); 1070 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1071 .addReg(MaskedOldVal0).addReg(NewVal); 1072 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1073 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1074 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1075 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1076 1077 // sinkMBB: 1078 // and maskedoldval1,oldval,mask 1079 // srl srlres,maskedoldval1,shiftamt 1080 // sll sllres,srlres,24 1081 // sra dest,sllres,24 1082 BB = sinkMBB; 1083 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1084 1085 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1086 .addReg(OldVal).addReg(Mask); 1087 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1088 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1089 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1090 .addReg(SrlRes).addImm(ShiftImm); 1091 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1092 .addReg(SllRes).addImm(ShiftImm); 1093 1094 MI->eraseFromParent(); // The instruction is gone now. 1095 1096 return exitMBB; 1097} 1098 1099MachineBasicBlock * 1100MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1101 MachineBasicBlock *BB, 1102 unsigned Size) const { 1103 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); 1104 1105 MachineFunction *MF = BB->getParent(); 1106 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1107 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1108 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1109 DebugLoc dl = MI->getDebugLoc(); 1110 1111 unsigned Dest = MI->getOperand(0).getReg(); 1112 unsigned Ptr = MI->getOperand(1).getReg(); 1113 unsigned OldVal = MI->getOperand(2).getReg(); 1114 unsigned NewVal = MI->getOperand(3).getReg(); 1115 1116 unsigned Success = RegInfo.createVirtualRegister(RC); 1117 1118 // insert new blocks after the current block 1119 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1120 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1121 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1122 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1123 MachineFunction::iterator It = BB; 1124 ++It; 1125 MF->insert(It, loop1MBB); 1126 MF->insert(It, loop2MBB); 1127 MF->insert(It, exitMBB); 1128 1129 // Transfer the remainder of BB and its successor edges to exitMBB. 1130 exitMBB->splice(exitMBB->begin(), BB, 1131 llvm::next(MachineBasicBlock::iterator(MI)), 1132 BB->end()); 1133 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1134 1135 // thisMBB: 1136 // ... 1137 // fallthrough --> loop1MBB 1138 BB->addSuccessor(loop1MBB); 1139 loop1MBB->addSuccessor(exitMBB); 1140 loop1MBB->addSuccessor(loop2MBB); 1141 loop2MBB->addSuccessor(loop1MBB); 1142 loop2MBB->addSuccessor(exitMBB); 1143 1144 // loop1MBB: 1145 // ll dest, 0(ptr) 1146 // bne dest, oldval, exitMBB 1147 BB = loop1MBB; 1148 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); 1149 BuildMI(BB, dl, TII->get(Mips::BNE)) 1150 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1151 1152 // loop2MBB: 1153 // sc success, newval, 0(ptr) 1154 // beq success, $0, loop1MBB 1155 BB = loop2MBB; 1156 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1157 .addReg(NewVal).addReg(Ptr).addImm(0); 1158 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1159 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1160 1161 MI->eraseFromParent(); // The instruction is gone now. 1162 1163 return exitMBB; 1164} 1165 1166MachineBasicBlock * 1167MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1168 MachineBasicBlock *BB, 1169 unsigned Size) const { 1170 assert((Size == 1 || Size == 2) && 1171 "Unsupported size for EmitAtomicCmpSwapPartial."); 1172 1173 MachineFunction *MF = BB->getParent(); 1174 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1175 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1176 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1177 DebugLoc dl = MI->getDebugLoc(); 1178 1179 unsigned Dest = MI->getOperand(0).getReg(); 1180 unsigned Ptr = MI->getOperand(1).getReg(); 1181 unsigned CmpVal = MI->getOperand(2).getReg(); 1182 unsigned NewVal = MI->getOperand(3).getReg(); 1183 1184 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1185 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1186 unsigned Mask = RegInfo.createVirtualRegister(RC); 1187 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1188 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1189 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1190 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1191 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1192 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1193 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1194 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1195 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1196 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1197 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1198 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1199 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1200 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1201 unsigned Success = RegInfo.createVirtualRegister(RC); 1202 1203 // insert new blocks after the current block 1204 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1205 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1206 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1207 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1208 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1209 MachineFunction::iterator It = BB; 1210 ++It; 1211 MF->insert(It, loop1MBB); 1212 MF->insert(It, loop2MBB); 1213 MF->insert(It, sinkMBB); 1214 MF->insert(It, exitMBB); 1215 1216 // Transfer the remainder of BB and its successor edges to exitMBB. 1217 exitMBB->splice(exitMBB->begin(), BB, 1218 llvm::next(MachineBasicBlock::iterator(MI)), 1219 BB->end()); 1220 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1221 1222 BB->addSuccessor(loop1MBB); 1223 loop1MBB->addSuccessor(sinkMBB); 1224 loop1MBB->addSuccessor(loop2MBB); 1225 loop2MBB->addSuccessor(loop1MBB); 1226 loop2MBB->addSuccessor(sinkMBB); 1227 sinkMBB->addSuccessor(exitMBB); 1228 1229 // FIXME: computation of newval2 can be moved to loop2MBB. 1230 // thisMBB: 1231 // addiu masklsb2,$0,-4 # 0xfffffffc 1232 // and alignedaddr,ptr,masklsb2 1233 // andi ptrlsb2,ptr,3 1234 // sll shiftamt,ptrlsb2,3 1235 // ori maskupper,$0,255 # 0xff 1236 // sll mask,maskupper,shiftamt 1237 // nor mask2,$0,mask 1238 // andi maskedcmpval,cmpval,255 1239 // sll shiftedcmpval,maskedcmpval,shiftamt 1240 // andi maskednewval,newval,255 1241 // sll shiftednewval,maskednewval,shiftamt 1242 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1243 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1244 .addReg(Mips::ZERO).addImm(-4); 1245 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1246 .addReg(Ptr).addReg(MaskLSB2); 1247 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1248 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1249 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1250 .addReg(Mips::ZERO).addImm(MaskImm); 1251 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1252 .addReg(ShiftAmt).addReg(MaskUpper); 1253 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1254 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1255 .addReg(CmpVal).addImm(MaskImm); 1256 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1257 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1258 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1259 .addReg(NewVal).addImm(MaskImm); 1260 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1261 .addReg(ShiftAmt).addReg(MaskedNewVal); 1262 1263 // loop1MBB: 1264 // ll oldval,0(alginedaddr) 1265 // and maskedoldval0,oldval,mask 1266 // bne maskedoldval0,shiftedcmpval,sinkMBB 1267 BB = loop1MBB; 1268 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1269 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1270 .addReg(OldVal).addReg(Mask); 1271 BuildMI(BB, dl, TII->get(Mips::BNE)) 1272 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1273 1274 // loop2MBB: 1275 // and maskedoldval1,oldval,mask2 1276 // or storeval,maskedoldval1,shiftednewval 1277 // sc success,storeval,0(alignedaddr) 1278 // beq success,$0,loop1MBB 1279 BB = loop2MBB; 1280 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1281 .addReg(OldVal).addReg(Mask2); 1282 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1283 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1284 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1285 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1286 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1287 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1288 1289 // sinkMBB: 1290 // srl srlres,maskedoldval0,shiftamt 1291 // sll sllres,srlres,24 1292 // sra dest,sllres,24 1293 BB = sinkMBB; 1294 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1295 1296 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1297 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1298 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1299 .addReg(SrlRes).addImm(ShiftImm); 1300 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1301 .addReg(SllRes).addImm(ShiftImm); 1302 1303 MI->eraseFromParent(); // The instruction is gone now. 1304 1305 return exitMBB; 1306} 1307 1308//===----------------------------------------------------------------------===// 1309// Misc Lower Operation implementation 1310//===----------------------------------------------------------------------===// 1311SDValue MipsTargetLowering:: 1312LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1313{ 1314 MachineFunction &MF = DAG.getMachineFunction(); 1315 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1316 1317 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1318 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1319 "Cannot lower if the alignment of the allocated space is larger than \ 1320 that of the stack."); 1321 1322 SDValue Chain = Op.getOperand(0); 1323 SDValue Size = Op.getOperand(1); 1324 DebugLoc dl = Op.getDebugLoc(); 1325 1326 // Get a reference from Mips stack pointer 1327 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 1328 1329 // Subtract the dynamic size from the actual stack size to 1330 // obtain the new stack size. 1331 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 1332 1333 // The Sub result contains the new stack start address, so it 1334 // must be placed in the stack pointer register. 1335 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, 1336 SDValue()); 1337 1338 // This node always has two return values: a new stack pointer 1339 // value and a chain 1340 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); 1341 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1342 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1343 1344 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1345} 1346 1347SDValue MipsTargetLowering:: 1348LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1349{ 1350 // The first operand is the chain, the second is the condition, the third is 1351 // the block to branch to if the condition is true. 1352 SDValue Chain = Op.getOperand(0); 1353 SDValue Dest = Op.getOperand(2); 1354 DebugLoc dl = Op.getDebugLoc(); 1355 1356 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1357 1358 // Return if flag is not set by a floating point comparison. 1359 if (CondRes.getOpcode() != MipsISD::FPCmp) 1360 return Op; 1361 1362 SDValue CCNode = CondRes.getOperand(2); 1363 Mips::CondCode CC = 1364 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1365 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1366 1367 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1368 Dest, CondRes); 1369} 1370 1371SDValue MipsTargetLowering:: 1372LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1373{ 1374 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1375 1376 // Return if flag is not set by a floating point comparison. 1377 if (Cond.getOpcode() != MipsISD::FPCmp) 1378 return Op; 1379 1380 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1381 Op.getDebugLoc()); 1382} 1383 1384SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1385 SelectionDAG &DAG) const { 1386 // FIXME there isn't actually debug info here 1387 DebugLoc dl = Op.getDebugLoc(); 1388 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1389 1390 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1391 SDVTList VTs = DAG.getVTList(MVT::i32); 1392 1393 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1394 1395 // %gp_rel relocation 1396 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1397 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1398 MipsII::MO_GPREL); 1399 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1400 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1401 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1402 } 1403 // %hi/%lo relocation 1404 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1405 MipsII::MO_ABS_HI); 1406 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1407 MipsII::MO_ABS_LO); 1408 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1409 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1410 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1411 } 1412 1413 EVT ValTy = Op.getValueType(); 1414 bool HasGotOfst = (GV->hasInternalLinkage() || 1415 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1416 unsigned GotFlag = IsN64 ? 1417 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1418 MipsII::MO_GOT; 1419 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1420 GA = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, GA); 1421 SDValue ResNode = DAG.getLoad(ValTy, dl, 1422 DAG.getEntryNode(), GA, MachinePointerInfo(), 1423 false, false, 0); 1424 // On functions and global targets not internal linked only 1425 // a load from got/GP is necessary for PIC to work. 1426 if (!HasGotOfst) 1427 return ResNode; 1428 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1429 IsN64 ? MipsII::MO_GOT_OFST : 1430 MipsII::MO_ABS_LO); 1431 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1432 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1433} 1434 1435SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1436 SelectionDAG &DAG) const { 1437 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1438 // FIXME there isn't actually debug info here 1439 DebugLoc dl = Op.getDebugLoc(); 1440 1441 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1442 // %hi/%lo relocation 1443 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 1444 MipsII::MO_ABS_HI); 1445 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 1446 MipsII::MO_ABS_LO); 1447 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1448 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1449 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1450 } 1451 1452 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1453 MipsII::MO_GOT); 1454 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset); 1455 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1456 MipsII::MO_ABS_LO); 1457 SDValue Load = DAG.getLoad(MVT::i32, dl, 1458 DAG.getEntryNode(), BAGOTOffset, 1459 MachinePointerInfo(), false, false, 0); 1460 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 1461 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1462} 1463 1464SDValue MipsTargetLowering:: 1465LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1466{ 1467 // If the relocation model is PIC, use the General Dynamic TLS Model, 1468 // otherwise use the Initial Exec or Local Exec TLS Model. 1469 // TODO: implement Local Dynamic TLS model 1470 1471 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1472 DebugLoc dl = GA->getDebugLoc(); 1473 const GlobalValue *GV = GA->getGlobal(); 1474 EVT PtrVT = getPointerTy(); 1475 1476 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1477 // General Dynamic TLS Model 1478 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 1479 0, MipsII::MO_TLSGD); 1480 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA); 1481 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32); 1482 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd); 1483 1484 ArgListTy Args; 1485 ArgListEntry Entry; 1486 Entry.Node = Argument; 1487 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 1488 Args.push_back(Entry); 1489 std::pair<SDValue, SDValue> CallResult = 1490 LowerCallTo(DAG.getEntryNode(), 1491 (Type *) Type::getInt32Ty(*DAG.getContext()), 1492 false, false, false, false, 0, CallingConv::C, false, true, 1493 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, 1494 dl); 1495 1496 return CallResult.first; 1497 } 1498 1499 SDValue Offset; 1500 if (GV->isDeclaration()) { 1501 // Initial Exec TLS Model 1502 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1503 MipsII::MO_GOTTPREL); 1504 Offset = DAG.getLoad(MVT::i32, dl, 1505 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1506 false, false, 0); 1507 } else { 1508 // Local Exec TLS Model 1509 SDVTList VTs = DAG.getVTList(MVT::i32); 1510 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1511 MipsII::MO_TPREL_HI); 1512 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1513 MipsII::MO_TPREL_LO); 1514 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1); 1515 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo); 1516 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1517 } 1518 1519 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1520 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1521} 1522 1523SDValue MipsTargetLowering:: 1524LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1525{ 1526 SDValue ResNode; 1527 SDValue HiPart; 1528 // FIXME there isn't actually debug info here 1529 DebugLoc dl = Op.getDebugLoc(); 1530 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1531 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 1532 1533 EVT PtrVT = Op.getValueType(); 1534 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1535 1536 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 1537 1538 if (!IsPIC) { 1539 SDValue Ops[] = { JTI }; 1540 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 1541 } else {// Emit Load from Global Pointer 1542 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); 1543 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 1544 MachinePointerInfo(), 1545 false, false, 0); 1546 } 1547 1548 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 1549 MipsII::MO_ABS_LO); 1550 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 1551 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1552 1553 return ResNode; 1554} 1555 1556SDValue MipsTargetLowering:: 1557LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1558{ 1559 SDValue ResNode; 1560 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1561 const Constant *C = N->getConstVal(); 1562 // FIXME there isn't actually debug info here 1563 DebugLoc dl = Op.getDebugLoc(); 1564 1565 // gp_rel relocation 1566 // FIXME: we should reference the constant pool using small data sections, 1567 // but the asm printer currently doesn't support this feature without 1568 // hacking it. This feature should come soon so we can uncomment the 1569 // stuff below. 1570 //if (IsInSmallSection(C->getType())) { 1571 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1572 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1573 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1574 1575 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1576 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1577 N->getOffset(), MipsII::MO_ABS_HI); 1578 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1579 N->getOffset(), MipsII::MO_ABS_LO); 1580 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1581 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1582 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1583 } else { 1584 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1585 N->getOffset(), MipsII::MO_GOT); 1586 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP); 1587 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 1588 CP, MachinePointerInfo::getConstantPool(), 1589 false, false, 0); 1590 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1591 N->getOffset(), MipsII::MO_ABS_LO); 1592 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1593 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1594 } 1595 1596 return ResNode; 1597} 1598 1599SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1600 MachineFunction &MF = DAG.getMachineFunction(); 1601 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1602 1603 DebugLoc dl = Op.getDebugLoc(); 1604 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1605 getPointerTy()); 1606 1607 // vastart just stores the address of the VarArgsFrameIndex slot into the 1608 // memory location argument. 1609 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1610 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1611 MachinePointerInfo(SV), 1612 false, false, 0); 1613} 1614 1615static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) { 1616 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1617 DebugLoc dl = Op.getDebugLoc(); 1618 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0)); 1619 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1)); 1620 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0, 1621 DAG.getConstant(0x7fffffff, MVT::i32)); 1622 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1, 1623 DAG.getConstant(0x80000000, MVT::i32)); 1624 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1625 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result); 1626} 1627 1628static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1629 // FIXME: 1630 // Use ext/ins instructions if target architecture is Mips32r2. 1631 // Eliminate redundant mfc1 and mtc1 instructions. 1632 unsigned LoIdx = 0, HiIdx = 1; 1633 1634 if (!isLittle) 1635 std::swap(LoIdx, HiIdx); 1636 1637 DebugLoc dl = Op.getDebugLoc(); 1638 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1639 Op.getOperand(0), 1640 DAG.getConstant(LoIdx, MVT::i32)); 1641 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1642 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1643 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1644 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1645 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1646 DAG.getConstant(0x7fffffff, MVT::i32)); 1647 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1648 DAG.getConstant(0x80000000, MVT::i32)); 1649 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1650 1651 if (!isLittle) 1652 std::swap(Word0, Word1); 1653 1654 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1655} 1656 1657SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) 1658 const { 1659 EVT Ty = Op.getValueType(); 1660 1661 assert(Ty == MVT::f32 || Ty == MVT::f64); 1662 1663 if (Ty == MVT::f32) 1664 return LowerFCOPYSIGN32(Op, DAG); 1665 else 1666 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); 1667} 1668 1669SDValue MipsTargetLowering:: 1670LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1671 // check the depth 1672 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1673 "Frame address can only be determined for current frame."); 1674 1675 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1676 MFI->setFrameAddressIsTaken(true); 1677 EVT VT = Op.getValueType(); 1678 DebugLoc dl = Op.getDebugLoc(); 1679 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT); 1680 return FrameAddr; 1681} 1682 1683// TODO: set SType according to the desired memory barrier behavior. 1684SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op, 1685 SelectionDAG& DAG) const { 1686 unsigned SType = 0; 1687 DebugLoc dl = Op.getDebugLoc(); 1688 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1689 DAG.getConstant(SType, MVT::i32)); 1690} 1691 1692SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1693 SelectionDAG& DAG) const { 1694 // FIXME: Need pseudo-fence for 'singlethread' fences 1695 // FIXME: Set SType for weaker fences where supported/appropriate. 1696 unsigned SType = 0; 1697 DebugLoc dl = Op.getDebugLoc(); 1698 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1699 DAG.getConstant(SType, MVT::i32)); 1700} 1701 1702//===----------------------------------------------------------------------===// 1703// Calling Convention Implementation 1704//===----------------------------------------------------------------------===// 1705 1706#include "MipsGenCallingConv.inc" 1707 1708//===----------------------------------------------------------------------===// 1709// TODO: Implement a generic logic using tblgen that can support this. 1710// Mips O32 ABI rules: 1711// --- 1712// i32 - Passed in A0, A1, A2, A3 and stack 1713// f32 - Only passed in f32 registers if no int reg has been used yet to hold 1714// an argument. Otherwise, passed in A1, A2, A3 and stack. 1715// f64 - Only passed in two aliased f32 registers if no int reg has been used 1716// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1717// not used, it must be shadowed. If only A3 is avaiable, shadow it and 1718// go to stack. 1719// 1720// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1721//===----------------------------------------------------------------------===// 1722 1723static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1724 MVT LocVT, CCValAssign::LocInfo LocInfo, 1725 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1726 1727 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1728 1729 static const unsigned IntRegs[] = { 1730 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1731 }; 1732 static const unsigned F32Regs[] = { 1733 Mips::F12, Mips::F14 1734 }; 1735 static const unsigned F64Regs[] = { 1736 Mips::D6, Mips::D7 1737 }; 1738 1739 // ByVal Args 1740 if (ArgFlags.isByVal()) { 1741 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1742 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1743 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1744 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1745 r < std::min(IntRegsSize, NextReg); ++r) 1746 State.AllocateReg(IntRegs[r]); 1747 return false; 1748 } 1749 1750 // Promote i8 and i16 1751 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1752 LocVT = MVT::i32; 1753 if (ArgFlags.isSExt()) 1754 LocInfo = CCValAssign::SExt; 1755 else if (ArgFlags.isZExt()) 1756 LocInfo = CCValAssign::ZExt; 1757 else 1758 LocInfo = CCValAssign::AExt; 1759 } 1760 1761 unsigned Reg; 1762 1763 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1764 // is true: function is vararg, argument is 3rd or higher, there is previous 1765 // argument which is not f32 or f64. 1766 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1767 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1768 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1769 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1770 1771 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1772 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1773 // If this is the first part of an i64 arg, 1774 // the allocated register must be either A0 or A2. 1775 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1776 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1777 LocVT = MVT::i32; 1778 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1779 // Allocate int register and shadow next int register. If first 1780 // available register is Mips::A1 or Mips::A3, shadow it too. 1781 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1782 if (Reg == Mips::A1 || Reg == Mips::A3) 1783 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1784 State.AllocateReg(IntRegs, IntRegsSize); 1785 LocVT = MVT::i32; 1786 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1787 // we are guaranteed to find an available float register 1788 if (ValVT == MVT::f32) { 1789 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1790 // Shadow int register 1791 State.AllocateReg(IntRegs, IntRegsSize); 1792 } else { 1793 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1794 // Shadow int registers 1795 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1796 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1797 State.AllocateReg(IntRegs, IntRegsSize); 1798 State.AllocateReg(IntRegs, IntRegsSize); 1799 } 1800 } else 1801 llvm_unreachable("Cannot handle this ValVT."); 1802 1803 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1804 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1805 1806 if (!Reg) 1807 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1808 else 1809 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1810 1811 return false; // CC must always match 1812} 1813 1814//===----------------------------------------------------------------------===// 1815// Call Calling Convention Implementation 1816//===----------------------------------------------------------------------===// 1817 1818static const unsigned O32IntRegsSize = 4; 1819 1820static const unsigned O32IntRegs[] = { 1821 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1822}; 1823 1824// Return next O32 integer argument register. 1825static unsigned getNextIntArgReg(unsigned Reg) { 1826 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 1827 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 1828} 1829 1830// Write ByVal Arg to arg registers and stack. 1831static void 1832WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 1833 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1834 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1835 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1836 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1837 MVT PtrType, bool isLittle) { 1838 unsigned LocMemOffset = VA.getLocMemOffset(); 1839 unsigned Offset = 0; 1840 uint32_t RemainingSize = Flags.getByValSize(); 1841 unsigned ByValAlign = Flags.getByValAlign(); 1842 1843 // Copy the first 4 words of byval arg to registers A0 - A3. 1844 // FIXME: Use a stricter alignment if it enables better optimization in passes 1845 // run later. 1846 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 1847 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 1848 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1849 DAG.getConstant(Offset, MVT::i32)); 1850 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 1851 MachinePointerInfo(), 1852 false, false, std::min(ByValAlign, 1853 (unsigned )4)); 1854 MemOpChains.push_back(LoadVal.getValue(1)); 1855 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1856 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1857 } 1858 1859 if (RemainingSize == 0) 1860 return; 1861 1862 // If there still is a register available for argument passing, write the 1863 // remaining part of the structure to it using subword loads and shifts. 1864 if (LocMemOffset < 4 * 4) { 1865 assert(RemainingSize <= 3 && RemainingSize >= 1 && 1866 "There must be one to three bytes remaining."); 1867 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 1868 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1869 DAG.getConstant(Offset, MVT::i32)); 1870 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 1871 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1872 LoadPtr, MachinePointerInfo(), 1873 MVT::getIntegerVT(LoadSize * 8), false, 1874 false, Alignment); 1875 MemOpChains.push_back(LoadVal.getValue(1)); 1876 1877 // If target is big endian, shift it to the most significant half-word or 1878 // byte. 1879 if (!isLittle) 1880 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 1881 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 1882 1883 Offset += LoadSize; 1884 RemainingSize -= LoadSize; 1885 1886 // Read second subword if necessary. 1887 if (RemainingSize != 0) { 1888 assert(RemainingSize == 1 && "There must be one byte remaining."); 1889 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1890 DAG.getConstant(Offset, MVT::i32)); 1891 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 1892 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1893 LoadPtr, MachinePointerInfo(), 1894 MVT::i8, false, false, Alignment); 1895 MemOpChains.push_back(Subword.getValue(1)); 1896 // Insert the loaded byte to LoadVal. 1897 // FIXME: Use INS if supported by target. 1898 unsigned ShiftAmt = isLittle ? 16 : 8; 1899 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 1900 DAG.getConstant(ShiftAmt, MVT::i32)); 1901 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 1902 } 1903 1904 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1905 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1906 return; 1907 } 1908 1909 // Create a fixed object on stack at offset LocMemOffset and copy 1910 // remaining part of byval arg to it using memcpy. 1911 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1912 DAG.getConstant(Offset, MVT::i32)); 1913 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true); 1914 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 1915 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 1916 DAG.getConstant(RemainingSize, MVT::i32), 1917 std::min(ByValAlign, (unsigned)4), 1918 /*isVolatile=*/false, /*AlwaysInline=*/false, 1919 MachinePointerInfo(0), MachinePointerInfo(0)); 1920} 1921 1922/// LowerCall - functions arguments are copied from virtual regs to 1923/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1924/// TODO: isTailCall. 1925SDValue 1926MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee, 1927 CallingConv::ID CallConv, bool isVarArg, 1928 bool &isTailCall, 1929 const SmallVectorImpl<ISD::OutputArg> &Outs, 1930 const SmallVectorImpl<SDValue> &OutVals, 1931 const SmallVectorImpl<ISD::InputArg> &Ins, 1932 DebugLoc dl, SelectionDAG &DAG, 1933 SmallVectorImpl<SDValue> &InVals) const { 1934 // MIPs target does not yet support tail call optimization. 1935 isTailCall = false; 1936 1937 MachineFunction &MF = DAG.getMachineFunction(); 1938 MachineFrameInfo *MFI = MF.getFrameInfo(); 1939 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1940 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1941 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1942 1943 // Analyze operands of the call, assigning locations to each operand. 1944 SmallVector<CCValAssign, 16> ArgLocs; 1945 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1946 getTargetMachine(), ArgLocs, *DAG.getContext()); 1947 1948 if (Subtarget->isABI_O32()) 1949 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1950 else 1951 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1952 1953 // Get a count of how many bytes are to be pushed on the stack. 1954 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1955 1956 // Chain is the output chain of the last Load/Store or CopyToReg node. 1957 // ByValChain is the output chain of the last Memcpy node created for copying 1958 // byval arguments to the stack. 1959 SDValue Chain, CallSeqStart, ByValChain; 1960 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 1961 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal); 1962 ByValChain = InChain; 1963 1964 // If this is the first call, create a stack frame object that points to 1965 // a location to which .cprestore saves $gp. 1966 if (IsPIC && !MipsFI->getGPFI()) 1967 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1968 1969 // Get the frame index of the stack frame object that points to the location 1970 // of dynamically allocated area on the stack. 1971 int DynAllocFI = MipsFI->getDynAllocFI(); 1972 1973 // Update size of the maximum argument space. 1974 // For O32, a minimum of four words (16 bytes) of argument space is 1975 // allocated. 1976 if (Subtarget->isABI_O32()) 1977 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1978 1979 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1980 1981 if (MaxCallFrameSize < NextStackOffset) { 1982 MipsFI->setMaxCallFrameSize(NextStackOffset); 1983 1984 // Set the offsets relative to $sp of the $gp restore slot and dynamically 1985 // allocated stack space. These offsets must be aligned to a boundary 1986 // determined by the stack alignment of the ABI. 1987 unsigned StackAlignment = TFL->getStackAlignment(); 1988 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1989 StackAlignment * StackAlignment; 1990 1991 if (IsPIC) 1992 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 1993 1994 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 1995 } 1996 1997 // With EABI is it possible to have 16 args on registers. 1998 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1999 SmallVector<SDValue, 8> MemOpChains; 2000 2001 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 2002 2003 // Walk the register/memloc assignments, inserting copies/loads. 2004 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2005 SDValue Arg = OutVals[i]; 2006 CCValAssign &VA = ArgLocs[i]; 2007 2008 // Promote the value if needed. 2009 switch (VA.getLocInfo()) { 2010 default: llvm_unreachable("Unknown loc info!"); 2011 case CCValAssign::Full: 2012 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 2013 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 2014 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 2015 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 2016 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2017 Arg, DAG.getConstant(0, MVT::i32)); 2018 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2019 Arg, DAG.getConstant(1, MVT::i32)); 2020 if (!Subtarget->isLittle()) 2021 std::swap(Lo, Hi); 2022 unsigned LocRegLo = VA.getLocReg(); 2023 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2024 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2025 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2026 continue; 2027 } 2028 } 2029 break; 2030 case CCValAssign::SExt: 2031 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 2032 break; 2033 case CCValAssign::ZExt: 2034 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 2035 break; 2036 case CCValAssign::AExt: 2037 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 2038 break; 2039 } 2040 2041 // Arguments that can be passed on register must be kept at 2042 // RegsToPass vector 2043 if (VA.isRegLoc()) { 2044 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2045 continue; 2046 } 2047 2048 // Register can't get to this point... 2049 assert(VA.isMemLoc()); 2050 2051 // ByVal Arg. 2052 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2053 if (Flags.isByVal()) { 2054 assert(Subtarget->isABI_O32() && 2055 "No support for ByVal args by ABIs other than O32 yet."); 2056 assert(Flags.getByValSize() && 2057 "ByVal args of size 0 should have been ignored by front-end."); 2058 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, 2059 DAG, Arg, VA, Flags, getPointerTy(), Subtarget->isLittle()); 2060 continue; 2061 } 2062 2063 // Create the frame index object for this incoming parameter 2064 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2065 VA.getLocMemOffset(), true); 2066 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2067 2068 // emit ISD::STORE whichs stores the 2069 // parameter value to a stack Location 2070 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2071 MachinePointerInfo(), 2072 false, false, 0)); 2073 } 2074 2075 // Extend range of indices of frame objects for outgoing arguments that were 2076 // created during this function call. Skip this step if no such objects were 2077 // created. 2078 if (LastFI) 2079 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 2080 2081 // If a memcpy has been created to copy a byval arg to a stack, replace the 2082 // chain input of CallSeqStart with ByValChain. 2083 if (InChain != ByValChain) 2084 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain, 2085 NextStackOffsetVal); 2086 2087 // Transform all store nodes into one single node because all store 2088 // nodes are independent of each other. 2089 if (!MemOpChains.empty()) 2090 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2091 &MemOpChains[0], MemOpChains.size()); 2092 2093 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2094 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2095 // node so that legalize doesn't hack it. 2096 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2097 bool LoadSymAddr = false; 2098 SDValue CalleeLo; 2099 2100 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2101 if (IsPIC && G->getGlobal()->hasInternalLinkage()) { 2102 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2103 getPointerTy(), 0,MipsII:: MO_GOT); 2104 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2105 0, MipsII::MO_ABS_LO); 2106 } else { 2107 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2108 getPointerTy(), 0, OpFlag); 2109 } 2110 2111 LoadSymAddr = true; 2112 } 2113 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2114 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 2115 getPointerTy(), OpFlag); 2116 LoadSymAddr = true; 2117 } 2118 2119 SDValue InFlag; 2120 2121 // Create nodes that load address of callee and copy it to T9 2122 if (IsPIC) { 2123 if (LoadSymAddr) { 2124 // Load callee address 2125 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee); 2126 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee, 2127 MachinePointerInfo::getGOT(), 2128 false, false, 0); 2129 2130 // Use GOT+LO if callee has internal linkage. 2131 if (CalleeLo.getNode()) { 2132 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo); 2133 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo); 2134 } else 2135 Callee = LoadValue; 2136 } 2137 2138 // copy to T9 2139 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0)); 2140 InFlag = Chain.getValue(1); 2141 Callee = DAG.getRegister(Mips::T9, MVT::i32); 2142 } 2143 2144 // Build a sequence of copy-to-reg nodes chained together with token 2145 // chain and flag operands which copy the outgoing args into registers. 2146 // The InFlag in necessary since all emitted instructions must be 2147 // stuck together. 2148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2149 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2150 RegsToPass[i].second, InFlag); 2151 InFlag = Chain.getValue(1); 2152 } 2153 2154 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2155 // = Chain, Callee, Reg#1, Reg#2, ... 2156 // 2157 // Returns a chain & a flag for retval copy to use. 2158 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2159 SmallVector<SDValue, 8> Ops; 2160 Ops.push_back(Chain); 2161 Ops.push_back(Callee); 2162 2163 // Add argument registers to the end of the list so that they are 2164 // known live into the call. 2165 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2166 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2167 RegsToPass[i].second.getValueType())); 2168 2169 if (InFlag.getNode()) 2170 Ops.push_back(InFlag); 2171 2172 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2173 InFlag = Chain.getValue(1); 2174 2175 // Create the CALLSEQ_END node. 2176 Chain = DAG.getCALLSEQ_END(Chain, 2177 DAG.getIntPtrConstant(NextStackOffset, true), 2178 DAG.getIntPtrConstant(0, true), InFlag); 2179 InFlag = Chain.getValue(1); 2180 2181 // Handle result values, copying them out of physregs into vregs that we 2182 // return. 2183 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2184 Ins, dl, DAG, InVals); 2185} 2186 2187/// LowerCallResult - Lower the result values of a call into the 2188/// appropriate copies out of appropriate physical registers. 2189SDValue 2190MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2191 CallingConv::ID CallConv, bool isVarArg, 2192 const SmallVectorImpl<ISD::InputArg> &Ins, 2193 DebugLoc dl, SelectionDAG &DAG, 2194 SmallVectorImpl<SDValue> &InVals) const { 2195 // Assign locations to each value returned by this call. 2196 SmallVector<CCValAssign, 16> RVLocs; 2197 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2198 getTargetMachine(), RVLocs, *DAG.getContext()); 2199 2200 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2201 2202 // Copy all of the result registers out of their specified physreg. 2203 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2204 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2205 RVLocs[i].getValVT(), InFlag).getValue(1); 2206 InFlag = Chain.getValue(2); 2207 InVals.push_back(Chain.getValue(0)); 2208 } 2209 2210 return Chain; 2211} 2212 2213//===----------------------------------------------------------------------===// 2214// Formal Arguments Calling Convention Implementation 2215//===----------------------------------------------------------------------===// 2216static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2217 std::vector<SDValue>& OutChains, 2218 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2219 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 2220 unsigned LocMem = VA.getLocMemOffset(); 2221 unsigned FirstWord = LocMem / 4; 2222 2223 // copy register A0 - A3 to frame object 2224 for (unsigned i = 0; i < NumWords; ++i) { 2225 unsigned CurWord = FirstWord + i; 2226 if (CurWord >= O32IntRegsSize) 2227 break; 2228 2229 unsigned SrcReg = O32IntRegs[CurWord]; 2230 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2231 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2232 DAG.getConstant(i * 4, MVT::i32)); 2233 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2234 StorePtr, MachinePointerInfo(), false, 2235 false, 0); 2236 OutChains.push_back(Store); 2237 } 2238} 2239 2240/// LowerFormalArguments - transform physical registers into virtual registers 2241/// and generate load operations for arguments places on the stack. 2242SDValue 2243MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2244 CallingConv::ID CallConv, 2245 bool isVarArg, 2246 const SmallVectorImpl<ISD::InputArg> 2247 &Ins, 2248 DebugLoc dl, SelectionDAG &DAG, 2249 SmallVectorImpl<SDValue> &InVals) 2250 const { 2251 MachineFunction &MF = DAG.getMachineFunction(); 2252 MachineFrameInfo *MFI = MF.getFrameInfo(); 2253 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2254 2255 MipsFI->setVarArgsFrameIndex(0); 2256 2257 // Used with vargs to acumulate store chains. 2258 std::vector<SDValue> OutChains; 2259 2260 // Assign locations to all of the incoming arguments. 2261 SmallVector<CCValAssign, 16> ArgLocs; 2262 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2263 getTargetMachine(), ArgLocs, *DAG.getContext()); 2264 2265 if (Subtarget->isABI_O32()) 2266 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2267 else 2268 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2269 2270 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2271 2272 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2273 CCValAssign &VA = ArgLocs[i]; 2274 2275 // Arguments stored on registers 2276 if (VA.isRegLoc()) { 2277 EVT RegVT = VA.getLocVT(); 2278 unsigned ArgReg = VA.getLocReg(); 2279 TargetRegisterClass *RC = 0; 2280 2281 if (RegVT == MVT::i32) 2282 RC = Mips::CPURegsRegisterClass; 2283 else if (RegVT == MVT::i64) 2284 RC = Mips::CPU64RegsRegisterClass; 2285 else if (RegVT == MVT::f32) 2286 RC = Mips::FGR32RegisterClass; 2287 else if (RegVT == MVT::f64) 2288 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass; 2289 else 2290 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2291 2292 // Transform the arguments stored on 2293 // physical registers into virtual ones 2294 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2295 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2296 2297 // If this is an 8 or 16-bit value, it has been passed promoted 2298 // to 32 bits. Insert an assert[sz]ext to capture this, then 2299 // truncate to the right size. 2300 if (VA.getLocInfo() != CCValAssign::Full) { 2301 unsigned Opcode = 0; 2302 if (VA.getLocInfo() == CCValAssign::SExt) 2303 Opcode = ISD::AssertSext; 2304 else if (VA.getLocInfo() == CCValAssign::ZExt) 2305 Opcode = ISD::AssertZext; 2306 if (Opcode) 2307 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2308 DAG.getValueType(VA.getValVT())); 2309 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2310 } 2311 2312 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 2313 if (Subtarget->isABI_O32()) { 2314 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 2315 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue); 2316 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 2317 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2318 getNextIntArgReg(ArgReg), RC); 2319 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2320 if (!Subtarget->isLittle()) 2321 std::swap(ArgValue, ArgValue2); 2322 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2323 ArgValue, ArgValue2); 2324 } 2325 } 2326 2327 InVals.push_back(ArgValue); 2328 } else { // VA.isRegLoc() 2329 2330 // sanity check 2331 assert(VA.isMemLoc()); 2332 2333 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2334 2335 if (Flags.isByVal()) { 2336 assert(Subtarget->isABI_O32() && 2337 "No support for ByVal args by ABIs other than O32 yet."); 2338 assert(Flags.getByValSize() && 2339 "ByVal args of size 0 should have been ignored by front-end."); 2340 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2341 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2342 true); 2343 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2344 InVals.push_back(FIN); 2345 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2346 2347 continue; 2348 } 2349 2350 // The stack pointer offset is relative to the caller stack frame. 2351 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2352 VA.getLocMemOffset(), true); 2353 2354 // Create load nodes to retrieve arguments from the stack 2355 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2356 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2357 MachinePointerInfo::getFixedStack(LastFI), 2358 false, false, 0)); 2359 } 2360 } 2361 2362 // The mips ABIs for returning structs by value requires that we copy 2363 // the sret argument into $v0 for the return. Save the argument into 2364 // a virtual register so that we can access it from the return points. 2365 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2366 unsigned Reg = MipsFI->getSRetReturnReg(); 2367 if (!Reg) { 2368 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2369 MipsFI->setSRetReturnReg(Reg); 2370 } 2371 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2372 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2373 } 2374 2375 if (isVarArg && Subtarget->isABI_O32()) { 2376 // Record the frame index of the first variable argument 2377 // which is a value necessary to VASTART. 2378 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2379 assert(NextStackOffset % 4 == 0 && 2380 "NextStackOffset must be aligned to 4-byte boundaries."); 2381 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2382 MipsFI->setVarArgsFrameIndex(LastFI); 2383 2384 // If NextStackOffset is smaller than o32's 16-byte reserved argument area, 2385 // copy the integer registers that have not been used for argument passing 2386 // to the caller's stack frame. 2387 for (; NextStackOffset < 16; NextStackOffset += 4) { 2388 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 2389 unsigned Idx = NextStackOffset / 4; 2390 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 2391 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 2392 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2393 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2394 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2395 MachinePointerInfo(), 2396 false, false, 0)); 2397 } 2398 } 2399 2400 MipsFI->setLastInArgFI(LastFI); 2401 2402 // All stores are grouped in one node to allow the matching between 2403 // the size of Ins and InVals. This only happens when on varg functions 2404 if (!OutChains.empty()) { 2405 OutChains.push_back(Chain); 2406 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2407 &OutChains[0], OutChains.size()); 2408 } 2409 2410 return Chain; 2411} 2412 2413//===----------------------------------------------------------------------===// 2414// Return Value Calling Convention Implementation 2415//===----------------------------------------------------------------------===// 2416 2417SDValue 2418MipsTargetLowering::LowerReturn(SDValue Chain, 2419 CallingConv::ID CallConv, bool isVarArg, 2420 const SmallVectorImpl<ISD::OutputArg> &Outs, 2421 const SmallVectorImpl<SDValue> &OutVals, 2422 DebugLoc dl, SelectionDAG &DAG) const { 2423 2424 // CCValAssign - represent the assignment of 2425 // the return value to a location 2426 SmallVector<CCValAssign, 16> RVLocs; 2427 2428 // CCState - Info about the registers and stack slot. 2429 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2430 getTargetMachine(), RVLocs, *DAG.getContext()); 2431 2432 // Analize return values. 2433 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2434 2435 // If this is the first return lowered for this function, add 2436 // the regs to the liveout set for the function. 2437 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2438 for (unsigned i = 0; i != RVLocs.size(); ++i) 2439 if (RVLocs[i].isRegLoc()) 2440 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2441 } 2442 2443 SDValue Flag; 2444 2445 // Copy the result values into the output registers. 2446 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2447 CCValAssign &VA = RVLocs[i]; 2448 assert(VA.isRegLoc() && "Can only return in registers!"); 2449 2450 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 2451 OutVals[i], Flag); 2452 2453 // guarantee that all emitted copies are 2454 // stuck together, avoiding something bad 2455 Flag = Chain.getValue(1); 2456 } 2457 2458 // The mips ABIs for returning structs by value requires that we copy 2459 // the sret argument into $v0 for the return. We saved the argument into 2460 // a virtual register in the entry block, so now we copy the value out 2461 // and into $v0. 2462 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2463 MachineFunction &MF = DAG.getMachineFunction(); 2464 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2465 unsigned Reg = MipsFI->getSRetReturnReg(); 2466 2467 if (!Reg) 2468 llvm_unreachable("sret virtual register not created in the entry block"); 2469 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2470 2471 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2472 Flag = Chain.getValue(1); 2473 } 2474 2475 // Return on Mips is always a "jr $ra" 2476 if (Flag.getNode()) 2477 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2478 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2479 else // Return Void 2480 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2481 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2482} 2483 2484//===----------------------------------------------------------------------===// 2485// Mips Inline Assembly Support 2486//===----------------------------------------------------------------------===// 2487 2488/// getConstraintType - Given a constraint letter, return the type of 2489/// constraint it is for this target. 2490MipsTargetLowering::ConstraintType MipsTargetLowering:: 2491getConstraintType(const std::string &Constraint) const 2492{ 2493 // Mips specific constrainy 2494 // GCC config/mips/constraints.md 2495 // 2496 // 'd' : An address register. Equivalent to r 2497 // unless generating MIPS16 code. 2498 // 'y' : Equivalent to r; retained for 2499 // backwards compatibility. 2500 // 'f' : Floating Point registers. 2501 if (Constraint.size() == 1) { 2502 switch (Constraint[0]) { 2503 default : break; 2504 case 'd': 2505 case 'y': 2506 case 'f': 2507 return C_RegisterClass; 2508 break; 2509 } 2510 } 2511 return TargetLowering::getConstraintType(Constraint); 2512} 2513 2514/// Examine constraint type and operand type and determine a weight value. 2515/// This object must already have been set up with the operand type 2516/// and the current alternative constraint selected. 2517TargetLowering::ConstraintWeight 2518MipsTargetLowering::getSingleConstraintMatchWeight( 2519 AsmOperandInfo &info, const char *constraint) const { 2520 ConstraintWeight weight = CW_Invalid; 2521 Value *CallOperandVal = info.CallOperandVal; 2522 // If we don't have a value, we can't do a match, 2523 // but allow it at the lowest weight. 2524 if (CallOperandVal == NULL) 2525 return CW_Default; 2526 Type *type = CallOperandVal->getType(); 2527 // Look at the constraint type. 2528 switch (*constraint) { 2529 default: 2530 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2531 break; 2532 case 'd': 2533 case 'y': 2534 if (type->isIntegerTy()) 2535 weight = CW_Register; 2536 break; 2537 case 'f': 2538 if (type->isFloatTy()) 2539 weight = CW_Register; 2540 break; 2541 } 2542 return weight; 2543} 2544 2545/// Given a register class constraint, like 'r', if this corresponds directly 2546/// to an LLVM register class, return a register of 0 and the register class 2547/// pointer. 2548std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2549getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2550{ 2551 if (Constraint.size() == 1) { 2552 switch (Constraint[0]) { 2553 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2554 case 'y': // Same as 'r'. Exists for compatibility. 2555 case 'r': 2556 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2557 case 'f': 2558 if (VT == MVT::f32) 2559 return std::make_pair(0U, Mips::FGR32RegisterClass); 2560 if (VT == MVT::f64) 2561 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 2562 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2563 break; 2564 } 2565 } 2566 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2567} 2568 2569bool 2570MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2571 // The Mips target isn't yet aware of offsets. 2572 return false; 2573} 2574 2575bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2576 if (VT != MVT::f32 && VT != MVT::f64) 2577 return false; 2578 if (Imm.isNegZero()) 2579 return false; 2580 return Imm.isZero(); 2581} 2582