Searched refs:DefIdx (Results 1 - 25 of 52) sorted by relevance

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/external/llvm/include/llvm/MC/
H A DMCInstrItineraries.h183 /// instruction of itinerary class DefClass, operand index DefIdx can be
186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, argument
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
192 if (Forwardings[FirstDefIdx + DefIdx] == 0)
200 return Forwardings[FirstDefIdx + DefIdx] ==
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx, argument
212 int DefCycle = getOperandCycle(DefClass, DefIdx);
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
H A DMCSubtargetInfo.h129 unsigned DefIdx) const {
130 assert(DefIdx < SC->NumWriteLatencyEntries &&
131 "MachineModel does not specify a WriteResource for DefIdx");
133 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
/external/swiftshader/third_party/LLVM/include/llvm/MC/
H A DMCInstrItineraries.h197 /// index DefIdx can be bypassed when it's read by an instruction of
199 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, argument
203 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
205 if (Forwardings[FirstDefIdx + DefIdx] == 0)
213 return Forwardings[FirstDefIdx + DefIdx] ==
220 int getOperandLatency(unsigned DefClass, unsigned DefIdx, argument
225 int DefCycle = getOperandCycle(DefClass, DefIdx);
235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp128 unsigned DefIdx = 0; local
132 ++DefIdx;
134 return DefIdx;
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); local
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
192 STI->getWriteLatencyEntry(SCDesc, DefIdx);
208 // If DefIdx does not exist in the model (e.g. implicit defs), then return
214 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
228 for (unsigned DefIdx
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H A DPeepholeOptimizer.cpp296 unsigned DefIdx;
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
358 DefIdx = MRI.def_begin(Reg).getOperandNo();
363 /// the pair \p MI, \p DefIdx.
369 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
375 assert(DefIdx < Def->getDesc().getNumDefs() &&
376 Def->getOperand(DefIdx).isReg() && "Invalid definition");
377 Reg = Def->getOperand(DefIdx)
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H A DTargetInstrInfo.cpp982 SDNode *DefNode, unsigned DefIdx,
992 return ItinData->getOperandCycle(DefClass, DefIdx);
994 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1056 unsigned DefIdx) const {
1062 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1070 unsigned DefIdx,
1075 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1096 unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const {
1106 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx);
1109 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
981 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
1068 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
1094 computeOperandLatency( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
1123 getRegSequenceInputs( const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const argument
1148 getExtractSubregInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const argument
1171 getInsertSubregInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const argument
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H A DLiveRangeCalc.cpp46 SlotIndex DefIdx = local
50 LR.createDeadDef(DefIdx, Alloc);
195 unsigned DefIdx; local
198 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
201 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
/external/swiftshader/third_party/LLVM/lib/Target/
H A DTargetInstrInfo.cpp66 const MachineInstr *DefMI, unsigned DefIdx,
73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
78 SDNode *DefNode, unsigned DefIdx,
88 return ItinData->getOperandCycle(DefClass, DefIdx);
90 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
115 unsigned DefIdx) const {
120 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
65 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
77 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h42 /// and \p DefIdx.
51 /// with the pair \p MI, \p DefIdx. False otherwise.
55 const MachineInstr &MI, unsigned DefIdx,
59 /// and \p DefIdx.
65 /// with the pair \p MI, \p DefIdx. False otherwise.
68 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
72 /// and \p DefIdx.
80 /// with the pair \p MI, \p DefIdx. False otherwise.
84 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
282 const MachineInstr &DefMI, unsigned DefIdx,
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H A DARMBaseInstrInfo.cpp3187 unsigned DefIdx, unsigned DefAlign) const {
3188 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3191 return ItinData->getOperandCycle(DefClass, DefIdx);
3228 unsigned DefIdx, unsigned DefAlign) const {
3229 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3232 return ItinData->getOperandCycle(DefClass, DefIdx);
3331 unsigned DefIdx, unsigned DefAlign,
3337 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3338 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3347 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3184 getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
3225 getLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
3329 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
3440 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
3673 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
3709 getOperandLatencyImpl( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const argument
3770 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
4071 hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h125 unsigned DefIdx; member in class:llvm::ScheduleDAGSDNodes::RegDefIter
143 return DefIdx-1;
H A DScheduleDAGSDNodes.cpp507 DefIdx = 0;
513 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
521 for (;DefIdx < NodeNumDefs; ++DefIdx) {
522 if (!Node->hasAnyUseOfValue(DefIdx))
524 ValueType = Node->getValueType(DefIdx);
525 ++DefIdx;
587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); local
591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMBaseInstrInfo.h209 const MachineInstr *DefMI, unsigned DefIdx,
213 SDNode *DefNode, unsigned DefIdx,
225 unsigned DefIdx, unsigned DefAlign) const;
229 unsigned DefIdx, unsigned DefAlign) const;
240 unsigned DefIdx, unsigned DefAlign,
252 const MachineInstr *DefMI, unsigned DefIdx,
255 const MachineInstr *DefMI, unsigned DefIdx) const;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h131 unsigned DefIdx; member in class:llvm::ScheduleDAGSDNodes::RegDefIter
149 return DefIdx-1;
H A DScheduleDAGSDNodes.cpp554 DefIdx = 0;
560 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
568 for (;DefIdx < NodeNumDefs; ++DefIdx) {
569 if (!Node->hasAnyUseOfValue(DefIdx))
571 ValueType = Node->getSimpleValueType(DefIdx);
572 ++DefIdx;
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h374 /// and \p DefIdx.
383 /// with the pair \p MI, \p DefIdx. False otherwise.
391 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
395 /// and \p DefIdx.
401 /// with the pair \p MI, \p DefIdx. False otherwise.
409 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
413 /// and \p DefIdx.
421 /// with the pair \p MI, \p DefIdx. False otherwise.
429 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
928 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx
933 getRegSequenceLikeInputs( const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const argument
947 getExtractSubregLikeInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const argument
962 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const argument
1280 hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h119 const MachineInstr &DefMI, unsigned DefIdx,
123 SDNode *DefNode, unsigned DefIdx,
125 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
131 unsigned DefIdx) const override {
H A DPPCVSXSwapRemoval.cpp617 int DefIdx = SwapMap[DefMI]; local
618 (void)EC->unionSets(SwapVector[DefIdx].VSEId,
621 DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId,
696 int DefIdx = SwapMap[DefMI]; local
698 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
699 SwapVector[DefIdx].IsStore) {
705 DEBUG(dbgs() << " def " << DefIdx << ": ");
771 int DefIdx = SwapMap[DefMI]; local
772 SwapVector[DefIdx]
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DLiveRangeEdit.cpp122 SlotIndex DefIdx;
124 DefIdx = lis.getInstructionIndex(RM.OrigMI);
126 DefIdx = RM.ParentVNI->def;
127 RM.OrigMI = lis.getInstructionFromIndex(DefIdx);
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
H A DRegisterCoalescer.cpp659 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); local
660 assert(DefIdx != -1);
662 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
768 SlotIndex DefIdx = UseIdx.getDefIndex(); local
769 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
772 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
773 assert(DVNI->def == DefIdx);
1016 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getDefIndex(); local
1017 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
1018 if (DefIdx !
1026 SlotIndex DefIdx = LIS->getInstructionIndex(CopyMI).getDefIndex(); local
1939 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getDefIndex(); local
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H A DScheduleDAGInstrs.cpp600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); local
601 if (DefIdx != -1) {
602 const MachineOperand &MO = DefMI->getOperand(DefIdx);
604 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
625 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
634 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h184 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
/external/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp203 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
204 DefIdx != DefEnd; ++DefIdx) {
207 DefIdx);
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp205 unsigned DefIdx = 0; local
209 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
210 IsTiedToChangedOp = OpChanged[DefIdx];
296 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetInstrInfo.h644 const MachineInstr *DefMI, unsigned DefIdx,
648 SDNode *DefNode, unsigned DefIdx,
673 const MachineInstr *DefMI, unsigned DefIdx,
682 const MachineInstr *DefMI, unsigned DefIdx) const;
671 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument

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