| /external/swiftshader/third_party/LLVM/lib/Target/ |
| H A D | TargetFrameLowering.cpp | 37 int FI, unsigned &FrameReg) const {
43 FrameReg = RI->getFrameRegister(MF);
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16RegisterInfo.cpp | 100 unsigned FrameReg; local
103 FrameReg = Mips::SP;
107 FrameReg = Mips::S0;
111 FrameReg = MI.getOperand(OpNo+2).getReg();
113 FrameReg = Mips::SP;
134 !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
140 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
144 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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| H A D | MipsSERegisterInfo.cpp | 135 unsigned FrameReg; local
139 FrameReg = ABI.GetStackPtr();
142 FrameReg = ABI.GetBasePtr();
144 FrameReg = getFrameRegister(MF);
146 FrameReg = ABI.GetStackPtr();
148 FrameReg = getFrameRegister(MF);
187 .addReg(FrameReg)
190 FrameReg = Reg;
204 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
207 FrameReg
[all...] |
| H A D | MipsSEFrameLowering.h | 31 unsigned &FrameReg) const override;
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUFrameLowering.h | 37 unsigned &FrameReg) const override;
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| H A D | AMDGPUFrameLowering.cpp | 77 unsigned &FrameReg) const {
82 // Fill in FrameReg output argument.
83 FrameReg = RI->getFrameRegister(MF);
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| /external/llvm/lib/Target/BPF/ |
| H A D | BPFRegisterInfo.cpp | 59 unsigned FrameReg = getFrameRegister(MF);
67 MI.getOperand(i).ChangeToRegister(FrameReg, false);
88 .addReg(FrameReg);
96 MI.getOperand(i).ChangeToRegister(FrameReg, false);
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| /external/llvm/lib/CodeGen/ |
| H A D | TargetFrameLoweringImpl.cpp | 39 /// (in output arg FrameReg). This is the default implementation which
42 int FI, unsigned &FrameReg) const {
49 FrameReg = RI->getFrameRegister(MF);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.h | 42 unsigned &FrameReg) const override;
44 unsigned &FrameReg,
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| H A D | AArch64RegisterInfo.cpp | 376 unsigned FrameReg; local
382 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
385 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
391 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
392 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
403 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMFrameLowering.h | 53 unsigned &FrameReg) const;
56 unsigned &FrameReg, int SPAdj) const;
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| H A D | Thumb1RegisterInfo.cpp | 387 unsigned FrameReg, int &Offset,
402 if (FrameReg != ARM::SP) {
416 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
431 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
434 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
446 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
460 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
462 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
477 MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
486 unsigned NumBits = (FrameReg
[all...] |
| H A D | Thumb1RegisterInfo.h | 55 unsigned FrameReg, int &Offset,
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| /external/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 352 unsigned FrameReg, int &Offset,
368 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
378 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
391 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
397 if (NewOpc != Opcode && FrameReg != ARM::SP)
512 unsigned FrameReg = ARM::SP;
522 FrameReg = getFrameRegister(MF);
525 FrameReg = BasePtr;
533 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
545 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, fals
[all...] |
| H A D | ARMFrameLowering.h | 50 unsigned &FrameReg) const override;
52 unsigned &FrameReg, int SPAdj) const;
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| H A D | ThumbRegisterInfo.h | 51 unsigned FrameReg, int &Offset,
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| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiRegisterInfo.cpp | 157 unsigned FrameReg = getFrameRegister(MF); local
160 FrameReg = getBaseRegister();
162 FrameReg = Lanai::SP;
198 // Reg = FrameReg OP Reg
203 .addReg(FrameReg)
221 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
239 .addReg(FrameReg)
243 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.cpp | 173 unsigned FrameReg; local
175 Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg);
187 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
188 replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg);
199 .addReg(FrameReg).addImm(0);
200 replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg);
208 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
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| H A D | SparcFrameLowering.h | 43 unsigned &FrameReg) const override;
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 64 unsigned Reg, unsigned FrameReg, int Offset ) {
72 .addReg(FrameReg)
79 .addReg(FrameReg)
85 .addReg(FrameReg)
95 unsigned Reg, unsigned FrameReg,
108 .addReg(FrameReg)
115 .addReg(FrameReg)
121 .addReg(FrameReg)
289 unsigned FrameReg = getFrameRegister(MF); local
293 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, fals
62 InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset ) argument
93 InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS ) argument
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 198 unsigned FrameReg = getFrameRegister(MF); local
202 MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
240 .addReg(FrameReg)
246 .addReg(FrameReg)
251 .addReg(FrameReg)
261 .addReg(FrameReg)
267 .addReg(FrameReg)
272 .addReg(FrameReg)
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| /external/llvm/include/llvm/Target/ |
| H A D | TargetFrameLowering.h | 245 /// returned directly, and the base register is returned via FrameReg.
247 unsigned &FrameReg) const;
251 /// FrameReg. This is generally used for emitting statepoint or EH tables that
256 unsigned &FrameReg,
259 return getFrameIndexReference(MF, FI, FrameReg);
255 getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, unsigned &FrameReg, bool IgnoreSPUpdates) const argument
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| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmInstrumentation.cpp | 504 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out); local
505 if (FrameReg == X86::NoRegister)
506 return FrameReg;
507 return getX86SubSuperRegister(FrameReg, 32);
537 unsigned FrameReg = GetFrameReg(Ctx, Out); variable
538 if (MRI && FrameReg != X86::NoRegister) {
540 if (FrameReg == X86::ESP) {
547 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg));
572 unsigned FrameReg = GetFrameReg(Ctx, Out); variable
573 if (Ctx.getRegisterInfo() && FrameReg !
762 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out); local
795 unsigned FrameReg = GetFrameReg(Ctx, Out); variable
832 unsigned FrameReg = GetFrameReg(Ctx, Out); variable
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.h | 47 unsigned &FrameReg) const override;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| H A D | MipsRegisterInfo.cpp | 284 unsigned FrameReg;
288 FrameReg = Mips::SP;
290 FrameReg = getFrameRegister(MF);
322 BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
324 FrameReg = Mips::AT;
330 MI.getOperand(i).ChangeToRegister(FrameReg, false);
|