Searched refs:Intr (Results 1 - 9 of 9) sorted by relevance
/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPromoteAlloca.cpp | 770 IntrinsicInst *Intr = dyn_cast<IntrinsicInst>(Call); local 771 if (!Intr) { 792 Builder.SetInsertPoint(Intr); 793 switch (Intr->getIntrinsicID()) { 797 Intr->eraseFromParent(); 800 MemCpyInst *MemCpy = cast<MemCpyInst>(Intr); 804 Intr->eraseFromParent(); 808 MemMoveInst *MemMove = cast<MemMoveInst>(Intr); 812 Intr->eraseFromParent(); 816 MemSetInst *MemSet = cast<MemSetInst>(Intr); [all...] |
H A D | SIISelLowering.cpp | 1315 bool SITargetLowering::isCFIntrinsic(const SDNode *Intr) const { 1316 if (Intr->getOpcode() != ISD::INTRINSIC_W_CHAIN) 1319 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) { 1365 SDNode *Intr = BRCOND.getOperand(1).getNode(); local 1370 if (Intr->getOpcode() == ISD::SETCC) { 1372 SetCC = Intr; 1373 Intr = SetCC->getOperand(0).getNode(); 1381 if (!isCFIntrinsic(Intr)) { 1392 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr [all...] |
H A D | SIISelLowering.h | 72 bool isCFIntrinsic(const SDNode *Intr) const;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonOptimizeSZextends.cpp | 124 Value *Intr = Shl->getOperand(0); local 132 if (IntrinsicInst *I = dyn_cast<IntrinsicInst>(Intr)) {
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/external/clang/utils/TableGen/ |
H A D | NeonEmitter.cpp | 471 Intrinsic &Intr; member in class:__anon3371::Intrinsic::DagEmitter 475 DagEmitter(Intrinsic &Intr, StringRef CallPrefix) : argument 476 Intr(Intr), CallPrefix(CallPrefix) { 1497 Intrinsic &Callee = Intr.Emitter.getIntrinsic(N, Types); 1501 Intr.Dependencies.insert(&Callee); 1531 assert_with_loc(Intr.Variables.find(DI->getArgName(ArgIdx)) != 1532 Intr.Variables.end(), 1534 castToType = Intr.Variables[DI->getArgName(ArgIdx)].getType(); 1540 castToType = Intr [all...] |
/external/syslinux/gpxe/src/drivers/infiniband/ |
H A D | linda.h | 62 pseudo_bit_t Intr[1]; member in struct:QIB_7220_SendPbc_pb
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 2175 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { argument 2191 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); local 2192 switch (Intr) { 2239 return lowerMSALoadIntr(Op, DAG, Intr); 2243 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { argument 2259 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); local 2260 switch (Intr) { 2267 return lowerMSAStoreIntr(Op, DAG, Intr);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 10803 Intrinsic::ID Intr, IntrLD, IntrPerm; local 10806 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr : 10814 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld : 10824 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy); 10910 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr local 10912 if ((IID == Intr ||
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 1470 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops); local 1472 SDValue NewChain = SDValue(Intr.getNode(), 0); 1474 return Intr;
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