/external/vixl/test/aarch32/ |
H A D | test-assembler-cond-rd-memop-immediate-512-a32.cc | 1600 {{al, r0, r2, minus, 180, PostIndex}, 1603 "al r0 r2 minus 180 PostIndex", 1605 {{al, r7, r10, plus, 36, PostIndex}, 1608 "al r7 r10 plus 36 PostIndex", 1615 {{al, r0, r8, plus, 182, PostIndex}, 1618 "al r0 r8 plus 182 PostIndex", 1630 {{al, r11, r3, minus, 116, PostIndex}, 1633 "al r11 r3 minus 116 PostIndex", 1640 {{al, r7, r1, plus, 13, PostIndex}, 1643 "al r7 r1 plus 13 PostIndex", [all...] |
H A D | test-assembler-cond-rd-memop-rs-a32.cc | 1619 {{al, r9, r4, plus, r7, PostIndex}, 1622 "al r9 r4 plus r7 PostIndex", 1629 {{al, r5, r9, minus, r14, PostIndex}, 1632 "al r5 r9 minus r14 PostIndex", 1644 {{al, r14, r7, minus, r5, PostIndex}, 1647 "al r14 r7 minus r5 PostIndex", 1649 {{al, r1, r11, plus, r14, PostIndex}, 1652 "al r1 r11 plus r14 PostIndex", 1659 {{al, r1, r13, plus, r11, PostIndex}, 1662 "al r1 r13 plus r11 PostIndex", [all...] |
H A D | test-assembler-cond-rd-memop-immediate-8192-a32.cc | 1605 {{al, r7, r12, plus, 1804, PostIndex}, 1608 "al r7 r12 plus 1804 PostIndex", 1615 {{al, r0, r8, minus, 4, PostIndex}, 1618 "al r0 r8 minus 4 PostIndex", 1620 {{al, r14, r2, plus, 1635, PostIndex}, 1623 "al r14 r2 plus 1635 PostIndex", 1660 {{al, r13, r10, plus, 1459, PostIndex}, 1663 "al r13 r10 plus 1459 PostIndex", 1665 {{al, r11, r12, plus, 2490, PostIndex}, 1668 "al r11 r12 plus 2490 PostIndex", [all...] |
H A D | test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 1612 {{al, r13, r3, minus, r1, ROR, 31, PostIndex}, 1615 "al r13 r3 minus r1 ROR 31 PostIndex", 1617 {{al, r9, r7, minus, r1, LSL, 8, PostIndex}, 1620 "al r9 r7 minus r1 LSL 8 PostIndex", 1647 {{al, r0, r14, plus, r2, LSL, 10, PostIndex}, 1650 "al r0 r14 plus r2 LSL 10 PostIndex", 1657 {{al, r0, r4, minus, r12, LSL, 31, PostIndex}, 1660 "al r0 r4 minus r12 LSL 31 PostIndex", 1662 {{al, r11, r12, plus, r7, LSL, 25, PostIndex}, 1665 "al r11 r12 plus r7 LSL 25 PostIndex", [all...] |
H A D | test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 1612 {{al, r12, r11, minus, r8, LSR, 2, PostIndex}, 1615 "al r12 r11 minus r8 LSR 2 PostIndex", 1617 {{al, r9, r3, plus, r10, ASR, 28, PostIndex}, 1620 "al r9 r3 plus r10 ASR 28 PostIndex", 1627 {{al, r14, r11, minus, r2, ASR, 2, PostIndex}, 1630 "al r14 r11 minus r2 ASR 2 PostIndex", 1657 {{al, r0, r13, minus, r4, ASR, 26, PostIndex}, 1660 "al r0 r13 minus r4 ASR 26 PostIndex", 1667 {{al, r0, r4, minus, r8, ASR, 21, PostIndex}, 1670 "al r0 r4 minus r8 ASR 21 PostIndex", [all...] |
H A D | test-simulator-cond-rd-memop-immediate-512-a32.cc | 1330 {{al, r14, r7, plus, 211, PostIndex}, 1331 "al r14 r7 plus 211 PostIndex", 1335 {{al, r7, r11, plus, 202, PostIndex}, 1336 "al r7 r11 plus 202 PostIndex", 1340 {{al, r11, r3, plus, 175, PostIndex}, 1341 "al r11 r3 plus 175 PostIndex", 1345 {{al, r4, r8, plus, 129, PostIndex}, 1346 "al r4 r8 plus 129 PostIndex", 1350 {{al, r4, r7, plus, 71, PostIndex}, 1351 "al r4 r7 plus 71 PostIndex", [all...] |
H A D | test-simulator-cond-rd-memop-immediate-8192-a32.cc | 1330 {{al, r14, r11, plus, 1506, PostIndex}, 1331 "al r14 r11 plus 1506 PostIndex", 1335 {{al, r7, r14, plus, 3399, PostIndex}, 1336 "al r7 r14 plus 3399 PostIndex", 1340 {{al, r11, r6, plus, 2588, PostIndex}, 1341 "al r11 r6 plus 2588 PostIndex", 1345 {{al, r4, r9, plus, 2906, PostIndex}, 1346 "al r4 r9 plus 2906 PostIndex", 1350 {{al, r4, r8, plus, 1916, PostIndex}, 1351 "al r4 r8 plus 1916 PostIndex", [all...] |
H A D | test-simulator-cond-rd-memop-rs-a32.cc | 1337 {{al, r8, r11, plus, r4, PostIndex}, 1338 "al r8 r11 plus r4 PostIndex", 1342 {{al, r4, r1, plus, r2, PostIndex}, 1343 "al r4 r1 plus r2 PostIndex", 1347 {{al, r0, r7, plus, r5, PostIndex}, 1348 "al r0 r7 plus r5 PostIndex", 1352 {{al, r3, r6, plus, r10, PostIndex}, 1353 "al r3 r6 plus r10 PostIndex", 1357 {{al, r7, r3, plus, r6, PostIndex}, 1358 "al r7 r3 plus r6 PostIndex", [all...] |
H A D | test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 1335 {{al, r9, r4, plus, r0, ROR, 19, PostIndex}, 1336 "al r9 r4 plus r0 ROR 19 PostIndex", 1340 {{al, r2, r3, plus, r8, LSL, 10, PostIndex}, 1341 "al r2 r3 plus r8 LSL 10 PostIndex", 1345 {{al, r11, r14, plus, r5, LSL, 31, PostIndex}, 1346 "al r11 r14 plus r5 LSL 31 PostIndex", 1350 {{al, r5, r14, plus, r9, ROR, 11, PostIndex}, 1351 "al r5 r14 plus r9 ROR 11 PostIndex", 1355 {{al, r6, r1, plus, r5, LSL, 11, PostIndex}, 1356 "al r6 r1 plus r5 LSL 11 PostIndex", [all...] |
H A D | test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 1335 {{al, r9, r0, plus, r4, LSR, 26, PostIndex}, 1336 "al r9 r0 plus r4 LSR 26 PostIndex", 1340 {{al, r2, r1, plus, r9, LSR, 30, PostIndex}, 1341 "al r2 r1 plus r9 LSR 30 PostIndex", 1345 {{al, r11, r7, plus, r8, LSR, 13, PostIndex}, 1346 "al r11 r7 plus r8 LSR 13 PostIndex", 1350 {{al, r5, r11, plus, r3, ASR, 2, PostIndex}, 1351 "al r5 r11 plus r3 ASR 2 PostIndex", 1355 {{al, r5, r12, plus, r11, LSR, 27, PostIndex}, 1356 "al r5 r12 plus r11 LSR 27 PostIndex", [all...] |
H A D | test-disasm-a32.cc | 676 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PostIndex)), 680 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xff123, PostIndex)), 683 COMPARE_A32(Ldr(r0, MemOperand(r1, -0xff123, PostIndex)), 687 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xfff12, PostIndex)), 691 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xff12, PostIndex)), 694 COMPARE_T32(Ldr(r0, MemOperand(r1, -0xff12, PostIndex)), 724 MUST_FAIL_TEST_BOTH(Ldr(r0, MemOperand(r0, 0xfff12, PostIndex)), 760 COMPARE_T32(Ldr(r0, MemOperand(r1, minus, r2, PostIndex)), 774 COMPARE_A32(Ldr(pc, MemOperand(r0, r0, PostIndex)), "ldr pc, [r0], r0\n"); 775 COMPARE_T32(Ldr(pc, MemOperand(r0, r0, PostIndex)), [all...] |
/external/vixl/examples/aarch64/ |
H A D | add2-vectors.cc | 57 __ Ld1(v1.V16B(), MemOperand(x1, 16, PostIndex)); 59 __ St1(v0.V16B(), MemOperand(x0, 16, PostIndex)); 72 __ Ldrb(w6, MemOperand(x1, 1, PostIndex)); 74 __ Strb(w5, MemOperand(x0, 1, PostIndex));
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H A D | crc-checksums.cc | 57 __ Ldrb(w3, MemOperand(x2, 1, PostIndex));
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H A D | sum-array.cc | 49 __ Ldrb(w3, MemOperand(x2, 1, PostIndex)); // w3 = *(x2++)
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/external/vixl/test/aarch64/ |
H A D | test-trace-aarch64.cc | 169 __ ldp(w23, w24, MemOperand(x1, 8, PostIndex)); 172 __ ldp(x25, x26, MemOperand(x1, 16, PostIndex)); 175 __ ldpsw(x27, x28, MemOperand(x1, 8, PostIndex)); 178 __ ldr(w29, MemOperand(x1, 4, PostIndex)); 181 __ ldr(x2, MemOperand(x1, 8, PostIndex)); 184 __ ldrb(w3, MemOperand(x1, 1, PostIndex)); 187 __ ldrb(x4, MemOperand(x1, 1, PostIndex)); 190 __ ldrh(w5, MemOperand(x1, 2, PostIndex)); 193 __ ldrh(x6, MemOperand(x1, 2, PostIndex)); 196 __ ldrsb(w7, MemOperand(x1, 1, PostIndex)); [all...] |
H A D | test-disasm-aarch64.cc | 1022 COMPARE(ldr(w0, MemOperand(x1, 4, PostIndex)), "ldr w0, [x1], #4"); 1023 COMPARE(ldr(w2, MemOperand(x3, 255, PostIndex)), "ldr w2, [x3], #255"); 1024 COMPARE(ldr(w4, MemOperand(x5, -256, PostIndex)), "ldr w4, [x5], #-256"); 1025 COMPARE(ldr(x6, MemOperand(x7, 8, PostIndex)), "ldr x6, [x7], #8"); 1026 COMPARE(ldr(x8, MemOperand(x9, 255, PostIndex)), "ldr x8, [x9], #255"); 1027 COMPARE(ldr(x10, MemOperand(x11, -256, PostIndex)), "ldr x10, [x11], #-256"); 1028 COMPARE(str(w12, MemOperand(x13, 4, PostIndex)), "str w12, [x13], #4"); 1029 COMPARE(str(w14, MemOperand(x15, 255, PostIndex)), "str w14, [x15], #255"); 1030 COMPARE(str(w16, MemOperand(x17, -256, PostIndex)), "str w16, [x17], #-256"); 1031 COMPARE(str(x18, MemOperand(x19, 8, PostIndex)), "st [all...] |
H A D | test-assembler-aarch64.cc | 2414 __ Ldr(w1, MemOperand(x24, 4096 * sizeof(src[0]), PostIndex)); 2415 __ Str(w1, MemOperand(x25, 4096 * sizeof(dst[0]), PostIndex)); 2516 __ Ldr(w0, MemOperand(x17, 4, PostIndex)); 2517 __ Str(w0, MemOperand(x18, 12, PostIndex)); 2518 __ Ldr(x1, MemOperand(x19, 8, PostIndex)); 2519 __ Str(x1, MemOperand(x20, 16, PostIndex)); 2520 __ Ldr(x2, MemOperand(x21, -8, PostIndex)); 2521 __ Str(x2, MemOperand(x22, -32, PostIndex)); 2522 __ Ldrb(w3, MemOperand(x23, 1, PostIndex)); 2523 __ Strb(w3, MemOperand(x24, 5, PostIndex)); [all...] |
/external/v8/src/arm/ |
H A D | codegen-arm.cc | 76 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); 80 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); 82 __ vst1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(dest, PostIndex)); 83 __ vst1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(dest, PostIndex)); 88 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); 89 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); 91 __ vst1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(dest, PostIndex)); 92 __ vst1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(dest, PostIndex)); 93 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); 94 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); [all...] |
H A D | macro-assembler-arm.h | 419 ldr(src2, MemOperand(sp, 4, PostIndex), cond); 420 ldr(src1, MemOperand(sp, 4, PostIndex), cond); 431 ldr(src3, MemOperand(sp, 4, PostIndex), cond); 436 ldr(src1, MemOperand(sp, 4, PostIndex), cond); 455 ldr(src4, MemOperand(sp, 4, PostIndex), cond); 464 ldr(src1, MemOperand(sp, 4, PostIndex), cond);
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/external/v8/src/arm64/ |
H A D | codegen-arm64.cc | 164 __ Ldr(x13, MemOperand(src_elements, kPointerSize, PostIndex)); 168 __ Str(d0, MemOperand(dst_elements, kDoubleSize, PostIndex)); 245 __ Str(the_hole, MemOperand(dst_elements, kPointerSize, PostIndex)); 267 __ Ldr(x13, MemOperand(src_elements, kPointerSize, PostIndex)); 278 __ Str(heap_num, MemOperand(dst_elements, kPointerSize, PostIndex)); 286 __ Str(the_hole, MemOperand(dst_elements, kPointerSize, PostIndex));
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/external/v8/src/regexp/arm64/ |
H A D | regexp-macro-assembler-arm64.cc | 255 __ Ldrb(w10, MemOperand(characters_address, 1, PostIndex)); 258 __ Ldrh(w10, MemOperand(characters_address, 2, PostIndex)); 336 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); 337 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); 488 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); 489 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); 492 __ Ldrh(w10, MemOperand(capture_start_address, 2, PostIndex)); 493 __ Ldrh(w11, MemOperand(current_position_address, 2, PostIndex)); 894 MemOperand(output_array(), kPointerSize, PostIndex)); 915 MemOperand(base, -kPointerSize, PostIndex)); [all...] |
/external/v8/src/regexp/arm/ |
H A D | regexp-macro-assembler-arm.cc | 254 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); 255 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); 389 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); 390 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); 393 __ ldrh(r3, MemOperand(r0, char_size(), PostIndex)); 394 __ ldrh(r4, MemOperand(r2, char_size(), PostIndex)); 769 __ str(r2, MemOperand(r0, kPointerSize, PostIndex)); 770 __ str(r3, MemOperand(r0, kPointerSize, PostIndex)); 1178 MemOperand(backtrack_stackpointer(), kPointerSize, PostIndex));
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/external/vixl/src/aarch32/ |
H A D | operands-aarch32.cc | 519 if (operand.GetAddrMode() == PostIndex) { 550 if (operand.GetAddrMode() == PostIndex) {
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H A D | macro-assembler-aarch32.cc | 2065 case PostIndex: 2079 MemOperand(rn, load_store_offset, PostIndex)); 2162 case PostIndex: 2291 case PostIndex: 2305 MemOperand(rn, load_store_offset, PostIndex)); 2338 case PostIndex: 2438 case PostIndex: 2511 case PostIndex:
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/external/vixl/src/aarch64/ |
H A D | operands-aarch64.cc | 437 VIXL_ASSERT((addrmode == Offset) || (addrmode == PostIndex)); 481 bool MemOperand::IsPostIndex() const { return addrmode_ == PostIndex; }
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